Future trends for SiP In Medical Implant Applications

Transcription

1 Future trends for SiP In Medical Implant Applications Piers Tremlett, Zarlink Semiconductor NMI at TWI, 12 Dec 07

2 A case study This presentation uses Zarlink s Medical RF device To consider potential embedded component designs The main objective is to reduce SiP size And ensure suitability for Pacemaker applications [Page 1]

3 Introduction Introduction to the Packaging Foundry at Zarlink Design requirements for RF SiP in Pacemakers Zarlink s embedded component research projects Review of other embedded component design options The future of embedded component in Zarlink RF SiP s [Page 2]

4 Introduction to Zarlink Microelectronics Packaging Foundry

5 Zarlink Microelectronics Packaging foundry 75% packages for implantable medical devices 25% merchant subcontract packaging Module and Packaging design 75 employees Based in Caldicot, South Wales Part of a multinational company Zarlink Semiconductor [Page 4]

6 History 1983 Established as manufacturer of ceramic hybrid circuits SLIC for telecom applications 2001 Packaging facility Specialist packaging Mainly Medical Microelectronics [Page 5] CONFIDENTIAL

7 Design requirements for the Pacemaker

8 Example Conditions and Implants Implantable electronic devices treat these conditions: Profound Deafness Cochlear Implant Heart conditions Pacemakers Diabetes Insulin pumps Paralysis Stroke victims Dropped Foot Implant [Page 7]

9 Pacemakers Pacemakers dominate the implant market It is the most effective was to treat arrhythmia Relatively young people affected by arrhythmia Arrhythmia is a common condition Most other implant devices: Too expensive or risky Only the elderly affected Rare condition, low volume [Page 8]

10 Pacemaker requirements for new RF SiP design technologies Space is a premium SiP format Narrow long PCB circuits Low profile SMT format Reliability Provide RF shielding? Component protection - handling Reduced cost [Page 9]

11 Zarlink s embedded component research projects

12 Zarlink research projects SHIFT Active die embedded in flex EU FP6 integrated project, 1 st demonstrator due shortly CiP Embedded die in PCB Zarlink funded project Collaboration with Technical University of Berlin ADEPT Embedded planar passive components Emphasis on characterisation and simulation Collaboration with TWI [Page 11]

13 Difficulties for embedded components Full PCB manufacturing panels sizes are used 12 x 18 panel size or more Much larger than normal PCBs Very demanding accuracies are required IC dimensions PCB manufacturers lack Pick and place machines / skills Test equipment and skills eg for testing active die Lack of equipment for large area PCBs Pick and place machines Testers [Page 12]

14 SHIFT project concept

15 Objectives of SHIFT To Embed active die on Flex Die Flex substrate To provide working demonstrators To evaluate reliability [Page 14]

16 Stud Bump the die (Use solder bumps at higher volumes?) Image:- courtesy of Thales

17 Assemble die to Flex Die Gold stud bump Copper tracking Flex Thermo compression bond die to flex substrate Underfill the die (Reflow solder solder bumps at higher volume?) [Page 16]

18 Laminate flex/die with Prepregs 2 nd Prepreg Create Vias 1 st Prepreg with holes for die Polyimide Flex substrate Image:- courtesy of RL Design [Page 17]

19 Final Assembly Place SMT components Fold Module [Page 18]

20 Will SHIFT meet Zarlink RF module objectives? Space / Format Will reduce module size Will suit module with flex tail Reliability Testing not yet started RF shielding / component protection Partial shielding and component protection - might require a shield Reduced cost Flex tail reduces number of circuits per panel Known Good Die issue / Novel process low yields? Limited supplier base higher cost [Page 19]

21 CiP Chip in Polymer

22 Objectives of CiP 20mm 9mm Reduce RF module SiP to less than half the current size Surface mountable LGA format Demonstrate a working RF transciever [Page 21]

23 CiPs structure Based upon FR4 core Plated via connections to die Pictures courtesy of TUB [Page 22]

24 Plate the die wire bond pads Bond pads must be plated to stop the laser beam Laser beam drills to create via hole Electroless Ni/Au Or Electroplated Cu [Page 23] Pictures courtesy of TUB and IMEC

25 CIPS embedded die RCC [Page 24]

26 CiPS module SMT module Working RF module SMT components Embedded die LGA solder pads [Page 25]

27 Will CiP meet Zarlink RF module objectives? Space / Format Will reduce module size Will suit low profile SMT format Reliability 3000 thermal cycles Vibration and shock MSL 3, MSL 2 soon Reduced cost Extra cost to plate the die pads Known Good Die issue / Novel process low yields? Limited supplier base high prices? [Page 26]

28 Other embedded component technologies Embedded Passives

29 Planar embedded passive components Laminate layer capacitors, inductor and resistors Compatible with PCB manufacturing techniques Inductors Planar spiral inductors to be investigated in ADEPT project Could be etched into available copper area in RF module Resistors Good for PCBs with many resistors with wide tolerances Zarlink RF module has 1 resistor cost / size benefit? Capacitors Good for decoupling ground/ power planes on large PCBs Capacitance too low for Zarlink RF module [Page 28]

30 Embed SMT type passives? This structure is currently used in products in Japan PCB yield loss involves cheap passives and not die Would costs be lower? Flip chip SMT type passives [Page 29]

31 Integrate thin film passive IC Die with thin film passives on it surface Embed two die to produce smallest format? Lowest yield format expensive? RF die Thin film passives die [Page 30]

32 Potential Zarlink module design A road map design

33 Potential Zarlink module design Normal PCB and SMT assembly Then laminate and encapsulate both sides Use etch and via process to provide: Integral shield and component protection LGA pads [Page 32]

34 Potential Zarlink module reviewed Size / format Reduced size Low profile LGA Reliability Similar to CiP RF shielding / Component protection An integral shield Protect components Reduced cost Starts with normal SMT process at Zarlink Completed by PCB manufacturer Individual components returned to Zarlink [Page 33]

35 Further development needed Need to complete CiP and Shift Projects Need to develop a process to embed SMT type passives Need to work with an interested PCB supplier [Page 34]

36 Still some way to go before Zarlink develops what it wants! However, these are early stage projects that will provide us with an exciting roadmap to deliver the next generation of miniaturisation.

37 Conclusion PCB, IC and SMT technology are converging Zarlink intends to understand these new design technologies And be involved in new packaging development projects Currently the supply chain is immature Few suppliers Equipment needs developing ( eg large area pick and place machines) Specialist passives need developing for embedding Zarlink is investigating embedded components for SiP to enable miniaturisation but high yields and lower costs need to be demonstrated [Page 36]

38 ZARLINK SEMICONDUCTOR Piers Tremlett