SingMai Electronics PT55. Advanced Composite Video Interface: Encoder IP Core. User Manual. Revision th November 2016

Transcription

1 PT55 Advanced Composite Video Interface: Encoder IP Core User Manual Revision.8 11 th November 216 PT55 User Manual Revision.8 Page 1 of 32

2 Revisions Date Revisions Version First Draft Timing diagrams updated..2 Block diagram updated i standards added..3 IP core resource usage added. acvi description modified. Data transfer description added. Cable compensation description added. Simulation information added. Altera encryption description added FPGA resource use updated..4 Reg_clk port removed. Insertion test signal modified. Data transmit register locations corrected. Register address range changed to A[4:]. Text corrections and additions Luma interpolation added..5 Chroma interpolation filter modified. Subcarrier frequencies modified. acvi description modified. Data slicing schematic updated. Output interface schematic updated Verilog modules renamed..6 Some ports renamed. NTSC-M/PAL/NTSC-96H and PAL-96H standards added. SD chroma filters added. Input formatting added acvi.5 format added acvi.5 format removed. Changes to data transfer control. Changes to auto cable compensation. Additional luma interpolation filter added (for alternative analogue HD formats). Chroma interpolation filter redesigned..8 PT55 User Manual Revision.8 Page 2 of 32

3 Contents Revisions... 2 Contents... 3 Tables... 3 Figures Introduction PT55 Module description Signal Interconnections acvi Overview Technical Overview...12 PT55_encoder.v...12 Register_control.v...12 Yin.v...12 Cin.v...15 SPG.v...17 Modulator.v Preemphasis.v acvi Cable Compensation Data Transfers Register interface Register descriptions Output Interface Altera Encrypted files Tables Table 1 PT55 Altera FPGA resource requirements... 5 Table 2 PT55 Verilog file structure....6 Table 3 PT55 Input/Output signals...8 Table 4 acvi supported video formats Table 5 PT55 Input video formats...13 Table 6 Line and subcarrier frequencies (acvi and SD) Table 8 Register Descriptions Table 9 Encrypted file naming Figures Figure 1 PT55 Block schematic Figure 2 acvi Spectrum Figure 3 PT55 Block diagram Figure 4 Input chroma demultiplexing modes...13 Figure 5 Luma interpolator filter frequency response (acvi) Figure 6 NTSC/PAL Luma interpolation filter (27MHz) Figure 7 Luma interpolator filter frequency response (Control Register 2, bit 4 = '1') Figure 8 Cb/Cr Interpolation filter response (acvi) Figure 9 Cb/Cr Interpolation filter response (NTSC/PAL) Figure 1 72p/6 Horizontal Timing Figure 11 72p/5-6Hz Vertical Timing Figure 12 18p/3 Horizontal Timing Figure 13 18p/25-3Hz Vertical Timing Figure 14 Sinx/x Filter response....2 Figure 15 Pre-emphasis filter response - RG59 cable....2 Figure 16 acvi output, 3MHz sweep (Pre-emphasis = minimum) PT55 User Manual Revision.8 Page 3 of 32

4 Figure 17 acvi output, 3MHz sweep (Pre-emphasis = maximum)...21 Figure 18 Coaxial cable frequency response Figure 19 Insertion test signal Figure 2 Data transfer protocol Figure 21 Data slicing schematic Figure 22 PT55 Register control Figure 23 PT55 output interface schematic...31 PT55 User Manual Revision.8 Page 4 of 32

5 1. Introduction PT55 is an acvi encoder IP (intellectual property) core compatible with the acvi Advanced Composite Video Interface. acvi is a method to transmit high quality HD video over existing coaxial/twisted-pair cable networks or allow the use of less expensive RG-59/UTP cable in long distance installations. The encoder IP accepts separate YCbCr 4:2:2 digital component data together with its video clock (74.25MHz/ MHz) and horizontal and vertical timing signals, which it encodes to a single 1 bit straight binary composite output for driving a suitable DAC (digital to analogue converter) and amplifier. PT55 supports 72p-25Hz/3Hz/5Hz/59Hz/6Hz, 18p- 24Hz/25Hz/29Hz/3Hz and 18i-5Hz/59Hz/6Hz HD video formats. In addition, the PT55 will also encode 525i and 625i formatted data to NTSC-M/NTSC-96H or PAL/PAL-96H formats respectively (13.5MHz/18MHz clock inputs). Control and status registers are written to and read from using a conventional 8 bit wide microprocessor interface. PT55 also supports the bidirectional transfer of data between acvi transmitter and receiver. The intellectual property block is provided as RTL compliant Verilog-21 source code for FPGAs from all vendors or for ASICs. Typical resource usage for an Altera FPGA is shown in Table 1. Logic Cells Memory Bits M9K blocks 9x9 Multipliers 18x18 multipliers Table 1 PT55 Altera FPGA resource requirements An approximate equivalent for ASIC resource usage is LCs (logic cell only compile for Altera FPGA) x 14 ~ 172k 2 input NAND gate equivalent. The memory is 13kb of single port ROM (512 x 24) and 2kb of single port ROM (128 x 1). PT55 User Manual Revision.8 Page 5 of 32

6 2. PT55 Module description The PT55 acvi encoder IP core comprises 1 Verilog modules in a hierarchical structure, (see Table 2). acvi_encoder.v acvi_register_control.v acvi_cin.v acvi_yin.v acvi_tx_spg.v acvi_modulator.v acvi_preemphasis.v acvi_data.v Table 2 PT55 Verilog file structure. acvi_test_waveform.v Tx_SinCos_ROM.v The top level file is acvi_encoder.v which, in turn, calls seven of the other modules. acvi_modulator.v calls a third level file, Tx_SinCos_ROM.v and acvi_yin.v calls acvi_test_waveform.v. PT55 User Manual Revision.8 Page 6 of 32

7 3. Signal Interconnections The PT55 signal interconnect diagram is shown in Figure 1. Figure 1 PT55 Block schematic. The signal descriptions are shown in Table 3, below. Signal Clock Clock2x C_enable RESETn Inputs Description Luma pixel clock input (74.25MHz/ MHz for acvi, 13.5MHz for NTSC-M/PAL, 18MHz for NTSC-96H/PAL- 96H). All data inputs should be valid at the rising edge of this clock. Twice the Clock input frequency (148.5MHz/ MHz/27MHz/36MHz). Output data is valid on the rising edge of this clock. Rising edges of Clock and Clock2x should be coincident. Used for demultiplexing the 4:2:2 2 bit input (see input formatting on p.13). Asynchronous active low reset signal. Asserting this input PT55 User Manual Revision.8 Page 7 of 32

8 sets all the control registers to their default value and resets all registers. A[4:] Control address bus input used to select the control register to be written to/read from. Din[7:] Control data input bus. PT55_CSn Control chip select input, active low. Used in combination with the WRn input to control writing to the control registers. PT55_WRn Active low write enable input. Used in combination with the CSn input to control writing to the control registers. HSync_in Horizontal synchronization input. For 72p/6Hz operation this input is at 45kHz. Active low input, the falling edge is the H timing reference point. This input must be at least 4 Clock periods wide. (See input formatting on p.12). VSync_in Vertical synchronization input. For 72p/6Hz operation this input is at 6Hz. Active low input, the falling edge is the V timing reference point. This input must be at least 4 Clock periods wide. (See input formatting on p.12). FSync_in Frame synchronization input. For interlaced inputs this input indicates the first (= ) or second (= 1 ) field of the frame. For non-interlaced inputs this input should be tied to. (See input formatting on p.12). Y_in[9:] Y (luma) input or BT112 MSB input to the encoder. If luma, the input is straight binary, blanking level is 64 1 and peak level The data input should be valid at the rising edge of Clock. Y_in[9] is the MSB. If the input is 8-bits wide, the bottom 2 bits should be tied to. (See input formatting on p.13). Cb_in[9:] Cb (B-Y chroma) input or Cb/Cr multiplexed input to the encoder or BT112 LSB. If chroma the input is offset binary, blanking level is The data input should be valid at the rising edge of Clock. Cb_in[9] is the MSB. If the input is 8- bits wide, the bottom 2 bits should be tied to. (See input formatting on p.13). Cr_in[9:] Cr (R-Y chroma) input to the encoder. The input is offset binary, blanking level is The data input should be valid at the rising edge of Clock. Cr_in[9] is the MSB. If the input is 8-bits wide, the bottom 2 bits should be tied to. (See input formatting on p.13). Data_in Sliced data input from the acvi receiver (see Chapter 7). Outputs Signal Description Register_out[7:] Control output data bus. Outputs the control/status register data selected by the A[4:] bus. CSync Digital composite sync output. CVBS_out[9:] Encoded acvi/ntsc/pal output data. CVBS_out[9] is the MSB. The output is straight binary coded and is valid at the rising edge of Clock2x. Table 3 PT55 Input/Output signals PT55 User Manual Revision.8 Page 8 of 32

9 The Verilog instantiation of PT55 is shown below: PT55_encoder PT55_encoder_inst (.Clock(Clock_sig),.Clock2x(Clock2x_sig),.C_enable(C_enable_sig),.RESETn(RESETn_sig),.A(A_sig),.Din(Din_sig),.PT55_CSn(PT55_CSn_sig),.PT55_WRn(PT55_WRn_sig),.HSync_in(HSync_in_sig),.VSync_in(VSync_in_sig),.FSync_in(FSync_in_sig),.Y_in(Y_in_sig),.Cb_in(Cb_in_sig),.Cr_in(Cr_in_sig),.Data_in(Data_in_sig),.Register_out(Register_out_sig),.CSync(CSync_sig),.CVBS_out(CVBS_out_sig) ); // input Clock_sig // input Clock2x_sig // input C_enable_sig // input RESETn_sig // input [4:] A_sig // input [7:] Din_sig // input PT55_CSn_sig // input PT55_WRn_sig // input HSync_in_sig // input VSync_in_sig // input FSync_in_sig // input [9:] Y_in_sig // input [9:] Cb_in_sig // input [9:] Cr_in_sig // input Data_in_sig // output [7:] Register_out_sig // output CSync_sig // output [9:] CVBS_out_sig PT55 User Manual Revision.8 Page 9 of 32

10 4. acvi Overview The following is a brief overview of the acvi interface. The basic concept of the acvi interface is to build on the proven and reliable transport method of NTSC. NTSC transmissions are capable of transmitting more than 1km across RG-59 cable but the bandwidth is limited to 5MHz. Because the cable system is a closed system, it is only necessary for the transmitter and receiver to understand each other and we can modify the basic NTSC method to suit HD transmissions. There are two versions of acvi; first we will describe the full bandwidth version. According to the SMPTE-296M specification, HD (74.25MHz sampling) video transmission requires a luma bandwidth of 3MHz and chroma bandwidth of 15MHz. To save on system costs acvi supports the 3MHz luma bandwidth but constrains the chroma bandwidth to 7.5MHz (4:1:1 sampling). The colour difference signals are modulated onto a carrier in quadrature so they effectively use the same bandwidth: the chroma subcarrier is ~24.75MHz.. The high frequency luma and the modulated chroma overlap above 12.4MHz but because of the line to line phase relationship of the chroma, may be separated using a line comb filter (and also because of the use of single chip image sensors, there is usually little high frequency content to cause image artifacts). The effective bandwidth of the complete signal is therefore approximately 12.3MHz (chroma upper sideband + filter roll off) MHz or about 37MHz, setting a minimum sampling frequency of 2 x 37MHz or 74MHz. For convenience we choose 74.25MHz as a sampling frequency as this is related to the SMPTE272M standard; (see Figure 2). For transmission over 3m of RG-59 cable we can expect 18dB loss at higher frequencies 5MHz). However the synchronizing signals are at a much lower frequency where the loss is only about 1-2dB so reliable rastering of the received signal should always be assured. The peak to peak video level of acvi is 1.26V (1% colour bars) which maintains compatibility with any legacy SD equipment on the network and also allows common low-power 3.3V drivers to be used. Table 4 lists the currently supported video formats for acvi. Format Pixels/line Line F SC /F H Subcarrier frequency ratio 72p/25Hz kHz MHz 72p/3Hz kHz MHz 72p/5Hz kHz MHz 72p/59.94Hz kHz MHz 72p/6Hz kHz MHz 18p/24Hz kHz MHz 18p/25Hz kHz MHz 18p/29.97Hz kHz MHz 18p/3Hz kHz MHz 18i/5Hz kHz MHz 18i/59.94Hz kHz MHz 18i/6Hz kHz MHz Table 4 acvi supported video formats. 1 Input clock is MHz (else 148.5MHz). PT55 User Manual Revision.8 Page 1 of 32

11 Figure 2 acvi Spectrum. PT55 User Manual Revision.8 Page 11 of 32

12 5. Technical Overview A simplified block diagram of the PT55 encoder is shown in Figure 3. Figure 3 PT55 Block diagram. PT55_encoder.v This is the top level design file and it interconnects all the following modules. Register_control.v A conventional 8 bit microprocessor style control interface is used to write and read to the PT55 control registers. Details of the interface may be found in Chapter 8 and the register descriptions may be found in Chapter 9. Yin.v The PT55 can accept 3 different formats of video input as described in Table 5. Selection of the input format is made using Control register 2, bits [2:]. Input format Y_in[9:] Cb_in[9:] Cr_in[9:] Comments 4:4:4/4:2:2 Y input Cb input Cr input Separate Y/Cb/Cr inputs (3 bits). Y is clocked with Clock, Cb/Cr are clocked with Clock in 4:4:4 mode or with Clock if C_enable is 1 in 4:2:2 mode. Synchronising inputs are HSync_in, VSync_in and FSync_in (if interlaced). 4:2:2 Y input Cb/Cr input Not used Separate Y and multiplexed Cb/Cr inputs (2 bits). Y is clocked with Clock, Cb/Cr are clocked with Clock with either C_enable signaling which is Cb (= ) or Cr (= 1 ) or the demultiplexing signal PT55 User Manual Revision.8 Page 12 of 32

13 Input format Y_in[9:] Cb_in[9:] Cr_in[9:] Comments being derived from the HSync_in input Synchronising inputs are HSync_in, VSync_in and FSync_in (if interlaced). 4:2:2 BT112 input[19:1] (Y[9:]) BT112 input[9:] (Cb/Cr[9:]) Not used Table 5 PT55 Input video formats. Multiplexed Y/Cb/Cr inputs (2 bits). BT112 input is clocked with Clock. Synchronising inputs are extracted from the BT112 input (TRS). The two methods of demultiplexing the chroma in 2 bit mode are illustrated in Figure 4. Figure 4 Input chroma demultiplexing modes. If in acvi mode, the acvi test waveform (used for the automatic cable length compensation) is inserted on line 9 of the video input (see Chapter 6). The resulting luma signal is then interpolated from Clock frequency to Clock2x frequency using a 47 tap FIR filter: e.g. for NTSC/PAL the 13.5MHz Y input is interpolated to 27MHz and for acvi the 74.25MHz Y input is interpolated to 148.5MHz. The filter responses are shown below. PT55 User Manual Revision.8 Page 13 of 32

14 1 Inphase Filter Frequency Response Magnitude in db Frequency in MHz Figure 5 Luma interpolator filter frequency response (acvi). For NTSC-M and PAL (27MHz output) the same filter as for acvi is used, giving a passband of 5.25MHz and a stop band of 6.75MHz. For 96H operation (36MHz output) the passband is 7.2MHz. 1 Inphase Filter Frequency Response -1 Magnitude in db Frequency in MHz Figure 6 NTSC/PAL Luma interpolation filter (27MHz). PT55 User Manual Revision.8 Page 14 of 32

15 Control Register 2, bit 4, selects an alternative low pass filter for other analogue HD formats. The response of this filter is shown below. 1 Inphase Filter Frequency Response Magnitude in db Frequency in MHz Figure 7 Luma interpolator filter frequency response (Control Register 2, bit 4 = '1'). Cin.v The Cb and Cr inputs are conditioned according to the input format applied see Table 5. The Cb and Cr (chroma) inputs are offset binary with an expected blanking level of The inputs are latched on the rising edge of the Clock input. The Cb and Cr inputs are converted to 2 s complement format and then interpolated from half Clock frequency (4:2:2 mode) to Clock2x frequency in a 47-tap FIR filter which has a Gaussian response. For acvi the filter has a pass-band of 7.5MHz and a stop band attenuation of > -4dB at 12.3MHz. The filter response is shown below. PT55 User Manual Revision.8 Page 15 of 32

16 Inphase Filter Frequency Response -1 Magnitude in db Frequency in MHz Figure 8 Cb/Cr Interpolation filter response (acvi). For NTSC and PAL operation the chroma filter passband is set at 1.7MHz and the stop band is 3.375MHz - its response is shown in Figure 9. Inphase Filter Frequency Response -1 Magnitude in db Frequency in MHz Figure 9 Cb/Cr Interpolation filter response (NTSC/PAL). A separate set of coefficients is used for 96H mode (36MHz sampling), to produce the same response as that shown in Figure 9. Horizontal and vertical blanking is applied to the output. PT55 User Manual Revision.8 Page 16 of 32

17 SPG.v HSync_in (horizontal), VSync_in (vertical field) and FSync_in (frame if the input is interlaced) signals are used for picture synchronization or, in BT112 input mode, the embedded TRS timing signals are extracted from the input video data. The falling edge of the horizontal pulse input is used to reset a 12-bit counter clocked at Clock frequency. This is the H reference for the horizontal timing according to the SMPTE specifications and is the mid-point of the analogue tri-level synchronizing pulse. The outputs of this horizontal counter are decoded to produce blanking, synchronization, burst gate and broad pulses. The positions of these pulses are preset according to the selected video standard. Similarly the falling edge of the vertical pulse input is used to reset an 11-bit counter clocked at the beginning of each horizontal line (e.g. a line counter). The outputs from this counter are decoded to produce the vertical sync and blanking pulses. The positions of these pulses are preset according to the selected video standard. A composite sync pulse is formed from gated combinations of the horizontal, vertical and broad pulses. An analogue version of the digital pulse is also created using a look-up table, giving the edges an approximate raised cosine shape to avoid ringing during the transmission. The 1-9% transition time of the sync edges is approximately 215ns. The amplitude of the sync pulse can be set by Register $8. Figure 1 72p/6 Horizontal Timing. PT55 User Manual Revision.8 Page 17 of 32

18 Figure 11 72p/5-6Hz Vertical Timing. Figure 12 18p/3 Horizontal Timing. Figure 13 18p/25-3Hz Vertical Timing. PT55 User Manual Revision.8 Page 18 of 32

19 Modulator.v The chroma is frequency modulated onto a carrier, generated using a 32 bit ratio counter clocked from the 148.5MHz clock. The carrier seed is preset according to the video standard as shown in Tables 7 and 8. ratio phase change per line Fsc 1 pixels per line 148.5MHz θsc subcarrier seed Format Pixels/line Line frequency F SC /F H ratio Subcarrier Seed value 72p/25Hz kHz MHz p/3Hz kHz MHz p/5Hz kHz MHz p/59.94Hz kHz MHz p/6Hz kHz MHz p/24Hz kHz MHz p/25Hz kHz MHz p/29.97Hz kHz MHz p/3Hz kHz MHz i/5Hz kHz MHz i/59.94Hz kHz MHz i/6Hz kHz MHz NTSC-M kHz MHz PAL kHz (1/625) MHz NTSC-96H kHz MHz PAL-96H kHz (1/625) MHz Subcarrier clock is MHz. 2 Subcarrier clock is 148.5MHz. 3 Subcarrier clock is 27.MHz. 4 Subcarrier clock is 36.MHz. Table 6 Line and subcarrier frequencies (acvi and SD). The top 11 bits of this ratio counter (the phase word) are used by the demodulator to generate the sine and cosine waveforms. The subcarrier phase word is used to address a ROM containing sine and cosine values. A sample of the sine waveform is added, after shaping, to the back porch of the video signal to synchronise the chroma demodulator of the receiver. This colour burst is blanked during the field pulse. The interpolated Cb and Cr chroma inputs are multiplied by two scaling coefficients, U =.493Cb, V=.877Cr. These are multiplied in turn by the sine and cosine waveforms. The resulting U.sin(2πF sc.t) and V.cos(2πF sc.t) data is added together to form the final chroma signal. Preemphasis.v The luma has programmable gain and black level controls applied. The co-timed luma, sync, chroma and burst are added to create the final acvi output waveform. A sinx/x filter is applied to the composite signal to compensate for the high frequency sampling losses in the output DAC. The response of the sinx/x filter is shown in Figure 14. The sinx/x filter is a 7 tap FIR filter and may be bypassed using Control Register 2, bit 5. PT55 User Manual Revision.8 Page 19 of 32

20 1.4 Inphase Filter Frequency Response Magnitude in db Frequency in MHz Figure 14 Sinx/x Filter response. This resulting signal is then subjected to a variable degree of pre-emphasis with a maximum boost of >24dB at >5MHz. The pre-emphasis filter is a 5 tap FIR. The degree of pre-emphasis is dependent on the cable length and is designed to approximately compensate for the loss of >3m of RG-59 or UTP cable. The response of the pre-emphasis filter is shown below.. Inphase Filter Frequency Response Magnitude in db Frequency in MHz Figure 15 Pre-emphasis filter response - RG59 cable. PT55 User Manual Revision.8 Page 2 of 32

21 The resulting digital acvi encoded output should be input to a digital to analogue converter (DAC) and then buffered to drive the cable. Figure 16 acvi output, 3MHz sweep (Pre-emphasis = minimum). Figure 17 acvi output, 3MHz sweep (Pre-emphasis = maximum). PT55 User Manual Revision.8 Page 21 of 32

22 SingMai Electronics 6. acvi Cable Compensation The following description only applies to acvi video. All cables attenuate high frequencies more than low frequencies. The coaxial cable illustrated in Figure 18 (type RG-59) is typical of that used and shows that, at 5MHz (the upper frequency of acvi is 37MHz) an attenuation of 6.2dB/1m. acvi compensates for the frequency loss by applying pre-emphasis to the transmitted signal as this avoids the problem of providing tunable high frequency gain at the receiver which will also boost noise. To avoid the impracticality of boosting the high frequencies, the low frequencies are attenuated. The frequency response of the filter is closely matched to that of the cable attenuation so at the receiver it is only necessary to apply flat gain. The pre-emphasis filter is in the digital domain so it easy to change for different cable types and no external frequency dependent analogue networks, at either the transmitter of receiver, are necessary. Figure 18 Coaxial cable frequency response. To adjust the amount of pre-emphasis, a test waveform is inserted by the transmitter into the acvi signal on line 9 (for all supported video standards). The waveform allows the differential measurement of low and high frequencies across the cable, which is measured in the PT51 and used to control, via a data link, the degree of pre-emphasis applied at the transmitter. The waveform is shown in Figure 19. PT55 User Manual Revision.8 Page 22 of 32

23 SingMai Electronics Figure 19 Insertion test signal. The waveform comprises a white and black reference level, the amplitude of which is also the amplitude of the frequency burst. The frequency burst is a 24.75MHz sine wave (74.25/3 MHz). The difference between the white black amplitude and the peak-to-peak amplitude of the frequency burst allows the calculation of the cable attenuation at 25MHz and therefore the amount of preemphasis that needs to be applied. The degree of pre-emphasis required for the cable is transmitted from the receiver (PT51) to the transmitter (PT55) on line 8 during the vertical blanking interval. The format of the data transfer is the same as that used by the data transfer described in Chapter 7. The instruction word is set to 5 for the pre-emphasis value and the data byte is the degree of compensation, being no preemphasis and 255 being the maximum pre-emphasis. Figure 16 shows the acvi waveform with no pre-emphasis applied. Figure 17 shows the acvi waveform with maximum pre-emphasis. PT55 User Manual Revision.8 Page 23 of 32

24 SingMai Electronics 7. Data Transfers The following description only applies to acvi video. The acvi interface supports the bi-directional transfer of data between receiver and transmitter. The data is transmitted during the vertical blanking interval (Line 12 transmits from receiver to transmitter and Line 13 from transmitter to receiver). The format of the data is a 4 bit instruction word and an 8 bit data word. The instruction and data are not defined and may be set by the user. Each word is sent once per field/frame, so, for example, 6 words may be sent in each direction for the 72p/6 standard. To transmit data from receiver to transmitter, first the instruction word (C3-C in Figure 2) is written to Register $19. Next the data byte (D7-D in Figure 2) is written to Register $18. Register $19 should be read and bit examined. If this bit is 1 the previous data transfer is still in progress, if then the transfer may be initiated by writing any data to Register $19. The data is sent on Line 13 of the vertical blanking interval for all acvi standards. After the transmit data request the word is formatted as shown in Figure 22 and transmitted on the next line 13. After transmission the data busy bit is reset. Figure 2 Data transfer protocol. The data received from the receiver is the same format as the transmitted data (Figure 2). Figure 21 shows the schematic used on the PT55 evaluation module (SM6) to buffer and slice the vertical interval data sent from the acvi receiver to the transmitter. U1-A buffers the acvi video from the coaxial cable and U23 buffers the video from the UTP cable. J9 selects the input from either the coaxial connector (connect J9 pins 1-2) or the UTP connector (connect J9 pins 2-3). U1-B filters the input signal and C5 and D3 form a sync tip clamp to ensure stable DC levels into the data slicer. The data slicer is formed by comparator U1-D and buffered by U11 before being decoded by the PT55 acvi encoder IP core. PT55 User Manual Revision.8 Page 24 of 32

25 SingMai Electronics Figure 21 Data slicing schematic. The Data.v module examines the sliced data for the header flag. The receiver to transmitter data is inserted on Line 12. Once the header flag is detected, a bit clock is synchronized to the data and the data stream is decoded into the instruction word, data word and parity checks. The Instruction word may be read from Register $1C, the data word from Register $1B and the receiver status from Register $1D. To read data, first Register $1D, bit 7 should be examined if 1 it indicates new data has been received (and the received data parity check is OK). Register $1D also shows the status of the received instruction and data word parity. PT55 User Manual Revision.8 Page 25 of 32

26 SingMai Electronics Next the received instruction word should be read from Register $1C, and then the received data word from Register $1B. When Register $1B is read the new data flag (Register $1D bit 7) is reset. When the new data bit is set new received data will not be latched, preventing corruption of received data, but also possibly missing transmitted data if the data is not read often enough. PT55 User Manual Revision.8 Page 26 of 32

27 SingMai Electronics 8. Register interface Figure 22 shows the timing diagram for the register interface; it is a conventional microprocessor interface. Each register is selected via a 5 bit address bus. Writes to unused register locations are ignored. To write to the selected register the PT55_CSn (chip select) input must be asserted low and the A[4:] register address and the data for this register set up. The PT55_WRn input must then be driven low and high again: On the rising edge of this pulse the data is latched into the address selected. The PT55_CSn input should then be returned high. For the write to occur reliably the address (A[4:]) and data (Din[7:]) must be stable and valid during the low to high transition of the PT55_WRn pulse. The address input also selects the register data that is presented on the Register_out[7:] bus. This output is independent of the PT55_CSn or PT55_WRn inputs. Figure 22 PT55 Register control. PT55 User Manual Revision.8 Page 27 of 32

28 SingMai Electronics 9. Register descriptions Table 8 lists all of the control and status registers. All of the registers are 8 bit; unused register bits read back as zeros. Please note that some registers can be set to values that are illegal and will produce invalid outputs. Asserting the RESETn input sets the PT55 registers to their default values. Register Offset Register Name R/W $ Control 1 R/W $1 Control 2 R/W $5 Luma_scaling R/W $8 Sync_scaling R/W $9 Black_level R/W $1 Pre-emphasis gain R/W PT55 User Manual Revision.8 Bit Value Description Control Registers PT55 control 1 (video standard) 7:6 Not used. 5 S96H 4 SD_HDn 3: Video standard S96H SD_HDn Video standard[3:] Standard 72p p3 1 72p p p p p p p i i i6 1 NTSC-M 1 1 PAL 1 1 NTSC-96H PAL-96H PT55 control 2 7 Not used. 6 I set to 1 the automatic cable compensation is enabled. Else the pre-emphasis value is set manually using register $1. 5 If set to 1 the sinx/x filter is bypassed, else the filter is enabled. 4 Selects 1of 2 Y interpolation filter responses. ' selects acvi/ntsc/pal response, and 1 selects a 12MHz LPF response. 3 Not used. 2: Input format Description (see p.12). 3 bit separate Y/Cb/Cr, 4:4:4 sampling. 1 3 bit separate Y/Cb/Cr, 4:2:2 sampling 1 2 bit Y and multiplexed Cb/Cr, 4:2:2 sampling. Demultiplexing using C-enable bit Y and multiplexed Cb/Cr, 4:2:2 sampling. Demultiplexing using HSync_in. 1 2 bit multiplexed Y/Cb/Cr with embedded sync. Video Input 7: 8 bit unsigned value setting the amplitude of the output Y (luma) component. Default value = Value range = : 8 bit unsigned value setting the amplitude of the output composite sync waveform. Default value = Value range = : 8 bit signed value setting the DC offset value for active video (pedestal). Default value = 1. Value range = Output stage 7: Controls the degree of pre-emphasis applied to the acvi output Page 28 of 32

29 SingMai Electronics Register Offset Register Name R/W $18 $19 Tx Data word Tx Instruction word $1A Data transfer W 7: 7:4 3: 7: $1A Data busy R $1B Rx_Data_word R 7: $1C $1D Rx Instruction word Rx Status R 3: 7 $1E PE_Value R/W R/W Bit Value R :2 1 7: Description (in manual pre-emphasis mode Register $1 bit 6 = ). Default = = no pre-emphasis. Maximum pre-emphasis = Data Transfer Data word to be transmitted from receiver to transmitter. Not used Data word to be transmitted from receiver to transmitter. A write (data value is not important) to this register will initiate the transfer of the Tx data instruction and Tx data word over the acvi interface. Bit [] of this register indicates if the data transfer is complete. If Bit[] is a 1, the transfer is pending. If the transfer is complete and a new transfer may be initiated. Received data word. (note, this register will not be updated if there is a parity error). Received instruction word. If set to 1, new data has been received. This bit is reset to when Register $1B is read. Set to zero. Received instruction word parity. Calculated instruction word parity. Set to zero. Received data word parity. Calculated data word parity. Received pre-emphasis value from receiver for auto cable length compensation. Table 7 Register Descriptions. PT55 User Manual Revision.8 Page 29 of 32

30 SingMai Electronics 1. Output Interface The output of the acvi encoder is 1-bit, straight binary, video data at 148.5MHz. This has to be converted to analogue using a digital to analogue converter. On the evaluation board (SM6 revision.2) an Analog Devices 1-bit DAC, the AD975, is used for this purpose. The FPGA also provides a 148.5MHz clock for the DAC. The differential analogue outputs from the DAC (1.V pk-pk) are then amplified by U21 and filtered (U9) to remove clock noise and driven through a cable impedance matching series resistor to the coaxial or twisted-pair cable. The schematics for this are shown in Figure 23. PT55 User Manual Revision.8 Page 3 of 32

31 SingMai Electronics Figure 23 PT55 output interface schematic. PT55 User Manual Revision.8 Page 31 of 32

32 SingMai Electronics 11. Altera Encrypted files For evaluation of the PT55 using an Altera FPGA, SingMai can provide encrypted Verilog files, specific to the computer you will compile the design on. For us to provide these files SingMai needs to have the NIC number of the computer you will be running Quartus on. The encrypted files name have a similar naming to the original files see Table 9. The files may be compiled and simulated exactly as the original files, the only difference is they cannot be viewed. Original module name acvi_encoder.v acvi_register_control.v acvi_cin.v acvi_yin.v Encrypted module name acvi_encoder_enc.v acvi_register_control_enc.v acvi_cin_enc.v acvi_yin_enc.v acvi_tx_spg.v acvi_modulator.v acvi_preemphasis.v acvi_data.v acvi_tx_spg_enc.v acvi_modulator_enc.v acvi_preemphasis_enc.v acvi_data_enc.v Tx_SinCos_ROM.v Tx_SinCos_ROM_enc.v acvi_test_waveform.v acvi_test_waveform _enc.v Table 8 Encrypted file naming. First copy the files across into your main project directory. It is necessary to add the design file to your project which is done by clicking on Project and then Add/Remove Files in Project (within Quartus II). See Figure Next we need to tell Quartus where to find the associated license file. Within Quartus click on Tools and then License Setup. Click on the browse button to the right of the License file dialog box and point to the PT55_license.dat file. The files should then be able to be compiled and simulated. The license file is unique to you but allows unlimited use of the PT55 across the whole family of Altera programmable devices. It will usually expire 2 months after the date of issue. Please contact SingMai if you need an extension of this. PT55 User Manual Revision.8 Page 32 of 32