PHY 351/651 LABORATORY 9 Digital Electronics The Basics

Transcription

1 PHY 351/651 LABORATORY 9 Digital Electronics The Basics Reading Assignment Horowitz, Hill Chap. 8 Data sheets 74HC10N, 74HC86N, 74HC04N, 74HC03N, 74HC32N, 74HC08N, CD4007UBE, 74HC76N, LM555 Overview Over the course of the semester, your efforts have focused primarily on analog electronics. Yet, at the end of the day, all the circuits you built were then measured and analyzed using digital electronics (including LabVIEW). Moreover, I think it s safe to say that digital electronics are the backbone (or at least one of the backbones) of the modern technology we are all accustomed too (including many laboratory instruments). Thus, we would be remiss if we did not spend some time in this course at least scratching the surface of this important topic. In the remaining formal laboratory periods, you will utilize LabVIEW and the digital functions of your DAQ card to learn some of the basics of digital electronics and operate several important digital components. Specifically, the learning objectives of the remaining lab activities are: 1. To become familiar with basic digital concepts and terminology 2. To become familiar with the digital input/output (I/O) functions of LabVIEW and the NI USB To learn about important digital circuit elements like gates, flip-flops, timers, counters, and registers 4. To gain appreciation of how digital circuits shape our modern world Equipment o PB-503 proto-typing board o 74HC10N Triple 3-input NAND gates o CD4007UBE CMOS Dual Complementary Pair Plus Inverter o 74HC86N Quadruple 2-input XOR gates o 74HC04N Hex Inverters o 74HC03N Quadruple 2-input NAND gates o 74HC32N Quadruple 2-input OR gates o 74HC08N Dual 2-input AND gates o 74HC76N Dual JK Flip-Flops o LM555 Timer o Possibly various resistors, capacitors and other elements that will be noted later Page 1

2 o NI USB-6003 PHY351/651 DIGITAL ELECTRONICS THE BASICS - LAB 9 o Hand-held digital multi-meter, banana cables, coaxial cables, and BNC-to-minigrabber adapters Activity 1 Basic Introduction to Digital Concepts & Terminology Before we start building digital circuits and using LabVIEW to control their operation, it is a good idea to review some basic concepts and terminology. (a) (b) Figure 1: (a) Illustration of the decimal number 131 represented using the binary number system. Each digit is a bit that can take on a value of 0 or 1 and represents a different power of two (increasing successively from right to left so that the right most digit is the least significant bit (LSB) and the leftmost digit is the most significant bit (MSB)). (b) The symbolic notation and truth tables for the three basic Boolean operations AND, OR and NOT. By and large, digital electronics use the binary number system for computation, counting and storage, and thus are based on circuit elements whose outputs can take on two physical states (an example would be the BJT transistor you operated as a switch in Lab 6). There are different conventions for labeling the two possible states of these systems: off/on, 0/1, F/T, -/+, etc. Regardless of what you decide to call them, everyone calls the underlying unit of information representing the state of the system a bit. If you string eight such systems together, they are referred to collectively as a byte. Page 2

3 Employing the binary (or base-2) number system, one can use such bits (or bytes) to represent any arbitrary number. For example, Figure 1a illustrates how one byte can be used to represent the number 131. Here, each bit (or digit) represents a different power of 2, with the bit on the far right, known as the least significant bit (LSB), representing 2 ", and the bit on the far left, known as the most significant bit (MSB), representing 2 #. In principle, one can thus encode any arbitrary number in a series of two-state systems (like a transistor) using this approach. One can also use the binary number system along with Boolean algebra to perform mathematical (a) Exclusive Or (XOR) (b) Figure 2: Adapted from Diefenderfer Figures 13.3 and (a) A full 2-bit adder based upon two AND gates, two XOR gates and an OR gate. Here C in is the input carry. (b) A 2-bit subtractor employing the same gates but with two additional NOT gates before the ANDs. Here B in is the input borrow. For Activity 3, you will need to construct and test one of these circuits. calculations. In order to do this, one needs a set of logic gates (Fig. 1b). The three gates, and their associated truth tables, shown in Fig. 1b are the basic Boolean operations AND, OR, and NOT (or invert). Additional gates useful for computation (which you will work with shortly) can be derived from this, including the NAND (NOT AND), the NOR (NOT OR), and the XOR (exclusive OR, which is equivalent to (X AND NOT Y) OR (NOT X AND Y) ). I would like to make a quick note on the symbolic representation of these important gates: NOT X is Page 3

4 represented as X; X AND Y is represented with X Y; X OR Y is represented with X Y; and X XOR Y is represented with X Y or equivalently as (X Y) (X Y). The physical implementation of such gates can be readily achieved using an array of transistors in an integrated circuit (IC) for instance, remember the BJT-transistor-based NOR gate that you constructed and tested in Lab 6. Figure 2 shows examples of how addition and subtraction can be performed and implemented in a circuit using the basic and derived Boolean operations (and the corresponding logic gates). (a) TTL Voltage Ranges (b) CMOS Voltage Ranges V "" ~ 5.0 V V ## Logical One 2V ## /3 Logical One 2.0 V V ## /3 0.8 V 0 V Logical Zero 0 V Logical Zero Figure 3: General voltage thresholds for logical zero and logical one in (a) TTL and (b) CMOS devices. Note, V dd can range from 3V to 18V. (Thus be sure to look at the specs before powering such devices up!) You will have the opportunity in Activity 3 to construct and verify the operation of one of these. (either a 2-bit full adder, Fig. 2a, or a 2-bit full subtractor, Fig.2b). Before proceeding with the operation of digital components and circuits, we address one final consideration; namely, how 0 s and 1 s are physically defined. From your experience working with the BJT switch and NOR gate in Lab 6, it might occur to you that the definition of these two states is not so clear cut for instance, there are a range of voltages that cause the transistor to saturate (output state 0) and cut-off (output state 1); as well, the value of the output voltage depends on the value of the supply voltage used; moreover, different types of transistors, like BJTs versus MOSFETs, are likely to have different power supply voltages and output levels. In a nutshell, there could be many different values of transistor input/output voltages to represent the 0 and 1. Standard definitions for logical 0 and 1 are thus needed in order to efficiently and reproducibly string together multiple transistors to make a logic gate or multiple logic gates to perform computations. And of course, over the years such standards for defining logical 0 and 1 in IC s have been developed in correspondence with the development of the various transistor technologies. Currently, the two most widely used logic families are TTL (transistor-transistor logic; based upon arrays of BJTs and other discrete components) and CMOS (complementary Page 4

5 PHY351/651 DIGITAL ELECTRONICS THE BASICS - LAB 9 metal-oxide-semiconductor logic; based upon arrays of FETS). For TTL, voltages range from 0.0 V to the supply voltage V AA, where V AA ~ 5V. As such, the range of 0.0V to 0.8V represents logical zero, and the range of ~2V to 5 V represents logical one (Fig. 3a). For CMOS, the voltage scales are set by the drain supply voltage V BB, which can vary from 3V to 18V. The corresponding range for logical zero is 0V to 1/3V BB, and the range for logical one is between 2/3V BB and V BB (Fig. 3b). In general, CMOS and TTL (as well as other logic families) are not compatible. However, some CMOS devices are engineered to be TTL compatible (like the 74HC series devices we will be using today), and there are ICs manufactured for interfacing between the different families. For Activity 1, please complete the following exercises: 1. Work out the truth table for the 3-input NAND gate. Then reproduce this truth table using the 74HC10N, which is a CMOS-based, TTL-compatible triple 3-input NAND chip. 2. Implement a 2-input AND gate using the 3-input NAND chip and an inverter, which can be found either on the CD4007UBE, or the 74HC05N, or the 74HC04N, or you can use one NAND gate wired as inverter. 3. Work out the truth table for the XOR gate. Then verify the truth table for such a gate using the 74HC86N IC. To carry out the experimental portion of these exercises, you should use the 503 prototyping board and its digital switches and indicators (plus the proper power supply). As always, be sure to look at the specs before working with any of these chips. **For your lab report: Include the truth tables for the 3-input NAND and 2-input XOR. And discuss whether you were able to reproduce these tables. Activity 2 Digital I/O with LabVIEW and the PCI-6023/24E In addition to performing operations on analog signals, the NI USB-6003 DAQ also offers options for digital input/output (I/O). Specifically, there is a single digital port (also called a digital channel in LabVIEW) which contains 8 lines that can be individually configured, through MAX or through LabVIEW s Digital I/0 VI s, to either read or write a bit of data. On the USB- 6003, as you have already seen there are also digital I/O channels for triggering and timing functions, which can be controlled with LabVIEW VI s. In this lab activity, you will learn how to use LabVIEW to perform basic digital I/O functions with the USB Before you get started on the exercises below, there are a couple important pieces of information to note. (1) First, the digital lines on the 6003 are denoted in spec sheets by P0.<0..7>. (2) There are Digital I/O VI s that can be found on the Functions Palette; I will leave it to you to find them, but as before with the Analog I/O, there are Easy, Intermediate, and Advanced level VI s; for instance the Easy level VI s can simply be set up using Data Acquisition Assistant. In this activity, it s your choice with which ones you work. For Activity 2, please do the following exercises: 1. Use LabVIEW to output a 4-bit number of your choice to and light up the LEDs on the the PB503 to verify the logical state; when you do this, be sure to provide a ground Page 5

6 connection between the systems). There are several different ways to input the 4-bit number of your choice. I would first like you to do so by using 4 Boolean LED controls on the front panel of the VI. After you ve gotten this to work successfully, you should try simply typing an integer into a digital control. 2. Next use LabVIEW to output in succession all integers from 1 to 255 and have them displayed on your LED indicators. 3. Afterwards use LabVIEW to configure a single digital line to output a square TTL wave with frequency and phase of your choice. 4. Finally, use LabVIEW to read four digital lines and display the logic levels on LED indicators. Demonstrate that this works by setting the input digital signals using the logic switches on the PB503. **For your lab report: Include a screenshot of the front panel and diagram of each of the VI s in this activity. Activity 3 The 2-Bit Full Adder and Subtractor In this activity, you will take what you learned about logic gates in Activity 1 and combine that with what you learned about digital I/O with LabVIEW in Activity 2 in order to implement an important mathematical operation either addition or subtraction of two numbers. Specifically, you have the option of implementing either a full 2-bit adder or a 2-bit subtractor (Figs. 2a and 2b). Before implementing either of these circuits, it s helpful to understand how logic gates can be used to perform computation. Figure 4 illustrates what is known as a half adder; the figure also includes the associated truth table for the computation - I should note that the only difference in operation between the full adder and the half adder is that the full adder is capable of accepting a carry from a previous stage in the circuit. You should spend some time working through the truth table for the half adder on your own and also spend time understanding how the table represents the addition of two bits. It may be helpful to note that binary addition works the same way as decimal addition except that each digit can only take on two values. Thus, for example, = 00; and = 01; but = 10 (a 1 gets carried to the next significant digit). To proceed with Activity 3: (1) Choose either the full adder or the subtractor. (2) Work through the truth table for the circuit (for an input carry of both 0 and 1). (3) Then build the circuit on the PB503. (4) Use LabVIEW to apply the input bits A and B and to measure the output bits Sum and Carry. (5) Verify the truth table for the circuit. Note that some of the ICs that you use might require an external pull up resistor on their outputs, so be sure to read the datasheets carefully. Finally, this circuit (either the adder or the subtractor) is probably the most complicated circuit that you have constructed and operated thus far in the class. So don t get discouraged if it takes a while to debug everything and have your circuit operating correctly. When you re finished, you ll probably be happy to know that if you ever need to build an adder or subtractor in the future, you won t need to go to the lengths you did today you can simply buy an IC that does the task for you (and with a much larger number of bits!). Page 6

7 Figure 4: Taken from Diefenderfer Figure The truth table and schematic of a half adder. Be sure to fully understand this circuit before proceeding with construction of the full adder. **For your lab report: Include the truth table for the circuit that you decide to construct (either the full adder or the subtractor), and discuss the operation of the circuit. Discuss whether your circuit operated in the manner that you expected. Activity 4 Flip-Flops Flip-flops (FF) are essential building blocks in digital circuits. They can be built from basic gates, and have many applications, including use as basic memory elements, as components in counters, and as elements for transferring bits of data in shift registers. In this activity, you will initially build and operate several important digital flip-flops using an array of NAND gates. You will then operate and characterize the widely-used and versatile JK flip-flop. These initial sub-activities will serve to provide you with an understanding of how flip-flops function, what their truth tables are, etc. Then in the final two sub-activities, you will utilize JK flip-flops to build a count-to-16 binary counter and a 4-bit shift register. The clocked RSFF (reset-set flip-flop) Figure 5 illustrates the first flip-flop that you will build and characterize. This circuit is known as the clocked reset-set flip-flop (RSFF) - it is also known as a gated set-reset latch. To understand how the circuit functions, first notice that it is composed solely of NAND gates. The first set of two NAND gates accepts three input signals: S (SET), R (Reset), and C (Clock), with the Clock signal applied to both NANDs. The outputs of these first two NANDs are routed to Page 7

8 Figure 5: From Diefenderfer, Figure A circuit schematic of a reset-set flip-flop (RSFF) constructed from NAND gates. In Activity 4, you should construct this circuit and verify the associated truth table. two more NAND gates, which are both configured to accept each other s output as second inputs. You should stop here and convince yourself that this sort of feedback results in the two outputs being the logical inverses of one another (denoted Q and Q). Now, the first important thing to note is that if the clock signal is zero (C = 0), then Q and Q remain constant no matter what is applied to S and R. In such a state the FF is said to be disabled or inactive. Moreover, you can think of the FF in this state as acting like a latch preserving an earlier value of Q (and Q). The second important thing to note is that one can control the value of Q (and Q) by setting the clock to logical one (C = 1). In such a state, the FF is said to be enabled or active; and the output values (Q and Q) can be controlled by either changing the value of input S to logical one or by changing the value of input R to logical one. For instance, if S =1 and R=0, you should convince yourself that Q = 1 (and Q = 0). This is referred to as setting the RSFF to 1. Alternatively, if S =0 and R=1, then Q = 0 (and Q = 1). This is referred to as resetting the RSFF to 0. Of course, once the RSFF has been set or reset, it can then be disabled by setting C=0, whereby the output value is latched until the RSFF is enabled again. For this lab exercise: Construct an RSFF using one of the available NAND gate ICs that we have in the class (options include the 74HC03N and the 74LS00N; these both have four 2-input NAND gates per chip). Page 8

9 Use either LabVIEW or the digital indicators and switches on the 503 board to verify the truth table for the RSFF (Fig. 5). Be sure in particular to demonstrate the latching behavior. The DFF (data flip-flop) As you have probably already realized, with slight modification of the clocked RSFF, as shown in Fig. 6, one can make a simple one-bit memory element. This is known as the data flip-flop (DFF). In the DFF configuration, there are only two inputs: the data input (D) and the clock input (C). Just like with the RSFF, the clock signal (C) dictates whether the DFF is active (C = 1) or disabled (C = 0). When the DFF is active, the output Q takes on the value of the input D (obviously either 0 or 1). And when the DFF is disabled, the output is latched, preserving the prepared value of Q until the DFF is activated again. Thus one can use this simple circuit has a one bit storage unit. Importantly, because the circuit is disabled and activated by the external clock signal, one can synchronize this circuit with other circuits and thus build up an array of memory elements. For this lab exercise: Modify the RSFF from the previous exercise to construct a DFF. Use either LabVIEW or the digital indicators and switches on the 503 board to verify the truth table for the DFF (Fig. 5). Make sure to investigate how the clock enables and disables the DFF. The TFF (toggle flip-flop) The circuit in Fig. 7 illustrates one version of a device known as a toggle flip-flop (or TFF). The output values of Q and Q change state every time there is a negative clock transition (i.e. C goes from 1 to 0). This circuit is essential for counters (as you will see in the next exercise with JKFFs). As well, it can be used for frequency division. (For example, if one feeds a TTL square wave with frequency f into the Clock input, the output values Q and Q will toggle with frequency f/2; stringing multiple TFFs in series, once can divide the initial clock frequency by any arbitrary factor of two. To understand how the TFF in Fig. 7 works, it s important to realize that essentially you have two RSFFs in series, with the additional feature that the outputs of the second RSFF are fed back to the inputs of the first RSFF; this is done in such a manner that Q is fed to input S and Q is fed to input R. With this configuration, S and R always take on opposite values and toggle between 0 and 1 on each clock cycle. Looking at the RSFF truth table in Fig. 5, this behavior results in Q and Q toggling on every downward transition of the clock. You might be wondering why the output values toggle on the downward transition of the clock for this circuit. The key to understanding this is to realize that the two RSFFs are in a so-called master-slave configuration, where the first RSFF (the master) transitions on a positive clock edge and the second RSFF (the slave) transitions on a negative clock edge. The relative timing of the master and slave RSFFs is arranged by inverting the clock signal before it is fed to the slave RSFF (as shown in the diagram). Page 9

10 Figure 6: From Diefenderfer Fig A circuit schematic of a data flip-flop (DFF) and its associated truth table. Such circuits can be used a basic memory elements for devices like shift registers. You are to build this circuit in Activity 4. Output toggle Frequency f/2 Master RSFF Slave RSFF Clock Frequency f Figure 7: Adapted from Diefenderfer Fig A circuit schematic of a toggle flip-flop (TFF) constructed from two RSFFs in master-slave configuration. Such FFs are essential for counters. As well they are used for frequency division here the output toggle frequency is ½ the clock frequency. As such this circuit is known as a divide-by-two counter. Page 10

11 (a) (b) D Figure 8: Adapted from Diefenderfer s Fig (a) The circuit symbol and truth table for the JK flip-flop (JKFF). The parameters t n and t nh1 refer to the n th and (n+1) th clock cycle respectively. (b) The JKFF can be modified to function as a DFF by simply inverting the input and routing it to the K terminal. You are to use these JK flip-flops in Activity 4 to build a binary counter and a shift register. For this lab exercise: Start with either the RSFF from the first exercise or the DFF from the previous exercise and construct a TFF. Use LabVIEW to verify the behavior of the TFF. In particular show that the output values toggle at ½ the frequency of the clock. To do this, input a TTL wave at a frequency of your choice to the clock and record the output using your digital oscilloscope VI. **For your lab report: Provide a screen shot of a measurement of the frequency division using a TFF. Also provide a discussion on the difference in operation of the DFF and the TFF circuits and for what applications they might be useful. The JK flip-flop Perhaps the most widely-used and versatile flip-flop is the JK flip-flop (JKFF). While I will not require that you understand its operation in terms of the basic logic gates that compose it, you should take a look at a schematic of the particular JKFF that you will be using in this lab (the Page 11

12 74HC76N), which can be found in the data sheet for the device, in order to get an idea of its composition. Essentially the JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the J = K = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flipflop, i.e., change its output to the logical complement of its current value. Setting J = K = 0 maintains the current state. Shown in Fig. 8a are the truth table and circuit symbol for JKFFs. These you should learn and know well. In fact, the versatility of the JKFF can be appreciated by looking at these. For instance, if one fixes the J and K inputs so that J = K = 1, then the JKFF acts like a TFF with outputs Q and Q toggling between 0 and 1 on each downward clock edge. (Note: some JKFFs are engineered to toggle on the positive clock edge. The one you will use today transitions on the negative edge, but you should always check the specs just to be sure.) In a few minutes you will use several of these JKFFs in TFF mode to create a binary counter. Alternatively, if one makes the modification shown in Fig. 8b, the JKFF will act like a DFF, with a single input D, which can be transferred to the output Q on a negative clock edge and stored temporarily. Before you start working with this device, there are a couple of other things that should be pointed out. First, the SET terminal is used to set the output value Q to one (Q = 1). You should look in the specs to confirm, but this should occur when SET = 0 for the 74HC76N. It should be noted that the SET input overrides the J, K and clock inputs. So make sure you change SET back to one after setting the output. Finally, the RESET terminal is used to set the output value of Q to zero (Q = 0). For the 74HC76N, this occurs when RESET = 0. Just like with the SET function, the RESET function will override the J, K, and clock inputs, so be sure to set it to one after resetting. For this lab exercise: Verify the truth table for the JKFF. Be sure to also explore the SET and RESET functions. It may be simplest to do this using a digital oscilloscope and input TTL to the clock (rather than trying to see it on the LEDS on the 503; but it s up to you). Use several JKFFs in TFF mode to create a count-to-16 binary counter. I m not going to give you the exact circuit schematic. But to aid your design, I ve provided a picture of a count-to-4 binary counter in Fig. 9a. You can see in this design that the J and K inputs on each of the JKFFs are set to one, so the JKFFs each act as TFFs. Moreover, the Q output of the first JKFF is fed into Clock input of the second JKFF. As a result of this, the second JKFF undergoes one toggle in output value for every two toggles of the output of the first JKFF. In this manner, the frequency of the output signal from the counter is ¼ the input clock frequency. Additionally, for each input clock cycle a binary number is produced by the two cells (JKFFs). For the count-to-4 counter the numbers cycle sequentially between 0,1,2 & 3. Use LabVIEW to record and decode the counter in real-time. If you have trouble using LabVIEW to do this, then just use the logic indicators on the 503 board. After verifying the counter s operation, take a look at the frequency division of the output signals from your array of JKFFs. You can do this using a digital scope. Page 12

13 Use four JKFFs in DFF mode to build a 4-bit serial shift register (Fig. 9b). Shift registers are used to transfer data between elements in a network. For the case of the circuit in Fig. 9b, the JKFFs are wired in series, and thus data introduced at the first JKFF (either a one or zero) propagates along the chain of JKFFs, moving from one FF to the next on each negative edge of the clock. Use LabVIEW to record the operation of the shift-register in real-time. Again, if you have difficulty using LabVIEW to do this, simply use the LED logic indicators on the 503 board. One thing to note is that we only have a couple of the 74HC76N dual JKFF ICs in the lab. Thus some of you will have to use the SN74LS76AN. For the latter IC, SET is referred to as PRE and RESET is referred to as CLR in the datasheet. **For your lab report: Show a screen shot of your LabVIEW program for recording the count-to-16 counter (you should have it showing the number 16). If you were not able to decode the counter, then describe the operation of the counter (as measured using the LED indicators) and discuss the frequency division that you observed using the digital scope. Show a screen shot of your LabVIEW program for recording the operation of the shiftregister. Research and discuss the importance of counters and shift registers in digital computers. (a) (b) Q " Q " Toggle Frequency f/2 Data In Clock Frequency f Q # Q # Toggle Frequency f/4 Clock Pulses time Figure 9: Adapted from (a) Schematic of a 2-bit binary counter made from two JKFFs. For operation, J = K = 1. Operation described in the text. (b) Schematic of a 4-bit serial shift register made from 4 JKFFs. All JKFFs are initialized with output equal to zero (A=B=C=D=0). Then a pulse (a one) is sent into the Data terminal. On the next positive clock edge, this toggles the output of the first JKFF to one (A=1). The output A is fed into terminal J of the second JKFF. Then on the next positive clock edge, the output of the second JKFF toggles to one (B=1). And so on, until the data is transferred to the end of the register. Page 13

14 Activity 5 The 555 Timer and DAQ Counters *For PHY 651 (Optional for PHY 351)* The 555 Timer, Fig. 10a, is a classic IC that is used by scientists, engineers and hobbyists alike for many applications including pulse generation, timing circuits and waveform generation. In fact, whole books have been dedicated to this device (see the following website for a list of such references: In this activity, you will learn about two different modes of operation of the 555: the astable mode, which is used for generating square wave oscillations with controlled frequency and duty cycle; and the monostable mode, which is used for generating individual pulses and finite pulse trains. The 555 in astable mode Figure 10b illustrates the appropriate circuit connections for operating the 555 in astable mode. In this mode, the 555 essentially acts as a square wave oscillator. One can understand how this mode works by first looking at the simplified internal circuit schematic for the 555 in Fig. 10a and noticing several important things. (1) Terminal 7 is connected to the collector of a BJT switch (remember Lab6?); when the base of the BJT is low, terminal 7 is an open circuit; when the base of the BJT is high, terminal 7 is a short to ground. (2) Whether the BJT base is low or high is controlled by the Q output of a flip flop, which itself is controlled by two inputs S and R. Finally, (3) whether S and R are high or low are controlled by the outputs of two comparators, whose inputs are set by reference voltages from the divider network that connects to the V H power supply and by input terminals 5 and 6, which the user can set. (a) (b) Figure 10: Adapted from Diefenderfer s Figs and (a) Simplified circuit schematic of the LM555. (b) The 555 configured for astable (i.e. square wave oscillator) mode. Page 14

15 Now, looking at both Figs. 10a and 10b, imagine that the 555 is turned on and Q = 1 (it takes a value of logical one). As a result, the BJT switch will be shorted and any charge on the capacitor connected to terminals 2 and 6 will discharge through the BJT via resistor R M. As the capacitor discharges, the output state of the flip-flop remains constant until the voltage across the capacitor V A reaches V H /3. When V A drops below V H /3, the comparator attached to terminal 2 flips its output so that S = 1, and thus the flip-flop output switches such that Q = 0. After this, the BJT becomes an open circuit and the capacitor starts charging up through resistors R P and R M. It continues to charge up until V A = 2V H /3, at which point the comparator attached to terminal 6 switches so that R = 1. When this happens, the flip-flop output switches back to Q = 1, which shorts the BJT, which causes the capacitor to discharge, and the cycle starts all over again, continuing indefinitely. There are two important things left out of the conversation thus far. First, the output terminal, terminal 3 (V TUV ), provides access to the inverse of the toggled flip-flop output Q. Thus one can connect to terminal 3 and use it as a source of square wave oscillations. Second, one can tailor the duty cycle and period of the square wave oscillations by simply adjusting the values of C, R P and R M. Toward this end, you should know (and convince yourself if you haven t already) that the period and duty cycle (defined as ratio of high output to total period) are given respectively by: For this exercise: T = C(R P + 2R M ) & D. C. = (R P + R M )/(R P + 2R M ). Design a 555 oscillator with a frequency of 500 Hz and a duty cycle of 50% (or as close to those values as you can get). Measure this oscillator using either the Instek digital oscilloscope or your digitial oscilloscope VI. Verify the frequency and duty cycle you designed. Afterwards, take a look at the specs for the LM555, and find the section that discusses how to modify the spacing between peaks in the astable mode. As you will see, this requires applying a timevarying voltage to the control voltage port (terminal 5). Give this a shot and see if you can modify the peak positions as shown in the data sheet. Next, choose the values of C, R P and R M so that you generate a negative pulse (or logical low pulse) that is 10 μs in width and has a repetition frequency of 1000 Hz. **For your lab report: Provide values of the C, R P and R M for the two oscillators you created in this exercise. Discuss how close the frequency, duty cycle, and pulse widths were to the designed values. Provide screen shots or digital photo of the data (or, better yet, graphed data) of several cycles of the oscillations The 555 in monotable mode Figure 12a shows the circuit connections that should be made in order to operate the LM555 in monostable mode. When connected in this manner, the 555 can be used as a single-pulse generator this mode of operation is also called one-shot mode. To understand how one can generate single pulses using this configuration it is helpful to look at Page 15

16 Figs. 10a, 12a and 12b. First, imagine that the LM555 is initialized so that terminal 2 (Trigger) is held high (yielding S = 0), and that the flip-flop is set so that Q = 1, yielding V TUV = 0 and V _`a`_bvtc = 0 (and thus also R = 0). Now, as shown in Fig. 12b, imagine that a short negative pulse is applied to terminal 2, decreasing V Vcbddec so that V Vcbddec < V H /3. When this happens, S switches to S = 1, and thus the flip-flop output switches to Q = 0. This causes the output terminal, terminal 3, to swing high; and it also causes the BJT to open up and the capacitor C to start charging. The capacitor, however, will only charge until V _`a`_bvtc = 2V H /3, at which point the comparator connected to terminal 6 causes R to flip so that R = 0, and thus the flip-flop output flops backs to Q = 1, after which the BJT shorts and discharges C. The net result of all this is that you get a single pulse out of terminal 3 with a pulse width given by the time it takes the capacitor to charge from V H /3 to 2V H /3, which you can set by adjusting the values of C and R according to P. W. = 1.1RC. For this exercise: Configure the LM555 in monostable mode. And use it to perform single-shot pulse generation. Use your function generator to provide the trigger pulses (Fig. 11b). Use the Instek digital scope to read out and characterize both the trigger pulse and the output pulse from the LM555. You should operate the Instek in single shot mode, and configure it to trigger appropriately off of the trigger pulse from the counter in order to capture the pulse from the 555. Choose C and R to generate as small a pulse-width as possible. Be ambitious here. But also be reasonable. Think about what, besides R and C, could limit the pulse width. For instance, as you make the pulse width smaller, you need to make sure that the trigger pulse width remains smaller than the output pulse width (Make sure you understand why this is so.). But the trigger pulse width will be limited by the clock you use to generate it. One technique that you could use to make your trigger pulse very narrow is to use a highpass filter on the input to the trigger. Characterize the pulse produce. What is the over-shoot? What is the sag? What is the rise-time? Decay time? **For your lab report Discuss the results of the monostable operation. Include values of C and R that you used. Discuss whether the pulse width agreed with your expectations based upon these values of C and R. Discuss the minimum pulse width achieved; how you set up the trigger; and discuss the characteristics of the pulse (over-shoot; sag; rise-time; decay) Page 16

17 (a) (b) V # Terminal 2 1 kω 10 nf Trigger Signal Optional high-pass circuit for shaping the trigger pulse Figure 11: Adapted from Diefenderfer s Figures and (a) Illustration of the circuit connections to operate the LM555 in monostable (or one-shot) mode. The high-pass circuit displayed (and circled) underneath is an optional means for appropriately shaping the input trigger pulse that you will use to one-shot the 555. (b) Illustration depicting the timing of the input trigger pulse, the output voltage pulse from the 555, and the charging of the capacitor C. The details are described in the text. Page 17