Analog-to-Digital Conversion (Part 2) Microcomputer Architecture and Interfacing Colorado School of Mines Professor William Hoff

Transcription

1 Analog-to-Digital Conversion (Part 2)

2 Charge redistribution network Instead of a resistor ladder for the D/A converter, the microcontroller uses an-all capacitor system to generate the known voltages It is like a capacitor ladder, instead of a resistor ladder An advantage is that it allows the unknown voltage to be sampled and held, while the comparisons are taking place Recall basic formulas for capacitors: + + V C V C C Q = CV Q = C V + C 2 V 2

3 Sample and hold Sample mode comparator Total charge is Q s = 6 V x assume V L = Hold mode Q h = ( V i )6 = -6 V i = Q s by charge conservation -6 V i = 6 V x so V i = -V x 3

4 Conversion Now, let s switch the largest capacitor up to V H The total charge on the capacitors is still the same Q = 8(V H V i ) + 8( V i ) = 8 V H 6 V i = 6 V x (charge conservation) so V i = (8/6)V H - V x The comparator compares V i against V L = ; if V i < it outputs a Or, it outputs a if V x > (/2) V H 4

5 Conversion (continued) Let s say that the unknown voltage is V x > (/2) V H Next step is to switch the next largest capacitor up to V H Q = (8+4)(V H V i ) + 4( V i ) = 2 V H 6 V i = 6 V x (charge conservation) so V i = (2/6)V H - V x The comparator compares V i against V L = ; if V i < it outputs a Or, it outputs a if V x > (3/4) V H 5

6 Conversion (continued) Each step switches the next largest capacitor up to V H The output of the comparator determines if the capacitor remains at V H or is returned to V L Continue for a total of n steps (for n bit conversion) Example 3 rd step V i =? Example 4 th step V i =? 6

7 Successive approximation method Analog switches are transistors To get resistance as low as possible, the voltage on the gates must be high To get a high voltage (7 to 8V), a charge pump is used That s why you only turn on the A/D converter if you need it 7

8 Output code Quantization error Statistically, a quantization error of ±½ is better than - error To offset by ½ bit, a fixed capacitor of value ½ is used 2 n - V DD /2 n V DD Voltage Figure 2.3 Output characteristic of an ideal n-bit A/D converter 8

9 8 bit A/D To avoid needing a wide range of capacitor values, the ladder is split into two, with a small capacitor in series 9

10 HCS2 A/D Converter The HCS2 uses a successive approximation A/D converter, with either 8 or bit resolution The highest frequency of the conversion clock is 2 MHz (period is.5 microseconds) A/D conversion time is the sum of the converter time and the sample time At 2 MHz ATD clock frequency, an 8-bit conversion takes 8 clock steps, or 4 microseconds The sample time takes two clock steps (to charge the sample capacitor) and an additional 2, 4, 8, or 6 cycles (to store the charge in the storage node) Table 2.8 ATD conversion timings ATD clock frequency resolution converter time 2+2 sample clocks 2+4 sample clocks 2+8 sample clocks 2+6 sample clocks 2 MHz 2 MHz 5 KHz 5 KHz 8-bit () -bit (2) 8-bit -bit 4 s 5 s 6 s 2 s 2 s 3 s 8 s 2 s 5 s 9 s 2 s 36 s Note.. The fastest 8-bit resolution conversion time is 4 s + 2 s = 6 s. 2. The fastest -bit resolution conversion time is 5 s + 2 s = 7 s.

11 HCS2 A/D Converter You can generate an interrupt when conversion is done, or just poll a flag You can select from among 8 analog inputs Conversion is started by writing a value to a control register The conversion result can be right-justified unsigned, left-justified signed, and left-justified unsigned

12 An HCS2 can have two A/D converters Our chip (the C version) has only one VRH, VRL (reference high and reference low) usually tied to Vcc and gnd VDDA, VSSA are power supply inputs for the A/D (tie to Vcc and gnd) From the MC9S2C Family Reference Manual 2

13 Bus clock Clock prescaler ATD clock Results are always stored in order, in the result registers starting with ATD (ATDDR) Confusing: the result from say, input AN2 doesn t necessarily go into result register ATD 2 Conversion complete interrupt V RH V RL VDDA VSSA AN7/PAD7 AN6/PAD6 AN5/PAD5 AN4/PAD4 AN3/PAD3 AN2/PAD2 AN/PAD AN/PAD Analog MUX Mode and timing control Successive apparoximation Register (SAR) and DAC results ATD ATD ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 sample and hold ATD input enable register Port AD data register + - comparator Figure 2.8 The HCS2 ATD block diagram 3

14 Channel Selection CC, CB, and CA (ATDCTL5) select channel (storing starts conversion) MULT bit: =single input, =multiple inputs SCAN bit: =scan continuously, =do once As each conversion completes and is stored into a result register, the corresponding CCF bit in ATDSTAT is set When all conversions complete, the SCF bit in ATDSTAT is set 4

15 Multiple Inputs 5

16 A/D registers Each A/D module has the following registers: Four control registers: ATDxCTL2 - ATDxCTL5 Two status registers: ATDxSTAT and ATDxSTAT Two testing registers: ATDxTEST and ATDxTEST One input enable register: ATDxDIEN One port data register: PTADx Eight 6-bit result registers ATDxDR~ATDxDR7 where x = or In our chip (the C version) we only have one module, so the x is not needed 6

17 A/D Control Registers ATDCTL2 ADPU power up ATD system AFFC fast flag clear reset: ADPU AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE ASCIF ADPU: ATD power down bit = power down ATD = normal ATD operation AFFC: ATD fast flag clear all bit = ATD flag is cleared normally, i.e., read the status register before reading the result register = any access to a result register will cause the associated CCF flag to clear automatically if it is set at the time AWAI: ATD power down in wait mode bit = ATD continues to run when the HCS2 is in wait mode = halt conversion and power down ATD during wait mode ETRIGLE: External trigger level/edge control This bit controls the sensitivity of the external trigger signal. Details are shown in Table 2.. ETRIGP: External trigger polarity This bit controls the polarity of the external trigger signal. See Table 2. for details. ETRIGE: External trigger mode enable = disable external trigger on ATD channel 7 = enable external trigger on ATD channel 7 ASCIE: ATD sequence complete interrupt enable bit = disables ATD interrupt = enables ATD interrupt on sequence complete (ASCIF = ) ASCIF: ATD sequence complete interrupt flag = no ATD interrupt occurred = ATD sequence complete interrupt pending Figure.9 ATD control register 2 (ATDxCTL2, x = or ) 7

18 A/D Control Registers ATDCTL3 (S8C..SC): successive conversions are placed into successive result registers Examples: conversion: result always goes into ATDDR 4 conversions: successive results go into ATDDR..ATDDR3 reset: S8C S4C S2C SC FIFO FRZ FRZ S8C,S4C,S2C,SC: Conversion sequence limit = 8 conversions = conversion = 2 conversions = 3 conversions = 4 conversions = 5 conversions = 6 conversions = 7 conversions xxx = 8 conversions FIFO: Result register FIFO mode = conversion results are placed in the corresponding result register up to the selected sequence length = conversion results are placed in consecutive result registers (wrap around at end) FRZ and FRZ: background debug (freeze) enable bit : continue conversions in active background mode : reserved : finish current conversion, then freeze : freeze immediately when background mode is active Figure. ATD control register 3 (ATDxCTL3, x = or ) 8

19 A/D Control Registers ATDCTL4 PRS3:PRS: The maximum clock is 2 MHz So if we have a 24 MHz E clk, should set this to 5 (24 MHz/6 = 2 MHz) SMP:SMP determine sample time The sample time is 2 clock periods, but you can add time for more accuracy reset: SRES8 SMP SMP PRS4 PRS3 PRS2 PRS PRS SRES8: ATD resolution select bit = -bit operation = 8-bit operation SMP and SMP: select sample time bits These bits are used to select the length of the second phase of the sample time in units of ATD conversion clock cycles. See Table 2.2. PRS4--PRS: ATD clock prescaler bits These five bits are the binary value prescaler value PRS. The ATD conversion clock frequency is calculated as follows: ATDclock = [bus clock] PRS + The ATD conversion frequency must be between 5KHz and 2 MHz. The clock prescaler values are shown in Table 2.3. Figure 2. ATD control register 4 (ATDxCTL4, x = or ) Table 2.2 Sample time select.5 SMP SMP Length of 2nd phase of sample time 2 A/D conversion clock periods 4 A/D conversion clock periods 8 A/D conversion clock periods 6 A/D conversion clock periods 9

20 A/D Control Registers ATDCTL5 Set SCAN= to do continuous conversions Set MULT= to convert only one input CC,CB,CA selects input Table 2.4 Analog input channel select code reset: DJM DSGN SCAN MULT CC CB CA DJM: Result register data justification = left justified data in the result registers = right justified data in the result registers DSGN: Result register data signed or unsigned representation = unsigned data representation in the result registers = signed data representation in the result registers (not available in right justification) SCAN: Enable continuous channel scan bit = single conversion sequence = continuous conversion sequences (scan mode) MULT: Enable multichannel conversion bit = sample only one channel = sample across several channels CC, CB, and CA: Channel select code The channel selection is shown in Table 2.4. Figure 2.2 ATD control register 5 (ATDxCTL5, x = or ) CC CB CA analog input channel AN AN AN2 AN3 AN4 AN5 AN6 AN7 2

21 A/D Status Registers ATDSTAT SCF: Use to check when sequence is complete CC2:CC: indicates the number of the result register that will hold the result reset: SCF ETORF FIFOR CC2 CC CC SCF: Sequence complete flag = conversion sequence not completed = conversion sequence has completed ETORF: External trigger overrun flag = no external trigger overrun has occurred = external trigger overrun has occurred FIFOR: FIFO overrun flag = no overrun has occurred = an overrun has occurred CC2, CC, CC: conversion counter The conversion counter points to the result register that will receive the result of the current conversion. In non-fifo mode, this counter is reset to at the begin and end of the conversion. In FIFO mode, this counter is not reset and will wrap around when its maximum value is reached. Figure 2.3 ATD status register (ATDxSTAT, x = or ) 2

22 A/D Status Registers ATDSTAT Conversion complete flags for all channels You can poll this to find out when conversion is done If fast flag clear is selected, the flag is cleared by reading the result register reset: CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF CCF CCFx: conversion complete flag x (x = 7~) = conversion number x not completed = conversion number x has completed, result in ATDyDRx Figure 2.5 ATD status register (ATDxSTAT, x = or ) 22

23 Summary of A/D Registers Red - used for initialization Green - for interrupt configuration Black = for channel selection and making measurements Results go into ATDDR..ATDDR7 Register ATDCTL2 ADPU AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE ASCIF ATDCTL3 S8C S4C S2C SC FIFO FRZ FRZ ATDCTL4 SRES8 SMP SMP PRS4 PRS3 PRS2 PRS PRS ATDCTL5 DJM DSGN SCAN MULT CC CB CA ATDSTAT SCF ETORF FIFOR CC2 CC CC ATDSTAT CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF CCF 23

24 Initialization ADPU bit enables the ATD module (is disabled by default to conserve power) Takes microseconds for the ATD to become operating after setting the ADPU Example: Set up A/D to digitize continuously on channel 2 ATDCTL2 = xc; // turn on ATD and enable fast flag clear ATDCTL3 = x8; // set the ATD for channel conversion ATDCTL4 = x85; // set the ATD for 2 MHz,2 sample clks,8 bits ATDCTL5 = xa2; // right justified, continuous conversions of AD2 /* A/D results appear in ATDDRL */ 24

25 Example Set up A/D to convert and average 4 successive voltage readings on channel 3, using bits ATDCTL2 = xc; // turn on ATD and enable fast flag clear : //wait microseconds to power up ATDCTL3 = x2; ATDCTL4 = x5; // set the ATD for 4 conversions // set the ATD for 2 MHz,2 sample clks, bits // Start the conversion ATDCTL5 = x83; // right justified, single conversion of AD3 while (!(ATDSTAT & x8)) ; // wait for SCF = // Read and average the four measurements result = (ATDDR + ATDDR + ATDDR2 + ATDDR3)/4; 25

26 A to D Converter Types Successive Approximation Tracking A/D Converter Dual-slope A/D Converter Parallel (flash) A/D Converter Two-stage parallel A/D Converter 26

27 Tracking A/D Converter Very fast digitization as long as signal changes slowly 27

28 Dual-Slope A/D Converter Integrate input voltage for a fixed time T Then discharge it, and time how long it takes to reach zero Can be very accurate where speed isn t a concern (e.g., a multimeter) If you have periodic noise (e.g., 6Hz), can cancel it by making T equal to the period 28

29 Flash A/D Converter Very fast, but expensive 29

30 Summary / Questions The HCS2 uses a successive approximation A/D converter. A charge redistribution network (composed of capacitors) is used to generate known voltages. Why does a -bit conversion take longer than an 8- bit conversion? 3