TIME SCHEDULE. MODULE TOPICS PERIODS 1 Number system & Boolean algebra 17 Test I 1 2 Logic families &Combinational logic

Size: px
Start display at page:

Download "TIME SCHEDULE. MODULE TOPICS PERIODS 1 Number system & Boolean algebra 17 Test I 1 2 Logic families &Combinational logic"

Transcription

1 COURSE TITLE : DIGITAL INSTRUMENTS PRINCIPLE COURSE CODE : 3075 COURSE CATEGORY : B PERIODS/WEEK : 4 PERIODS/SEMESTER : 72 CREDITS : 4 TIME SCHEDULE MODULE TOPICS PERIODS 1 Number system & Boolean algebra 17 Test I 1 2 Logic families &Combinational logic 17 circuits Test II 1 3 Sequential logic circuits 17 Test III 1 4 ADC, DAC & MEMORIES 17 Test IV 1 Total 72 OBJECTIVES MODULE I 1.1. Understand number systems 1.1.1Explain the conversion from decimal to binary by actual division and tabulation with suitable example Study decimal and binary fractions and conversion of decimal fraction into binary with suitable examples Know the features of octal number system with suitable examples for conversion of decimal into octal and octal into binary Study octal fractions and conversion of decimal fraction into octal Know the features of Hexadecimal number system with suitable examples for conversion of decimal into Hexadecimal and Hexadecimal into binary Study Hexadecimal fraction and conversion of Hexadecimal into direct binary and back State the need for binary codes and list different types of binary codes Study the BCD codes, excess-3 code, Gray code and binary weighted codes with suitable examples Study ASCII code Study EBCDIC and error detecting and correcting codes With suitable examples give the idea of binary arithmetic such as addition, subtraction, multiplication and division Understand Boolean algebra and logic simplifications State the importance of logic theory and its applications Study the circuit diagram and explain the switching functions of AND, OR, XOR, and give their logic symbols Draw symbols for NAND, NOR, NOT operation and discuss the advantages of using universal logic gates Know about the sum of product (SOP) expression, product of sum expression (POS.) minters and max terms State the need for simplifying Boolean expression

2 1.2.6 Study the straight simplification with the help of logic rules and truth tables Study the basic principle of Karnaugh map Study two variables, three variables and four variables K-maps with the help of suitable examples and its reductions Study an idea of Don t care terms Study reduction of Boolean expressions using K-map Study the idea of simplification in both SOP and POS form with the help of example List the advantages and disadvantages of Karnaugh map. MODLULE II 2.1. Understand logic families Classify digital logic gates on the basis of number of components incorporated with examples Study logic families Distinguish between positive and negative logic Describe how to represent logic gates by switches Give the detailed circuit description of transistor transfer logic and TTL inverter Know the terms VIL, VIH, VOL, VOH, Noise margin, noise immunity propagation delay Know the term current sourcing and current sinking, fan-in, fan-out, power dissipation, speed power product. 2.2.Understand combinational logic circuits Study combinational logic circuits Design half adder, full adder, half subtractor, and full subtractor Design BCD adders Study the importance of Look-ahead carry adder with examples Study multiplexer & demultiplexer circuits List and explain the various applications of multiplexers and demultiplexers Explain the operation of encoders and decoders Explain various decoders such as BCD to decimal, binary to excess 3 code, binary to gray code and BCD to 7 segment with suitable examples Study digital comparators. MODULE III 3.1. Understand sequential logic circuits Study the sequential logic circuits Distinguish between synchronous and asynchronous sequential logic circuits Construct SR flip flop using NAND gates Explain JK flip flop with the help of truth table and timing diagram Study the need for preset and clear inputs Know the race around condition Study master slave JK flip flop Explain D flip flop, T flip flop with the help of diagram and truth table Study the working of shift registers-serial in serial out, parallel in parallel out, parallel in serial out and serial in parallel out Differentiate right shift and left shift registers Give the application of shift registers Know the working of ring counter and its applications Explain Johnson counter and its applications Study Binary counters Differentiate synchronous and asynchronous counters

3 Study ripple counter Design and implement modulo- N asynchronous counter upto 4 bit

4 MODULE IV 4.1. Understand different types memories Explain semi conductor memory List various types of memory Distinguish between ROM and RAM Explain basic principle of working of ROM State different types of ROM List different ROM and RAM ICs Explain the working of dynamic memory Compare Static RAM, Dynamic RAM State the difference between Flash ROM and NVRAM 4.2. Understand D to A and A to D converters Define accuracy Define resolution Calculate accuracy and resolution for DAC Draw the block diagram of simple binary weighted DAC Explain simple binary weighted DAC Explain briefly R- 2R ladder type network for DAC Study ADC Define & calculate resolution for ADC Study counter-ramp type ADC List the advantages and disadvantage of counter ramp type ADC Study successive approximation ADC List the advantages and disadvantages of SA- ADC CONTENT DETAILS MODULE I Number System and Boolean algebra Number systems - decimal, binary, octal, Hex number system conversion from one system to another system Fractions in all the number systems and its conversions - use of binary codes, different types of binary codes, binary coded decimal, self complementing codes, ASCII Code, EBCDIC error detecting and correcting codes, binary addition, subtraction, multiplication and division. 1 st complement and 2 s complement method of subtraction Introduction to logic theory, switching functions AND, OR, NOT, NOR, NAND, EX-OR operations. The sum of products (SOP) expression, product of sum (POS) expression, switching circuits, truth tables, Boolean theorems and postulates - simplifications of Boolean expressions - simplifications using postulates and Karnaugh map. MODULE II Logic families SSI, MSI, LSI, VLSI and ULSI, existing logic families, positive and negative logic - Transistor Transistor Logic- standard TTL and Schottky TTL, TTL inverter,, noise margin, noise immunity, propagation delay, current sourcing and current sinking, fan in, fan out, power dissipation, speed power product, Comparison of advantages and disadvantages of various logic families Combinational Logic Circuit Introduction Design half adder, full adder, half subtractor, full subtractor, BCD adder- Look ahead Carry adder, multiplexer/data selector - basic 2 to 1MUX, 4 to 1 MUX, applications of

5 the MUX, demultiplexer, 1 to 2 demultiplexer, 1 to 4 demultiplexer, multiplexer and demultiplexerics-encoders and decoders, encoder and decoder Ics. BCD to decimal, BCD to 7 segment decoder encoder digital comparators MODULE III Sequential Logic Circuits Introduction - SR flip flop, SR latch - SR flip-flop using NAND gates, JK flip- flop with preset and clear inputs, D flip-flop, T flip-flop, Master Slave flip-flop Flip flop ICs Binary counters-design and implementation of asynchronous modulus N counter, up down counters-examples- Design and implementation of mod N synchronous (upto 4 bit) counters, and random sequence generators-examples.study of counter ICs, implementation of mod N counters. Shift registers, serial in serial out, parallel in parallel out, serial in parallel out, parallel in serial out shift registers, left shift and right shift registers applications of shift registers, ring counter, Johnson counter and applications. MODULE IV Memories Semi conductor memory- Non-volatile memories ROM PROM EPROM EEROM Flash ROM Volatile memories RAM static RAM - dynamic RAM specifications of memory like speed, access time,capacity, type Digital to analog conversion Binary weighted DAC R-2R ladder type network for DAC Analog to digital conversion Ramp type ADC Successive Approximation ADC TEXT BOOKS 1. Digital fundamentals - Floyd & Jain 2. Fundamentals of digital circuits - A. Anand Kumar REFERENCE BOOKS 1. Digital system principles and applications - Ronald J. Tocci 2. Digital Integrated Circuits - Bogart 3. Digital Logic Applications and Design - John M Yarbrough 4 Digital computer fundamentals - Thomas. C. Bartee 5. Digital electronics- An introduction to theory and practice - Gothman 6. Digital design - Mano 7 Digital Electronics - Green

Tribhuvan University Institute of Science and Technology Bachelor of Science in Computer Science and Information Technology

Tribhuvan University Institute of Science and Technology Bachelor of Science in Computer Science and Information Technology Tribhuvan University Institute of Science and Technology Bachelor of Science in Computer Science and Information Technology Course Title: Digital Logic Full Marks: 60 + 0 + 0 Course No.: CSC Pass Marks:

More information

R13 SET - 1 '' ''' '' ' '''' Code No: RT21053

R13 SET - 1 '' ''' '' ' '''' Code No: RT21053 SET - 1 1. a) What are the characteristics of 2 s complement numbers? b) State the purpose of reducing the switching functions to minimal form. c) Define half adder. d) What are the basic operations in

More information

R13. II B. Tech I Semester Regular Examinations, Jan DIGITAL LOGIC DESIGN (Com. to CSE, IT) PART-A

R13. II B. Tech I Semester Regular Examinations, Jan DIGITAL LOGIC DESIGN (Com. to CSE, IT) PART-A SET - 1 Note: Question Paper consists of two parts (Part-A and Part-B) Answer ALL the question in Part-A Answer any THREE Questions from Part-B a) What are the characteristics of 2 s complement numbers?

More information

CS6201 UNIT I PART-A. Develop or build the following Boolean function with NAND gate F(x,y,z)=(1,2,3,5,7).

CS6201 UNIT I PART-A. Develop or build the following Boolean function with NAND gate F(x,y,z)=(1,2,3,5,7). VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603203 DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING Academic Year: 2015-16 BANK - EVEN SEMESTER UNIT I PART-A 1 Find the octal equivalent of hexadecimal

More information

Bachelor Level/ First Year/ Second Semester/ Science Full Marks: 60 Computer Science and Information Technology (CSc. 151) Pass Marks: 24

Bachelor Level/ First Year/ Second Semester/ Science Full Marks: 60 Computer Science and Information Technology (CSc. 151) Pass Marks: 24 2065 Computer Science and Information Technology (CSc. 151) Pass Marks: 24 Time: 3 hours. Candidates are required to give their answers in their own words as for as practicable. Attempt any TWO questions:

More information

Find the equivalent decimal value for the given value Other number system to decimal ( Sample)

Find the equivalent decimal value for the given value Other number system to decimal ( Sample) VELAMMAL COLLEGE OF ENGINEERING AND TECHNOLOGY, MADURAI 65 009 Department of Information Technology Model Exam-II-Question bank PART A (Answer for all Questions) (8 X = 6) K CO Marks Find the equivalent

More information

1 Hour Sample Test Papers: Sample Test Paper 1. Roll No.

1 Hour Sample Test Papers: Sample Test Paper 1. Roll No. 6.1.2 Sample Test Papers: Sample Test Paper 1 Roll No. Institute Name: Course Code: EJ/EN/ET/EX/EV/IC/IE/IS/MU/DE/ED/ET/IU Subject: Principles of Digital Techniques Marks: 25 1 Hour 1. All questions are

More information

Course Plan. Course Articulation Matrix: Mapping of Course Outcomes (COs) with Program Outcomes (POs) PSO-1 PSO-2

Course Plan. Course Articulation Matrix: Mapping of Course Outcomes (COs) with Program Outcomes (POs) PSO-1 PSO-2 Course Plan Semester: 4 - Semester Year: 2019 Course Title: DIGITAL ELECTRONICS Course Code: EC106 Semester End Examination: 70 Continuous Internal Evaluation: 30 Lesson Plan Author: Ms. CH SRIDEVI Last

More information

WINTER 15 EXAMINATION Model Answer

WINTER 15 EXAMINATION Model Answer Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate

More information

MODU LE DAY. Class-A, B, AB and C amplifiers - basic concepts, power, efficiency Basic concepts of Feedback and Oscillation. Day 1

MODU LE DAY. Class-A, B, AB and C amplifiers - basic concepts, power, efficiency Basic concepts of Feedback and Oscillation. Day 1 DAY MODU LE TOPIC QUESTIONS Day 1 Day 2 Day 3 Day 4 I Class-A, B, AB and C amplifiers - basic concepts, power, efficiency Basic concepts of Feedback and Oscillation Phase Shift Wein Bridge oscillators.

More information

North Shore Community College

North Shore Community College North Shore Community College Course Number: IEL217 Section: MAL Course Name: Digital Electronics 1 Semester: Credit: 4 Hours: Three hours of Lecture, Two hours Laboratory per week Thursdays 8:00am (See

More information

Nirma University Institute of Technology. Electronics and Communication Engineering Department. Course Policy

Nirma University Institute of Technology. Electronics and Communication Engineering Department. Course Policy Nirma University Institute of Technology Electronics and Communication Engineering Department Course Policy B. Tech Semester - III Academic Year: 2017 Course Code & Name : Credit Details : L T P C 4 2

More information

Department of Computer Science and Engineering Question Bank- Even Semester:

Department of Computer Science and Engineering Question Bank- Even Semester: Department of Computer Science and Engineering Question Bank- Even Semester: 2014-2015 CS6201& DIGITAL PRINCIPLES AND SYSTEM DESIGN (Common to IT & CSE, Regulation 2013) UNIT-I 1. Convert the following

More information

TYPICAL QUESTIONS & ANSWERS

TYPICAL QUESTIONS & ANSWERS DIGITALS ELECTRONICS TYPICAL QUESTIONS & ANSWERS OBJECTIVE TYPE QUESTIONS Each Question carries 2 marks. Choose correct or the best alternative in the following: Q.1 The NAND gate output will be low if

More information

DIGITAL SYSTEM DESIGN UNIT I (2 MARKS)

DIGITAL SYSTEM DESIGN UNIT I (2 MARKS) DIGITAL SYSTEM DESIGN UNIT I (2 MARKS) 1. Convert Binary number (111101100) 2 to Octal equivalent. 2. Convert Binary (1101100010011011) 2 to Hexadecimal equivalent. 3. Simplify the following Boolean function

More information

Subject : EE6301 DIGITAL LOGIC CIRCUITS

Subject : EE6301 DIGITAL LOGIC CIRCUITS QUESTION BANK Programme : BE Subject : Semester / Branch : III/EEE UNIT 1 NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES Review of number systems, binary codes, error detection and correction codes (Parity

More information

WINTER 14 EXAMINATION

WINTER 14 EXAMINATION Subject Code: 17320 WINTER 14 EXAMINATION Model Answer Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2)

More information

UNIT 1 NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES 1. Briefly explain the stream lined method of converting binary to decimal number with example. 2. Give the Gray code for the binary number (111) 2. 3.

More information

[2 credit course- 3 hours per week]

[2 credit course- 3 hours per week] Syllabus of Applied Electronics for F Y B Sc Semester- 1 (With effect from June 2012) PAPER I: Components and Devices [2 credit course- 3 hours per week] Unit- I : CIRCUIT THEORY [10 Hrs] Introduction;

More information

Semester III. Subject Name: Digital Electronics. Subject Code: 09CT0301. Diploma Branches in which this subject is offered: Computer Engineering

Semester III. Subject Name: Digital Electronics. Subject Code: 09CT0301. Diploma Branches in which this subject is offered: Computer Engineering Semester III Subject Name: Digital Electronics Subject Code: 09CT0301 Diploma Branches in which this subject is offered: Objective: The subject aims to prepare the students, To understand the basic of

More information

LESSON PLAN. Sub Code: EE2255 Sub Name: DIGITAL LOGIC CIRCUITS Unit: I Branch: EEE Semester: IV

LESSON PLAN. Sub Code: EE2255 Sub Name: DIGITAL LOGIC CIRCUITS Unit: I Branch: EEE Semester: IV Unit: I Branch: EEE Semester: IV Page 1 of 6 Unit I Syllabus: BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS 9 Boolean algebra: De-Morgan s theorem, switching functions and simplification using K-maps & Quine

More information

4.S-[F] SU-02 June All Syllabus Science Faculty B.Sc. II Yr. Instrumentation Practice [Sem.III & IV] S.Lot

4.S-[F] SU-02 June All Syllabus Science Faculty B.Sc. II Yr. Instrumentation Practice [Sem.III & IV] S.Lot [Sem.III & IV] S.Lot. - 1 - [Sem.III & IV] S.Lot. - 2 - [Sem.III & IV] S.Lot. - 3 - Syllabus B.Sc. ( Instrumentation Practice ) Second Year ( Third and Forth Semester ) ( Effective from June 2014 ) [Sem.III

More information

Digital Electronic Circuits and Systems

Digital Electronic Circuits and Systems Digital Electronic Circuits and Systems Macmillan Basis Books in Electronics General Editor: Noel M. Morris, Principal Lecturer, North Staffordshire Polytechnic LINEAR ELECTRONIC CIRCUITS AND SYSTEMS:

More information

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified)

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate

More information

SRM UNIVERSITY FACULTY OF ENGINEERING AND TECHNOLOGY SCHOOL OF ELECTRONICS AND ELECTRICAL ENGINEERING DEPARTMENT OF ECE COURSE PLAN

SRM UNIVERSITY FACULTY OF ENGINEERING AND TECHNOLOGY SCHOOL OF ELECTRONICS AND ELECTRICAL ENGINEERING DEPARTMENT OF ECE COURSE PLAN SRM UNIVERSITY FACULTY OF ENGINEERING AND TECHNOLOGY SCHOOL OF ELECTRONICS AND ELECTRICAL ENGINEERING DEPARTMENT OF ECE COURSE PLAN Course Code : EC0205 Course Title : DIGITAL SYSTEMS Semester : III Course

More information

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) WINTER 2018 EXAMINATION MODEL ANSWER

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) WINTER 2018 EXAMINATION MODEL ANSWER Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in themodel answer scheme. 2) The model answer and the answer written by candidate may

More information

Minnesota State College Southeast

Minnesota State College Southeast ELEC 2211: Digital Electronics II A. COURSE DESCRIPTION Credits: 4 Lecture Hours/Week: 2 Lab Hours/Week: 4 OJT Hours/Week: *.* Prerequisites: None Corequisites: None MnTC Goals: None Minnesota State College

More information

PURBANCHAL UNIVERSITY

PURBANCHAL UNIVERSITY [c] Implement a full adder circuit with a decoder and two OR gates. [4] III SEMESTER FINAL EXAMINATION-2006 Q. [4] [a] What is flip flop? Explain flip flop operating characteristics. [6] [b] Design and

More information

St. MARTIN S ENGINEERING COLLEGE

St. MARTIN S ENGINEERING COLLEGE St. MARTIN S ENGINEERING COLLEGE Dhulapally, Kompally, Secunderabad-500014. Branch Year&Sem Subject Name : Electronics and Communication Engineering : II B. Tech I Semester : SWITCHING THEORY AND LOGIC

More information

Question Bank. Unit 1. Digital Principles, Digital Logic

Question Bank. Unit 1. Digital Principles, Digital Logic Question Bank Unit 1 Digital Principles, Digital Logic 1. Using Karnaugh Map,simplify the following boolean expression and give the implementation of the same using i)nand gates only(sop) ii) NOR gates

More information

Solution to Digital Logic )What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it,

Solution to Digital Logic )What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it, Solution to Digital Logic -2067 Solution to digital logic 2067 1.)What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it, A Magnitude comparator is a combinational

More information

MODULE 3. Combinational & Sequential logic

MODULE 3. Combinational & Sequential logic MODULE 3 Combinational & Sequential logic Combinational Logic Introduction Logic circuit may be classified into two categories. Combinational logic circuits 2. Sequential logic circuits A combinational

More information

BHARATHIDASAN ENGINEERING COLLEGE, NATTRAMPALLI DEPARTMENT OF ECE

BHARATHIDASAN ENGINEERING COLLEGE, NATTRAMPALLI DEPARTMENT OF ECE BHARATHIDASAN ENGINEERING COLLEGE, NATTRAMPALLI DEPARTMENT OF ECE CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN 1 st year 2 nd semester CSE & IT Unit wise Important Part A and Part B Prepared by L.GOPINATH

More information

EXPERIMENT: 1. Graphic Symbol: OR: The output of OR gate is true when one of the inputs A and B or both the inputs are true.

EXPERIMENT: 1. Graphic Symbol: OR: The output of OR gate is true when one of the inputs A and B or both the inputs are true. EXPERIMENT: 1 DATE: VERIFICATION OF BASIC LOGIC GATES AIM: To verify the truth tables of Basic Logic Gates NOT, OR, AND, NAND, NOR, Ex-OR and Ex-NOR. APPARATUS: mention the required IC numbers, Connecting

More information

Prepared By Verified By Approved By Mr M.Kumar Mrs R.Punithavathi Dr. V.Parthasarathy Asst. Professor / IT HOD / IT Principal

Prepared By Verified By Approved By Mr M.Kumar Mrs R.Punithavathi Dr. V.Parthasarathy Asst. Professor / IT HOD / IT Principal DEPARTMENT OF INFORMATION TECHNOLOGY Question Bank Subject Name : Digital Principles and System Design Year / Sem : II Year / III Sem Batch : 2011 2015 Name of the Staff : Mr M.Kumar AP / IT Prepared By

More information

1. Convert the decimal number to binary, octal, and hexadecimal.

1. Convert the decimal number to binary, octal, and hexadecimal. 1. Convert the decimal number 435.64 to binary, octal, and hexadecimal. 2. Part A. Convert the circuit below into NAND gates. Insert or remove inverters as necessary. Part B. What is the propagation delay

More information

CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam

CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam MIDTERM EXAMINATION Spring 2012 Question No: 1 ( Marks: 1 ) - Please choose one A SOP expression is equal to 1

More information

MODULAR DIGITAL ELECTRONICS TRAINING SYSTEM

MODULAR DIGITAL ELECTRONICS TRAINING SYSTEM MODULAR DIGITAL ELECTRONICS TRAINING SYSTEM MDETS UCTECH's Modular Digital Electronics Training System is a modular course covering the fundamentals, concepts, theory and applications of digital electronics.

More information

QUICK GUIDE COMPUTER LOGICAL ORGANIZATION - OVERVIEW

QUICK GUIDE COMPUTER LOGICAL ORGANIZATION - OVERVIEW QUICK GUIDE http://www.tutorialspoint.com/computer_logical_organization/computer_logical_organization_quick_guide.htm COMPUTER LOGICAL ORGANIZATION - OVERVIEW Copyright tutorialspoint.com In the modern

More information

TEST-3 (DIGITAL ELECTRONICS)-(EECTRONIC)

TEST-3 (DIGITAL ELECTRONICS)-(EECTRONIC) 1 TEST-3 (DIGITAL ELECTRONICS)-(EECTRONIC) Q.1 The flip-flip circuit is. a) Unstable b) multistable c) Monostable d) bitable Q.2 A digital counter consists of a group of a) Flip-flop b) half adders c)

More information

DIGITAL ELECTRONICS MCQs

DIGITAL ELECTRONICS MCQs DIGITAL ELECTRONICS MCQs 1. A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register. A. 1 B. 2 C. 4 D. 8

More information

ROEVER COLLEGE OF ENGINEERING & TECHNOLOGY ELAMBALUR, PERAMBALUR DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

ROEVER COLLEGE OF ENGINEERING & TECHNOLOGY ELAMBALUR, PERAMBALUR DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING ROEVER COLLEGE OF ENGINEERING & TECHNOLOGY ELAMBALUR, PERAMBALUR-621220 DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING DIGITAL LOGIC CIRCUITS UNIT-1 BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS 1.

More information

AM AM AM AM PM PM PM

AM AM AM AM PM PM PM FACULTY OF ENGINEERING AND TECHNOLOGY DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING COURSE PLAN Course Code : CS0003 Course Title : DIGITAL COMPUTER FUNDAMENTALS Semester : III Course Time : Jun 204 to

More information

A.R. ENGINEERING COLLEGE, VILLUPURAM ECE DEPARTMENT

A.R. ENGINEERING COLLEGE, VILLUPURAM ECE DEPARTMENT .R. ENGINEERING COLLEGE, VILLUPURM ECE EPRTMENT QUESTION BNK SUB. NME: IGITL ELECTRONICS SUB. COE: EC223 SEM: III BRNCH/YER: ECE/II UNIT-I MINIMIZTION TECHNIQUESN LOGIC GTES PRT- ) efine Minterm & Maxterm.

More information

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad ELECTRICAL AND ELECTRONICS ENGINEERING

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad ELECTRICAL AND ELECTRONICS ENGINEERING Course Name INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 500 043 ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK : SWITCHING THEORY AND LOGIC DESISN Course Code : A40407

More information

ECE 263 Digital Systems, Fall 2015

ECE 263 Digital Systems, Fall 2015 ECE 263 Digital Systems, Fall 2015 REVIEW: FINALS MEMORY ROM, PROM, EPROM, EEPROM, FLASH RAM, DRAM, SRAM Design of a memory cell 1. Draw circuits and write 2 differences and 2 similarities between DRAM

More information

Theory Lecture Day Topic Practical Day. Week. number systems and their inter-conversion Decimal, Binary. 3rd. 1st. 1st

Theory Lecture Day Topic Practical Day. Week. number systems and their inter-conversion Decimal, Binary. 3rd. 1st. 1st Lesson Plan Name of the Faculty : Priyanka Nain Discipline: Electronics & Communication Engg. Semester:5th Subject:DEMP Lesson Plan Duration: 15 Weeks Work Load(Lecture/Practical) per week (In Hours):

More information

Laboratory Objectives and outcomes for Digital Design Lab

Laboratory Objectives and outcomes for Digital Design Lab Class: SE Department of Information Technology Subject Logic Design Sem : III Course Objectives and outcomes for LD Course Objectives: Students will try to : COB1 Understand concept of various components.

More information

Chapter 4. Logic Design

Chapter 4. Logic Design Chapter 4 Logic Design 4.1 Introduction. In previous Chapter we studied gates and combinational circuits, which made by gates (AND, OR, NOT etc.). That can be represented by circuit diagram, truth table

More information

S.K.P. Engineering College, Tiruvannamalai UNIT I

S.K.P. Engineering College, Tiruvannamalai UNIT I UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES Part - A Questions 1. Convert the hexadecimal number E3FA to binary.( Nov 2007) E3FA 16 Hexadecimal E 3 F A 11102 00112 11112 10102 So the equivalent binary

More information

VU Mobile Powered by S NO Group

VU Mobile Powered by S NO Group Question No: 1 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register.

More information

Computer Architecture and Organization

Computer Architecture and Organization A-1 Appendix A - Digital Logic Computer Architecture and Organization Miles Murdocca and Vincent Heuring Appendix A Digital Logic A-2 Appendix A - Digital Logic Chapter Contents A.1 Introduction A.2 Combinational

More information

MODEL QUESTIONS WITH ANSWERS THIRD SEMESTER B.TECH DEGREE EXAMINATION DECEMBER CS 203: Switching Theory and Logic Design. Time: 3 Hrs Marks: 100

MODEL QUESTIONS WITH ANSWERS THIRD SEMESTER B.TECH DEGREE EXAMINATION DECEMBER CS 203: Switching Theory and Logic Design. Time: 3 Hrs Marks: 100 MODEL QUESTIONS WITH ANSWERS THIRD SEMESTER B.TECH DEGREE EXAMINATION DECEMBER 2016 CS 203: Switching Theory and Logic Design Time: 3 Hrs Marks: 100 PART A ( Answer All Questions Each carries 3 Marks )

More information

SUBJECT NAME : DIGITAL ELECTRONICS SUBJECT CODE : EC8392 1. State Demorgan s Theorem. QUESTION BANK PART A UNIT - I DIGITAL FUNDAMENTALS De Morgan suggested two theorems that form important part of Boolean

More information

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous)

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) Subject Code: 17320 Model Answer Page 1 of 32 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the Model answer scheme. 2) The model

More information

2 Marks Q&A. Digital Electronics. K. Michael Mahesh M.E.,MIET. Asst. Prof/ECE Dept.

2 Marks Q&A. Digital Electronics. K. Michael Mahesh M.E.,MIET. Asst. Prof/ECE Dept. 2 Marks Q&A Digital Electronics 3rd SEM CSE & IT ST. JOSEPH COLLEGE OF ENGINEERING (DMI & MMI GROUP OF INSTITUTIONS) CHENNAI- 600 117 K. Michael Mahesh M.E.,MIET. Asst. Prof/ECE Dept. K. Michael Mahesh

More information

DIGITAL FUNDAMENTALS

DIGITAL FUNDAMENTALS DIGITAL FUNDAMENTALS A SYSTEMS APPROACH THOMAS L. FLOYD PEARSON Boston Columbus Indianapolis New York San Francisco Upper Saddle River Amsterdam Cape Town Dubai London Madrid Milan Munich Paris Montreal

More information

1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. [4] Figure 1.

1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. [4] Figure 1. [Question 1 is compulsory] 1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. Figure 1.1 b) Minimize the following Boolean functions:

More information

Principles of Computer Architecture. Appendix A: Digital Logic

Principles of Computer Architecture. Appendix A: Digital Logic A-1 Appendix A - Digital Logic Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic A-2 Appendix A - Digital Logic Chapter Contents A.1 Introduction A.2 Combinational

More information

TRAINING KITS ON DIGITAL ELECTRONIC EXPERIMENTS. Verify Truth table for TTL IC s AND, NOT, & NAND GATES

TRAINING KITS ON DIGITAL ELECTRONIC EXPERIMENTS. Verify Truth table for TTL IC s AND, NOT, & NAND GATES TRAINING KITS ON DIGITAL ELECTRONIC EXPERIMENTS CEE 2800 Basic Logic Gates using TTL IC's (7 in 1) To verify the truth table For TTL AND, OR. NOT, NAND,NOR, EX-OR, & EX-NOR Gates. Instrument comprises

More information

I B.SC (INFORMATION TECHNOLOGY) [ ] Semester II CORE : DIGITAL COMPUTER FUNDAMENTALS - 212B Multiple Choice Questions.

I B.SC (INFORMATION TECHNOLOGY) [ ] Semester II CORE : DIGITAL COMPUTER FUNDAMENTALS - 212B Multiple Choice Questions. Dr.G.R.Damodaran College of Science (Autonomous, affiliated to the Bharathiar University, recognized by the UGC)Re-accredited at the 'A' Grade Level by the NAAC and ISO 9001:2008 Certified CRISL rated

More information

Chapter Contents. Appendix A: Digital Logic. Some Definitions

Chapter Contents. Appendix A: Digital Logic. Some Definitions A- Appendix A - Digital Logic A-2 Appendix A - Digital Logic Chapter Contents Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic A. Introduction A.2 Combinational

More information

Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012

Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012 1 McGill University Faculty of Engineering ECSE-221B Introduction to Computer Engineering Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012 Examiner: Rola Harmouche Date:

More information

Digital Principles and Design

Digital Principles and Design Digital Principles and Design Donald D. Givone University at Buffalo The State University of New York Grauu Boston Burr Ridge, IL Dubuque, IA Madison, Wl New York San Francisco St. Louis Bangkok Bogota

More information

Dev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET

Dev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET Dev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET LABORATORY MANUAL EXPERIMENT NO. 1 ISSUE NO. : ISSUE DATE: REV. NO. : REV. DATE :

More information

G. D. Bishop, Electronics II. G. D. Bishop, Electronics III. John G. Ellis, and Norman J. Riches, Safety and Laboratory Practice

G. D. Bishop, Electronics II. G. D. Bishop, Electronics III. John G. Ellis, and Norman J. Riches, Safety and Laboratory Practice DIGITAL TECHNIQUES Macmillan Technician Series P. Astley, Engineering Drawing and Design II P. J. Avard and J. Cross, Workshop Processes and Materials I G. D. Bishop, Electronics II G. D. Bishop, Electronics

More information

Experiment 8 Introduction to Latches and Flip-Flops and registers

Experiment 8 Introduction to Latches and Flip-Flops and registers Experiment 8 Introduction to Latches and Flip-Flops and registers Introduction: The logic circuits that have been used until now were combinational logic circuits since the output of the device depends

More information

Analogue Versus Digital [5 M]

Analogue Versus Digital [5 M] Q.1 a. Analogue Versus Digital [5 M] There are two basic ways of representing the numerical values of the various physical quantities with which we constantly deal in our day-to-day lives. One of the ways,

More information

UNIT 1: DIGITAL LOGICAL CIRCUITS What is Digital Computer? OR Explain the block diagram of digital computers.

UNIT 1: DIGITAL LOGICAL CIRCUITS What is Digital Computer? OR Explain the block diagram of digital computers. UNIT 1: DIGITAL LOGICAL CIRCUITS What is Digital Computer? OR Explain the block diagram of digital computers. Digital computer is a digital system that performs various computational tasks. The word DIGITAL

More information

UNIVERSITI TEKNOLOGI MALAYSIA

UNIVERSITI TEKNOLOGI MALAYSIA SULIT Faculty of Computing UNIVERSITI TEKNOLOGI MALAYSIA FINAL EXAMINATION SEMESTER I, 2016 / 2017 SUBJECT CODE : SUBJECT NAME : SECTION : TIME : DATE/DAY : VENUES : INSTRUCTIONS : Answer all questions

More information

Sequential Logic. Analysis and Synthesis. Joseph Cavahagh Santa Clara University. r & Francis. TaylonSi Francis Group. , Boca.Raton London New York \

Sequential Logic. Analysis and Synthesis. Joseph Cavahagh Santa Clara University. r & Francis. TaylonSi Francis Group. , Boca.Raton London New York \ Sequential Logic Analysis and Synthesis Joseph Cavahagh Santa Clara University r & Francis TaylonSi Francis Group, Boca.Raton London New York \ CRC is an imprint of the Taylor & Francis Group, an informa

More information

Introduction to Digital Logic Missouri S&T University CPE 2210 Exam 3 Logistics

Introduction to Digital Logic Missouri S&T University CPE 2210 Exam 3 Logistics Introduction to Digital Logic Missouri S&T University CPE 2210 Exam 3 Logistics Egemen K. Çetinkaya Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science and

More information

FUNCTIONS OF COMBINATIONAL LOGIC

FUNCTIONS OF COMBINATIONAL LOGIC FUNCTIONS OF COMBINATIONAL LOGIC Agenda Adders Comparators Decoders Encoders Multiplexers Demultiplexers Adders Basic Adders Adders are important in computers other types of digital systems in which numerical

More information

ME 515 Mechatronics. Introduction to Digital Electronics

ME 515 Mechatronics. Introduction to Digital Electronics ME 55 Mechatronics /5/26 ME 55 Mechatronics Digital Electronics Asanga Ratnaweera Department of Faculty of Engineering University of Peradeniya Tel: 8239 (3627) Email: asangar@pdn.ac.lk Introduction to

More information

RS flip-flop using NOR gate

RS flip-flop using NOR gate RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two

More information

Dev Bhoomi Institute Of Technology PRACTICAL INSTRUCTION SHEET EXPERIMENT NO. ISSUE NO. : ISSUE DATE: REV. NO. : REV. DATE : PAGE:

Dev Bhoomi Institute Of Technology PRACTICAL INSTRUCTION SHEET EXPERIMENT NO. ISSUE NO. : ISSUE DATE: REV. NO. : REV. DATE : PAGE: Dev Bhoomi Institute Of Technology LABORATORY MANUAL PRACTICAL INSTRUCTION SHEET EXPERIMENT NO. ISSUE NO. : ISSUE DATE: REV. NO. : REV. DATE : PAGE: LABORATORY Name & Code: Digital Electronics SEMESTER:

More information

DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES

DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES 1 Learning Objectives 1. Explain the function of a multiplexer. Implement a multiplexer using gates. 2. Explain the

More information

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) MODEL ANSWER

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) MODEL ANSWER Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate

More information

THE KENYA POLYTECHNIC

THE KENYA POLYTECHNIC THE KENYA POLYTECHNIC ELECTRICAL/ELECTRONICS ENGINEERING DEPARTMENT HIGHER DIPLOMA IN ELECTRICAL ENGINEERING END OF YEAR II EXAMINATIONS NOVEMBER 006 DIGITAL ELECTRONICS 3 HOURS INSTRUCTIONS TO CANDIDATES:

More information

DHANALAKSHMI SRINIVASAN INSTITUTE OF RESEARCH AND TECHNOLOGY CS6201-DIGITAL PRINCIPLE AND SYSTEM DESIGN. I Year/ II Sem PART-A TWO MARKS UNIT-I

DHANALAKSHMI SRINIVASAN INSTITUTE OF RESEARCH AND TECHNOLOGY CS6201-DIGITAL PRINCIPLE AND SYSTEM DESIGN. I Year/ II Sem PART-A TWO MARKS UNIT-I DHANALAKSHMI SRINIVASAN INSTITUTE OF RESEARCH AND TECHNOLOGY CS6201-DIGITAL PRINCIPLE AND SYSTEM DESIGN I Year/ II Sem PART-A TWO MARKS UNIT-I BOOLEAN ALGEBRA AND LOGIC GATES 1) What are basic properties

More information

PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops

PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops Objective Construct a two-bit binary decoder. Study multiplexers (MUX) and demultiplexers (DEMUX). Construct an RS flip-flop from discrete gates.

More information

EE6301 DIGITAL LOGIC CIRCUITS UNIT-I NUMBERING SYSTEMS AND DIGITAL LOGIC FAMILIES 1) What are basic properties of Boolean algebra? The basic properties of Boolean algebra are commutative property, associative

More information

SEMESTER ONE EXAMINATIONS 2002

SEMESTER ONE EXAMINATIONS 2002 SEMESTER ONE EXAMINATIONS 2002 EE101 Digital Electronics Solutions Question 1. An assembly line has 3 failsafe sensors and 1 emergency shutdown switch. The Line should keep moving unless any of the following

More information

Logic Design. Flip Flops, Registers and Counters

Logic Design. Flip Flops, Registers and Counters Logic Design Flip Flops, Registers and Counters Introduction Combinational circuits: value of each output depends only on the values of inputs Sequential Circuits: values of outputs depend on inputs and

More information

Registers and Counters

Registers and Counters Registers and Counters Clocked sequential circuit = F/Fs and combinational gates Register Group of flip-flops (share a common clock and capable of storing one bit of information) Consist of a group of

More information

Lesson No Lesson No

Lesson No Lesson No Table of Contents Lesson No. 01 1 An Overview & Number Systems 1 Programmable Logic Devices (PLDs) 8 Fractions in Binary Number System 13 Binary Number System 12 Caveman number system 11 Decimal Number

More information

Decade Counters Mod-5 counter: Decade Counter:

Decade Counters Mod-5 counter: Decade Counter: Decade Counters We can design a decade counter using cascade of mod-5 and mod-2 counters. Mod-2 counter is just a single flip-flop with the two stable states as 0 and 1. Mod-5 counter: A typical mod-5

More information

Contents Circuits... 1

Contents Circuits... 1 Contents Circuits... 1 Categories of Circuits... 1 Description of the operations of circuits... 2 Classification of Combinational Logic... 2 1. Adder... 3 2. Decoder:... 3 Memory Address Decoder... 5 Encoder...

More information

Microprocessor Design

Microprocessor Design Microprocessor Design Principles and Practices With VHDL Enoch O. Hwang Brooks / Cole 2004 To my wife and children Windy, Jonathan and Michelle Contents 1. Designing a Microprocessor... 2 1.1 Overview

More information

AE/AC/AT54 LINEAR ICs & DIGITAL ELECTRONICS DEC 2014

AE/AC/AT54 LINEAR ICs & DIGITAL ELECTRONICS DEC 2014 Q.2a. Give the classification of different IC technologies. IETE 1 b.for a differential amplifier using ideal op-amp(shown in Fig. 2) (i) Find the output voltage v o (ii) Show that the output corresponding

More information

Page No.1. CS302 Digital Logic & Design_ Muhammad Ishfaq

Page No.1. CS302 Digital Logic & Design_ Muhammad Ishfaq Page No.1 File Version Update: (Dated: 17-May-2011) This version of file contains: Content of the Course (Done) FAQ updated version.(these must be read once because some very basic definition and question

More information

Define the outline of formal procedures and compare different digital components like multiplexers, flip flops, decoders, adders.

Define the outline of formal procedures and compare different digital components like multiplexers, flip flops, decoders, adders. COURSE OUTCOME CO1 CO2 CO3 CO4 CO5 CO6 Course Outcomes Explain the difference between analog and digital systems, logic gates and number representations, different weighted and non weighted codes Describe

More information

Come and join us at WebLyceum

Come and join us at WebLyceum Come and join us at WebLyceum For Past Papers, Quiz, Assignments, GDBs, Video Lectures etc Go to http://www.weblyceum.com and click Register In Case of any Problem Contact Administrators Rana Muhammad

More information

Saturated Non Saturated PMOS NMOS CMOS RTL Schottky TTL ECL DTL I I L TTL

Saturated Non Saturated PMOS NMOS CMOS RTL Schottky TTL ECL DTL I I L TTL EC6302-DIGITAL ELECTRONICS UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES 1. Define binary logic? Binary logic consists of binary variables and logical operations. The variables are designated by the alphabets

More information

MC9211 Computer Organization

MC9211 Computer Organization MC9211 Computer Organization Unit 2 : Combinational and Sequential Circuits Lesson2 : Sequential Circuits (KSB) (MCA) (2009-12/ODD) (2009-10/1 A&B) Coverage Lesson2 Outlines the formal procedures for the

More information

TWO MARK QUESTIONS EE6301 DIGITAL LOGIC CIRCUITS

TWO MARK QUESTIONS EE6301 DIGITAL LOGIC CIRCUITS TWO MARK QUESTIONS EE6301 DIGITAL LOGIC CIRCUITS UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES Review of number systems, binary codes, error detection and correction codes (Parity and Hamming code0-

More information

Date: Author: New: Revision: x SAULT COLLEGE OF APPLIED ARTS & TECHNOLOGY SAULT STE. MARIE, ONTARIO ELN TWO

Date: Author: New: Revision: x SAULT COLLEGE OF APPLIED ARTS & TECHNOLOGY SAULT STE. MARIE, ONTARIO ELN TWO SAULT COLLEGE OF APPLIED ARTS & TECHNOLOGY SAULT STE. MARIE, ONTARIO COURSE OUTLINE Course Title: DIGITAL ELECTRONICS Code No.: ELN 107-5 Program: ELECTRICAL/ELECTRONIC TECHNICIAN Semester: TWO Date: AUGUST

More information

RS flip-flop using NOR gate

RS flip-flop using NOR gate RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two

More information

CHAPTER 4: Logic Circuits

CHAPTER 4: Logic Circuits CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits

More information

Combinational Logic Design

Combinational Logic Design Lab #2 Combinational Logic Design Objective: To introduce the design of some fundamental combinational logic building blocks. Preparation: Read the following experiment and complete the circuits where

More information