A pixel chip for tracking in ALICE and particle identification in LHCb

Transcription

1 A pixel chip for tracking in ALICE and particle identification in LHCb K.Wyllie 1), M.Burns 1), M.Campbell 1), E.Cantatore 1), V.Cencelli 2) R.Dinapoli 3), F.Formenti 1), T.Grassi 1), E.Heijne 1), P.Jarron 1), K.Kloukinas 1), P.Lamanna 3), M.Morel 1), V.O Shea 4), V.Quiquempoix 1), D.San Segundo Bello 5), W.Snoeys 1), L.Van- Koningsveld 1) 2), 1) CERN, 2) INFN Rome, 3) University and INFN Bari, 4) University of Glasgow, 5) NIKHEF, Amsterdam. OUTLINE (Pixels for tracking in ALICE) Pixels for particle ID in LHCb General chip description Pixel cell description ALICE operational mode LHCb operational mode Periphery, configuration and I/O interface Future plans and conclusions See talk by Roberto Dinapoli An Analogue Front-End for Silicon Pixel Detectors in ALICE and LHCb 17th May 2000 FEE2000 Perugia, K.H.Wyllie 1

2 Pixels for tracking in ALICE Requirements for the ALICE pixel detector Minimal mass Spatial resolution of 12µm m in r-φ 1% average occupancy Level-1 trigger latency of 5.5µs Level-1 trigger rate = few khz Readout after Level-2 trigger Level-2 latency of 100µs, rate = few khz Full event readout in 400µs s (deadtime( 10%) Radiation tolerant to ~ 500 krad 17th May 2000 FEE2000 Perugia, K.H.Wyllie 2

3 Pixels for tracking in ALICE Implementation Thin sensors (12000 e - signal) Precise time stamp and delay of hits Buffering of Level-1 triggered events inside chip 10MHz readout clock 5 chips + 1 sensor form a ladder 4 ladders aligned in Z form a stave 60 staves form the 2-layer barrel geometry around the interaction point Half Stave ladder2 ladder1 10 chips of one half-stave read out sequentially in 400µs 120 half-staves read out in parallel 17th May 2000 FEE2000 Perugia, K.H.Wyllie 3

4 Pixels for particle ID in LHCb Baseline photodetector for Cherenkov photons in the LHCb RICH: Encapsulation of pixel chip and sensor within a Hybrid Photon Detector (HPD) Requirements Sensitivity to single photons No false hits due to noise (pattern recognition) 2.5mm 2.5mm channel size 8% maximum occupancy 1MHz average Level 0 trigger rate Level-0 trigger latency of 4µs4 Derandomisation of Level-0 triggered events Readout of triggered event in 900ns (deadtime( 1%) 17th May 2000 FEE2000 Perugia, K.H.Wyllie 4

5 Pixels for particle ID in LHCb Implementation 5000e- signal with 20kV accelerating potential Low power consumption (vacuum) Compatible with tube manufacturing Precise time stamp and delay of multiple hits 40MHz readout clock 500µm 500µm ( 5 demagnification) granularity Buffering of Level-0 triggered events System of 500 HPDs 17th May 2000 FEE2000 Perugia, K.H.Wyllie 5

6 Pixels for particle ID in LHCb Full scale prototype 17th May 2000 FEE2000 Perugia, K.H.Wyllie 6

7 Chip Description Fabricated in a commercial 0.25µm m CMOS process High component density Thin gate oxide - small V th shifts after irradiation Radiation-tolerant layout: : Enclosed gates and guard rings SEU-hardened logic ~ 13 million transistors 1.6V power supply Total static power consumption 480mW 17th May 2000 FEE2000 Perugia, K.H.Wyllie 7

8 Pixel Cell 130µm pre-amp (differential) shaper (differential) discriminator (+ fast-or) 60µW W static consumption 260µm two digital delay units trigger coincidence logic 4-event FIFO buffer readout logic see Roberto s talk 35µm 5 un-upsettable upsettable latches for configuration test input on/off pixel mask on/off 3 bits of threshold adjust 17th May 2000 FEE2000 Perugia, K.H.Wyllie 8

9 Pixel Cell : Digital Circuitry Delay unit: stores a hit for duration of trigger latency latches the time-stamp of a hit from a periodic Gray-encoded pattern (modulo n) on an 8-bit bus FIFO: Read/write addressable by Gray encoded bus Risk of switching noise coupling into analog circuitry is reduced by: Gray encoding of patterns on busses Current starved logic cells Differential front end - Roberto 17th May 2000 FEE2000 Perugia, K.H.Wyllie 9

10 ALICE Operational Mode up to 2 hits per Level-1 latency per cell readout time of ns = 25.6µs 17th May 2000 FEE2000 Perugia, K.H.Wyllie 10

11 LHCb Operational Mode 8 pixels configured as a super-pixel of 400µm 425µm readout time of 32 25ns = 800ns 17th May 2000 FEE2000 Perugia, K.H.Wyllie 11

12 The super-pixel 400µm 425µm 17th May 2000 FEE2000 Perugia, K.H.Wyllie 12

13 Periphery and Configuration Periphery contains: Counters to generate timestamp Counters to address FIFO buffers 8-bit DACs to provide voltage and current references for analog circuitry and current-starved logic Configuration of peripheral logic and pixel cells by means of JTAG serial interface - allows both write and read of configuration settings (test,mask.) reading back of analog levels (currents & voltages) generated by DACs connectivity tests of chips on stave using boundary scan allows detection of bad chips on stave 17th May 2000 FEE2000 Perugia, K.H.Wyllie 13

14 Configuration Memory Cells Threat of SEU: : not as bad as ATLAS and CMS but... Policy to protect memory cells against SEU (but not data logic) Memory cells in pixels and DACs: : SEU-hardened circuit Calin et al., IEEE Trans. Nucl. Sci. 43 No. 6, Dec th May 2000 FEE2000 Perugia, K.H.Wyllie 14

15 I/O Interface I/O pads: : Single-ended: Gunning Transceiver Logic (GTL) low swing slew rate control Separate supply for output buffers Multiple bonding pads for supply lines to reduce inductance and limit on-chip power supply bounce during switching 17th May 2000 FEE2000 Perugia, K.H.Wyllie 15

16 Design Problems Big Chip: Voltage drops: both X-direction (across chip) and Y-direction (up columns) => 6 metal layers needed to stay within specs for chip size => sensitive biases sent individually to columns time-of-flight delays up columns (few ns) simulation - required a complex Verilog description checking (!) - DRC,extraction, LVS Packaging for HPD encapsulation: Commercial PGA carriers bond-pad limited (but plenty of pins!) Possible custom carrier in future 17th May 2000 FEE2000 Perugia, K.H.Wyllie 16

17 Future Plans Design is with the foundry Chip back end of June Sensors available in August => bump-bonding ALICE: testbeams foreseen for end of 2000 LHCb: plan encapsulation of chips in HPDs by end of 2000 Begin second iteration of chip to meet full specs 17th May 2000 FEE2000 Perugia, K.H.Wyllie 17

18 Conclusions Chip designed to meet requirements of both the ALICE tracker and the LHCb RICH Deep-submicron technology has allowed the inclusion of large amount of functionality within each pixel cell BUT meeting the specs has been a challenging exercise! Consideration to: reducing switching noise minimising power consumption testability and system integration radiation tolerance 17th May 2000 FEE2000 Perugia, K.H.Wyllie 18