Time Domain Simulations
|
|
- Benjamin Bennett
- 5 years ago
- Views:
Transcription
1 Accuracy of the Computational Experiments Called Mike Steinberger Lead Architect Serial Channel Products SiSoft Time Domain Simulations Evaluation vs. Experimentation We re used to thinking of results that come from computers as being completely accurate and much more precise than we need. Many times, this leads to a false sense of security due to any of three possible problems: 1. Wrong Computation: The computation performed wasn t the correct one to begin with. For example, the boundary conditions imposed were unrealistic (3D field solver users beware) or the equations chosen did not apply to the problem at hand. 2. Numerical Inaccuracy: The algorithms used to solve the equations were not perfect (See [1] for the definitive practical treatment of this subject). 3. Incomplete Coverage: Not all relevant cases were considered. If none of these problems occurred, then we could call that computation an evaluation. Otherwise, we should consider the computation to be a computational experiment subject to the same uncertainties as a physical experiment. That is, the computational experiment can have sources of both random and systematic error, and there are confidence limits which apply to the results. One should be able to draw the error bars around the results and account for these error bars when making engineering decisions. This article considers time domain simulations of high speed serial channels as computational experiments, and explores the confidence limits that should be applied to such experiments. For the experiments considered here, the most critical problem is incomplete coverage. Serial channel performance is strongly affected by intersymbol interference and, as demonstrated in [2], all messages of length 64 or longer should be included in the experiment in order to obtain consistently accurate results. Suffice it to say that no time domain simulation will ever come close to the more than 10^19 bits required. While the results shown in this article may be of some direct value, the goal is to demonstrate some techniques that can be used to determine confidence limits for time domain simulations in general. 1
2 While the results shown in this article may be of some direct value, the goal is to demonstrate some techniques that can be used to determine confidence limits for time domain simulations in general. Experimental Approach The channel simulated was 5 Gb/s data transmitted over 1.5m of PC board trace in a low loss dielectric. There was no equalization at the transmitter and linear equalization at the receiver. The experimental approach taken was to vary the data pattern used in the time domain simulation as well as the length of the time domain simulation. To make sure that the data patterns were independent, they were drawn from different starting positions in the same linear feedback shift register (LFSR) pattern. This LFSR pattern has the advantage that it is much longer than any of the time domain simulations in the experiment. If a data pattern were to be repeated Table 1: The data patterns used. Data Pattern Definitions Pattern Number Pattern Seed 1 2^63-1 LFSR ^63-1 LFSR ^63-1 LFSR ^63-1 LFSR ^63-1 LFSR ^63-1 LFSR ^63-1 LFSR ^63-1 LFSR ^63-1 LFSR ^63-1 LFSR 8091 over the course of a simulation, then the data patterns would no longer be independent. Rather than choosing different seeds for the same LFSR pattern, we could have chosen different LFSR patterns. If the different data patterns were long enough to produce a representative sample of the intersymbol interference, that would have been a valid choice. An alternating 1/0 pattern or a 27-1 LFSR would not have provided an adequate sample of the intersymbol interference, however. This approach was applied to simulations of three different lengths: one million bits, ten million bits, and one hundred million bits. These results can be used to estimate how much the confidence limits can be improved by running longer time domain simulations. Statistical analysis was also applied to the same channel. Statistical analysis is entirely different from time domain simulation in that it computes the statistics of the eye diagram directly rather than compiling them from samples of a time domain waveform. This computation has the advantage that it directly accounts for a statistically significant sample of the intersymbol interference, and the disadvantage that it is only rigorously applicable to linear, time invariant channels. Since the channel used in this study was truly linear and time invariant, this statistical analysis can be considered to be an evaluation rather than a computational experiment, and its results are what the average of the time domain simulation results should be. For the purposes of this study, the statistical analysis results are the right answer. Results A performance analysis of a high speed serial link produces a lot of results offering many different ways to look at the behavior of the channel. It is not the goal of this article to explore the many ways in which channel performance can be presented. Rather, the goal is to show how the results of time domain simulations vary. We will therefore use three different outputs as examples: 1. Inner eye contours: The shape of the inside of the eye diagram at a particular probability. The probabilities shown are 10-3, 10-6, 10-9, and Bathtub curves: Plots of the probability of error as a function of sampling time. These curves are called bathtub curves because they often resemble the cross section of a bathtub. 3. Eye width: The width of the open portion of the eye diagram. This value loosely correlates with timing margin. Figure 1 is an example eye diagram for the channel. All the eye diagrams in this study look very similar to each other. The following figures show the inner eye contours for the three different lengths of time domain simulation. Note that as the length of the time domain simulation progresses from one million bits to one hundred million bits, the contour becomes clearly 2
3 Volts (v) Figure 1: Example eye diagram. distinct from the 10^-6 contour, and it s almost possible to discern the 10^-9 contour. Notice also that the lower probability contours have considerably more variance than the higher probability contours. The following figures show the bathtub curves for the same sets of simulations, along with the bathtub curve for the statistical analysis (shown in red) and the clock PDFs for the time domain simulations. Note that this way of viewing the data makes it much easier to see the variation due to the different data patterns. Figure 8 is an expanded view of Figure 5, Bathtub curves for one million bit simulations and statistical analysis, on page 5, showing how the bathtub curves diverge for the ten different data patterns. Note that the bathtub curves are nearly the same for the higher error probabilities, but then diverge for the lower probabilities. Finally, Table 2 summarizes the mean and standard deviation of the eye width for the time domain simulations and statistical analysis. Persistent Eye Diagram 1.5m low loss PCB trace -5 5 Volts (mv) Eye Diagram Contours One million bit simulations with ten different data patterns -5 5 Figure 2: Inner eye contours for one million bit simulations. Volts (mv) Eye Diagram Contours Ten million bit simulations with ten different data patterns -5 5 Figure 3: Inner eye contours for ten million bit simulations. Volts (v) Inner Eye Diagram Contours One hundred million bit simulations with ten different data patterns Sensitivity 25 0mV Sensitivity 25 0mV Figure 4: Inner eye contours for one hundred million bit simulations. _ 2.4E-2 _ 7.1E-3 _ 6E-4 _ 3.7E-7 _ 4.8E-12 _ _ 3
4 BLACK: Ten million bit time domain simulations using ten different data parameters Eye Width x1: ( ps) x2: (65.040ps) dx: ps -5 5 Figure 5: Bathtub curves for one million bit simulations and statistical analysis. Figure 6: Figure 7: BLACK: Ten million bit time domain simulations using ten different data parameters -5 5 Bathtub curves for ten million bit simulations and statistical analysis. BLACK: One hundred million bit time domain simulations uisng ten different data patterns -5 5 Bathtub curves for one hundred million bit simulations and analysis. Expanded BLACK: One million bit simulations with ten different data patterns Note that as the time domain simulation gets longer, the eye width approaches the statistical analysis result. Note also that increasing the length of the simulation doesn t reduce the standard deviation very much. Discussion and Conclusions The accumulation of a persistent eye from a time domain simulation is an event counting experiment very much like counting radioactive particles with a Gieger counter. That is, for any particular bin in the eye diagram, the expected number of events is equal to the probability density for that particular bin times the number of bits simulated. Also, as in the Gieger counter experiment, the variance of the even count is equal to the square root of the number of events counted [3]. Therefore, as the number of expected events goes down, the variance of the count becomes a larger percentage of the count. In the limit that only one event is expected (for example, along the inner contour of the eye diagram), the variance is also one, meaning that maybe there will be an event counted and maybe there won t. One simple conclusion from the above reasoning is that the number of bits in a time domain simulation should be greater than the reciprocal of the probability of error. That is, if the target bit error rate is 10-12, the time domain simulations should be at least bits long. That s not an experiment I m anxious to try. Figure 8: Expanded view of one million bit bathtub curves. The more important conclusion, however, is that there is a statistical variation associated with the results of any time domain simulation 4
5 of a high speed serial channel. It s important that the user has a reasonable estimate of that variance so that they can use the simulation results to make reliable engineering decisions. This article has demonstrated one approach for obtaining such an estimate. References [1] Press, Teukolsky, Vetterling and Flannery, Numerical Recipes in C++, second edition, Cambridge University Press, [2] Steinberger, Exploration of Deterministic Jitter Distributions, DesignCon2008. [3] Bevington, Data Reduction and Error Analysis for the Physical Sciences, McGraw-Hill, About the Author Michael Steinberger, Ph.D., is responsible for leading SiSoft s ongoing tool development effort for the design and analysis of serial links in the 5-30 Gbps range. Dr. Steinberger has over 30 years experience in the design and analysis of very high speed electronic circuits. Dr. Steinberger began his career at Hughes Aircraft designing microwave circuits. He then moved to Bell Labs, where he designed microwave systems that helped AT&T move from analog to digital long-distance transmission. He was instrumental in the development of high speed digital backplanes used throughout Eye Width Results Simulation Duration Mean Eye Width (ps) Eye Width Standard Deviation (ps) One million bits Ten million bits One hundred million bits Statistical analysis Table 2: The mean and standard deviation of the eye width for the time domain simulations and statistical analysis. Lucent s transmission product line. Prior to joining SiSoft, Dr. Steinberger led a group of over 20 design engineers at Cray Inc. responsible for SerDes design, high speed channel analysis, PCB design and custom RAM design. 5
IBIS-AMI Post-Simulation Analysis
IBIS-AMI Post-Simulation Analysis Mike LaBonte, Todd Westerhoff SiSoft DesignCon IBIS Summit February 2, 2018 Santa Clara, California IBIS Simulation Post-Processing Support IBIS 1.0: Vinl/Vinh IBIS 2.0:
More informationHalf-Rate Decision-Feedback Equalization Di-Bit Response Analysis and Evaluation EDA365
DesignCon 2008 Half-Rate Decision-Feedback Equalization Di-Bit Response Analysis and Evaluation Jihong Ren, Rambus Inc. jren@rambus.com Brian Leibowitz, Rambus Inc. Dan Oh, Rambus Inc. Jared Zerbe, Rambus
More informationCombating Closed Eyes Design & Measurement of Pre-Emphasis and Equalization for Lossy Channels
Combating Closed Eyes Design & Measurement of Pre-Emphasis and Equalization for Lossy Channels Why Test the Receiver? Serial Data communications standards have always specified both the transmitter and
More informationCombating Closed Eyes Design & Measurement of Pre-Emphasis and Equalization for Lossy Channels
Combating Closed Eyes Design & Measurement of Pre-Emphasis and Equalization for Lossy Channels Why Test the Receiver? Serial Data communications standards have always specified both the transmitter and
More informationPAM4 signals for 400 Gbps: acquisition for measurement and signal processing
TITLE PAM4 signals for 400 Gbps: acquisition for measurement and signal processing Image V1.00 1 Introduction, content High speed serial data links are in the process in increasing line speeds from 25
More informationSTAT 113: Statistics and Society Ellen Gundlach, Purdue University. (Chapters refer to Moore and Notz, Statistics: Concepts and Controversies, 8e)
STAT 113: Statistics and Society Ellen Gundlach, Purdue University (Chapters refer to Moore and Notz, Statistics: Concepts and Controversies, 8e) Learning Objectives for Exam 1: Unit 1, Part 1: Population
More informationNew Techniques for Designing and Analyzing Multi-GigaHertz Serial Links
New Techniques for Designing and Analyzing Multi-GigaHertz Serial Links Min Wang, Intel Henri Maramis, Intel Donald Telian, Cadence Kevin Chung, Cadence 1 Agenda 1. Wide Eyes and More Bits 2. Interconnect
More information10 Gb/s Duobinary Signaling over Electrical Backplanes Experimental Results and Discussion
10 Gb/s Duobinary Signaling over Electrical Backplanes Experimental Results and Discussion J. Sinsky, A. Adamiecki, M. Duelk, H. Walter, H. J. Goetz, M. Mandich contact: sinsky@lucent.com Supporters John
More informationThe Challenges of Measuring PAM4 Signals
TITLE The Challenges of Measuring PAM4 Signals Panelists: Doug Burns, SiSoft Stephen Mueller, Teledyne LeCroy Luis Boluña, Keysight Technologies Mark Guenther, Tektronix Image Jose Moreira, Advantest Martin
More informationNew Serial Link Simulation Process, 6 Gbps SAS Case Study
ew Serial Link Simulation Process, 6 Gbps SAS Case Study Donald Telian SI Consultant Session 7-TH2 Donald Telian SI Consultant About the Authors Donald Telian is an independent Signal Integrity Consultant.
More informationDesignCon Pavel Zivny, Tektronix, Inc. (503)
DesignCon 2009 New methods of measuring the performance of equalized serial data links and correlation of performance measures across the design flow, from simulation to measurement, and final BER tests
More informationThe EMC, Signal And Power Integrity Institute Presents
The EMC, Signal And Power Integrity Institute Presents Module 12 Pre-emphasis And Its Impact On The Eye Pattern And Bit-Error-Rate For High-Speed Signaling By Dr. David Norte Copyright 2005 by Dr. David
More informationOn Figure of Merit in PAM4 Optical Transmitter Evaluation, Particularly TDECQ
On Figure of Merit in PAM4 Optical Transmitter Evaluation, Particularly TDECQ Pavel Zivny, Tektronix V1.0 On Figure of Merit in PAM4 Optical Transmitter Evaluation, Particularly TDECQ A brief presentation
More informationDraft Baseline Proposal for CDAUI-8 Chipto-Module (C2M) Electrical Interface (NRZ)
Draft Baseline Proposal for CDAUI-8 Chipto-Module (C2M) Electrical Interface (NRZ) Authors: Tom Palkert: MoSys Jeff Trombley, Haoli Qian: Credo Date: Dec. 4 2014 Presented: IEEE 802.3bs electrical interface
More informationPrecision testing methods of Event Timer A032-ET
Precision testing methods of Event Timer A032-ET Event Timer A032-ET provides extreme precision. Therefore exact determination of its characteristics in commonly accepted way is impossible or, at least,
More informationAMI Simulation with Error Correction to Enhance BER
DesignCon 2011 AMI Simulation with Error Correction to Enhance BER Xiaoqing Dong, Huawei Technologies Dongxiaoqing82@huawei.com Geoffrey Zhang, Huawei Technologies geoff.zhang@huawei.com Kumar Keshavan,
More informationFor the SIA. Applications of Propagation Delay & Skew tool. Introduction. Theory of Operation. Propagation Delay & Skew Tool
For the SIA Applications of Propagation Delay & Skew tool Determine signal propagation delay time Detect skewing between channels on rising or falling edges Create histograms of different edge relationships
More informationPractical Receiver Equalization Tradeoffs Applicable to Next- Generation 28 Gb/s Links with db Loss Channels
DesignCon 2013 Practical Receiver Equalization Tradeoffs Applicable to Next- Generation 28 Gb/s Links with 20 35 db Loss Channels Edward Frlan, Semtech Corp. (EFrlan@semtech.com) Francois Tremblay, Semtech
More informationNew Techniques for Designing and Analyzing Multi-GigaHertz Serial Links
DesignCon 2005 New Techniques for Designing and Analyzing Multi-GigaHertz Serial Links Min Wang, Intel min.wang@intel.com Henri Maramis, Intel henri.maramis@intel.com Donald Telian, Cadence donaldt@cadence.com
More informationCharacterization and improvement of unpatterned wafer defect review on SEMs
Characterization and improvement of unpatterned wafer defect review on SEMs Alan S. Parkes *, Zane Marek ** JEOL USA, Inc. 11 Dearborn Road, Peabody, MA 01960 ABSTRACT Defect Scatter Analysis (DSA) provides
More informationPowering Collaboration and Innovation in the Simulation Design Flow Agilent EEsof Design Forum 2010
Powering Collaboration and Innovation in the Simulation Design Flow Agilent EEsof Design Forum 2010 Channel Simulator and AMI model support within ADS Page 1 Contributors to this Paper José Luis Pino,
More informationTransmitter Preemphasis: An Easier Path to 99% Coverage at 300m?
Transmitter Preemphasis: An Easier Path to 99% Coverage at 300m?, Jim McVey, The-Linh Nguyen Finisar Tom Lindsay - Clariphy January 24, 2005 Page: 1 Introduction Current Models Show 99% Coverage at 300m
More informationLAB 1: Plotting a GM Plateau and Introduction to Statistical Distribution. A. Plotting a GM Plateau. This lab will have two sections, A and B.
LAB 1: Plotting a GM Plateau and Introduction to Statistical Distribution This lab will have two sections, A and B. Students are supposed to write separate lab reports on section A and B, and submit the
More informationDesign of Fault Coverage Test Pattern Generator Using LFSR
Design of Fault Coverage Test Pattern Generator Using LFSR B.Saritha M.Tech Student, Department of ECE, Dhruva Institue of Engineering & Technology. Abstract: A new fault coverage test pattern generator
More informationm RSC Chromatographie Integration Methods Second Edition CHROMATOGRAPHY MONOGRAPHS Norman Dyson Dyson Instruments Ltd., UK
m RSC CHROMATOGRAPHY MONOGRAPHS Chromatographie Integration Methods Second Edition Norman Dyson Dyson Instruments Ltd., UK THE ROYAL SOCIETY OF CHEMISTRY Chapter 1 Measurements and Models The Basic Measurements
More informationSignal Integrity Design Using Fast Channel Simulator and Eye Diagram Statistics
Signal Integrity Design Using Fast Channel Simulator and Eye Diagram Statistics Sanjeev Gupta, Signal Integrity Applications Expert Colin Warwick, Signal Integrity Product Manager Agilent EEsof EDA XTalk1
More informationECE 5765 Modern Communication Fall 2005, UMD Experiment 10: PRBS Messages, Eye Patterns & Noise Simulation using PRBS
ECE 5765 Modern Communication Fall 2005, UMD Experiment 10: PRBS Messages, Eye Patterns & Noise Simulation using PRBS modules basic: SEQUENCE GENERATOR, TUNEABLE LPF, ADDER, BUFFER AMPLIFIER extra basic:
More informationTP1a mask, noise and jitter for SRn
TP1a mask, noise and jitter for SRn Piers Dawe Avago Technologies IEEE P802.3ba Quebec May 2009 TP1a mask, noise and jitter for SRn 1 Supporters Mike Dudek Jonathan King Brian Misek John Petrilla Independent*
More informationComparison of NRZ, PR-2, and PR-4 signaling. Qasim Chaudry Adam Healey Greg Sheets
Comparison of NRZ, PR-2, and PR-4 signaling Presented by: Rob Brink Contributors: Pervez Aziz Qasim Chaudry Adam Healey Greg Sheets Scope and Purpose Operation over electrical backplanes at 10.3125Gb/s
More informationFPGA IMPLEMENTATION AN ALGORITHM TO ESTIMATE THE PROXIMITY OF A MOVING TARGET
International Journal of VLSI Design, 2(2), 20, pp. 39-46 FPGA IMPLEMENTATION AN ALGORITHM TO ESTIMATE THE PROXIMITY OF A MOVING TARGET Ramya Prasanthi Kota, Nagaraja Kumar Pateti2, & Sneha Ghanate3,2
More informationDuobinary Transmission over ATCA Backplanes
Duobinary Transmission over ATCA Backplanes Majid Barazande-Pour John Khoury November 15-19, 2004 IEEE 802.3ap Backplane Ethernet Task Force Plenary Meeting San Antonio Texas Outline Introduction Adaptive
More informationEqualizing XAUI Backplanes with the MAX3980
Design Note: HFDN-17.0 Rev.1; 04/08 Equalizing XAUI Backplanes with the MAX3980 AVAILABLE Equalizing XAUI Backplanes with the MAX3980 1 Introduction This discussion explores the performance of the MAX3980
More informationLabView Exercises: Part II
Physics 3100 Electronics, Fall 2008, Digital Circuits 1 LabView Exercises: Part II The working VIs should be handed in to the TA at the end of the lab. Using LabView for Calculations and Simulations LabView
More informationPresentation to IEEE P802.3ap Backplane Ethernet Task Force July 2004 Working Session
Presentation to IEEE P802.3ap Backplane Ethernet Task Force July 2004 Working Session Title: PAM-4 versus NRZ Signaling: "Basic Theory" Source: John Bulzacchelli Troy Beukema David R Stauffer Joe Abler
More informationExperiment 4: Eye Patterns
Experiment 4: Eye Patterns ACHIEVEMENTS: understanding the Nyquist I criterion; transmission rates via bandlimited channels; comparison of the snap shot display with the eye patterns. PREREQUISITES: some
More informationPractical Bit Error Rate Measurements on Fibre Optic Communications Links in Student Teaching Laboratories
Ref ETOP021 Practical Bit Error Rate Measurements on Fibre Optic Communications Links in Student Teaching Laboratories Douglas Walsh 1, David Moodie 1, Iain Mauchline 1, Steve Conner 1, Walter Johnstone
More informationNew Technologies for 6 Gbps Serial Link Design & Simulation, a Case Study
New Technologies for 6 Gbps Serial Link Session # 8ICP8 Revision 1.0 SI Consultant Donald Telian Hitachi GST Paul Larson, Ravinder Ajmani IBM Kent Dramstad, Adge Hawes Presented at ABSTRACT The design
More informationDesignCon New Serial Link Simulation Process, 6 Gbps SAS Case Study. Donald Telian, SI Consultant
DesignCon 2009 New Serial Link Simulation Process, 6 Gbps SAS Case Study Donald Telian, SI Consultant telian@sti.net Paul Larson, Hitachi GST paul.larson@hitachigst.com Ravinder Ajmani, Hitachi GST Ravinder.Ajmani@hitachiGST.com
More informationOverview: Logic BIST
VLSI Design Verification and Testing Built-In Self-Test (BIST) - 2 Mohammad Tehranipoor Electrical and Computer Engineering University of Connecticut 23 April 2007 1 Overview: Logic BIST Motivation Built-in
More information(Skip to step 11 if you are already familiar with connecting to the Tribot)
LEGO MINDSTORMS NXT Lab 5 Remember back in Lab 2 when the Tribot was commanded to drive in a specific pattern that had the shape of a bow tie? Specific commands were passed to the motors to command how
More information8. Stratix GX Built-In Self Test (BIST)
8. Stratix GX Built-In Self Test (BIST) SGX52008-1.1 Introduction Each Stratix GX channel in the gigabit transceiver block contains embedded built-in self test (BIST) circuitry, which is available for
More informationFeatures. For price, delivery, and to place orders, please contact Hittite Microwave Corporation:
HMC-C1 Typical Applications The HMC-C1 is ideal for: OC-78 and SDH STM-25 Equipment Serial Data Transmission up to 5 Gbps Short, intermediate, and long haul fiber optic applications Broadband Test and
More informationDELTA MODULATION AND DPCM CODING OF COLOR SIGNALS
DELTA MODULATION AND DPCM CODING OF COLOR SIGNALS Item Type text; Proceedings Authors Habibi, A. Publisher International Foundation for Telemetering Journal International Telemetering Conference Proceedings
More informationEfficient 500 MHz Digital Phase Locked Loop Implementation sin 180nm CMOS Technology
Efficient 500 MHz Digital Phase Locked Loop Implementation sin 180nm CMOS Technology Akash Singh Rawat 1, Kirti Gupta 2 Electronics and Communication Department, Bharati Vidyapeeth s College of Engineering,
More informationJin-Fu Li Advanced Reliable Systems (ARES) Laboratory. National Central University
Chapter 3 Basics of VLSI Testing (2) Jin-Fu Li Advanced Reliable Systems (ARES) Laboratory Department of Electrical Engineering National Central University Jhongli, Taiwan Outline Testing Process Fault
More informationAnalog Performance-based Self-Test Approaches for Mixed-Signal Circuits
Analog Performance-based Self-Test Approaches for Mixed-Signal Circuits Tutorial, September 1, 2015 Byoungho Kim, Ph.D. Division of Electrical Engineering Hanyang University Outline State of the Art for
More informationBTV Tuesday 21 November 2006
Test Review Test from last Thursday. Biggest sellers of converters are HD to composite. All of these monitors in the studio are composite.. Identify the only portion of the vertical blanking interval waveform
More informationSamtec Final Inch PCIE Series Connector Differential Pair Configuration Channel Properties
Samtec Final Inch PCIE Series Connector Differential Pair Configuration Channel Properties Scott McMorrow, Director of Engineering Jim Bell, Senior Signal Integrity Engineer Page 1 Introduction and Philosophy
More informationUsing Allegro PCB SI GXL to Make Your Multi-GHz Serial Link Work Right Out of the Box
Using Allegro PCB SI GXL to Make Your Multi-GHz Serial Link Work Right Out of the Box Session 8.11 - Hamid Kharrati - A2e Technologies Agenda About the Project Modeling the System Frequency Domain Analysis
More informationApproach For Supporting Legacy Channels Per IEEE 802.3bj Objective
Approach For Supporting Legacy Channels Per IEEE 802.3bj Objective Jitendra Mohan, Texas Instruments Pravin Patel, IBM Jan 2012, IEEE 802.3bj Meeting, Newport Beach 1 Agenda Approach to enable NRZ over
More informationPCIe: EYE DIAGRAM ANALYSIS IN HYPERLYNX
PCIe: EYE DIAGRAM ANALYSIS IN HYPERLYNX w w w. m e n t o r. c o m PCIe: Eye Diagram Analysis in HyperLynx PCI Express Tutorial This PCI Express tutorial will walk you through time-domain eye diagram analysis
More informationEvaluating Oscilloscope Mask Testing for Six Sigma Quality Standards
Evaluating Oscilloscope Mask Testing for Six Sigma Quality Standards Application Note Introduction Engineers use oscilloscopes to measure and evaluate a variety of signals from a range of sources. Oscilloscopes
More informationHow to Predict the Output of a Hardware Random Number Generator
How to Predict the Output of a Hardware Random Number Generator Markus Dichtl Siemens AG, Corporate Technology Markus.Dichtl@siemens.com Abstract. A hardware random number generator was described at CHES
More informationMC9211 Computer Organization
MC9211 Computer Organization Unit 2 : Combinational and Sequential Circuits Lesson2 : Sequential Circuits (KSB) (MCA) (2009-12/ODD) (2009-10/1 A&B) Coverage Lesson2 Outlines the formal procedures for the
More informationHighly Accelerated Stress Screening of the Atlas Liquid Argon Calorimeter Front End Boards
Highly Accelerated Stress Screening of the Atlas Liquid Argon Calorimeter Front End Boards K. Benslama, G. Brooijmans, C.-Y. Chi, D. Dannheim, I. Katsanos, J. Parsons, S. Simion Nevis Labs, Columbia University
More informationWhy Engineers Ignore Cable Loss
Why Engineers Ignore Cable Loss By Brig Asay, Agilent Technologies Companies spend large amounts of money on test and measurement equipment. One of the largest purchases for high speed designers is a real
More informationOptimization of Multi-Channel BCH Error Decoding for Common Cases. Russell Dill Master's Thesis Defense April 20, 2015
Optimization of Multi-Channel BCH Error Decoding for Common Cases Russell Dill Master's Thesis Defense April 20, 2015 Bose-Chaudhuri-Hocquenghem (BCH) BCH is an Error Correcting Code (ECC) and is used
More informationAbhijeetKhandale. H R Bhagyalakshmi
Sobel Edge Detection Using FPGA AbhijeetKhandale M.Tech Student Dept. of ECE BMS College of Engineering, Bangalore INDIA abhijeet.khandale@gmail.com H R Bhagyalakshmi Associate professor Dept. of ECE BMS
More informationMeasurement User Guide
N4906 91040 Measurement User Guide The Serial BERT offers several different kinds of advanced measurements for various purposes: DUT Output Timing/Jitter This type of measurement is used to measure the
More informationVLSI Test Technology and Reliability (ET4076)
VLSI Test Technology and Reliability (ET476) Lecture 9 (2) Built-In-Self Test (Chapter 5) Said Hamdioui Computer Engineering Lab Delft University of Technology 29-2 Learning aims Describe the concept and
More informationOptimizing BNC PCB Footprint Designs for Digital Video Equipment
Optimizing BNC PCB Footprint Designs for Digital Video Equipment By Tsun-kit Chin Applications Engineer, Member of Technical Staff National Semiconductor Corp. Introduction An increasing number of video
More informationExperiment 7: Bit Error Rate (BER) Measurement in the Noisy Channel
Experiment 7: Bit Error Rate (BER) Measurement in the Noisy Channel Modified Dr Peter Vial March 2011 from Emona TIMS experiment ACHIEVEMENTS: ability to set up a digital communications system over a noisy,
More informationLogic Design II (17.342) Spring Lecture Outline
Logic Design II (17.342) Spring 2012 Lecture Outline Class # 05 February 23, 2012 Dohn Bowden 1 Today s Lecture Analysis of Clocked Sequential Circuits Chapter 13 2 Course Admin 3 Administrative Admin
More informationAudio Compression Technology for Voice Transmission
Audio Compression Technology for Voice Transmission 1 SUBRATA SAHA, 2 VIKRAM REDDY 1 Department of Electrical and Computer Engineering 2 Department of Computer Science University of Manitoba Winnipeg,
More informationThe Measurement Tools and What They Do
2 The Measurement Tools The Measurement Tools and What They Do JITTERWIZARD The JitterWizard is a unique capability of the JitterPro package that performs the requisite scope setup chores while simplifying
More informationDesign for Test. Design for test (DFT) refers to those design techniques that make test generation and test application cost-effective.
Design for Test Definition: Design for test (DFT) refers to those design techniques that make test generation and test application cost-effective. Types: Design for Testability Enhanced access Built-In
More informationSynthesized Clock Generator
Synthesized Clock Generator CG635 DC to 2.05 GHz low-jitter clock generator Clocks from DC to 2.05 GHz Random jitter
More informationSDAIII-CompleteLinQ Multi-Lane Serial Data, Noise and Crosstalk Analysis
SDAIII-CompleteLinQ Multi-Lane Serial Data, Noise and Crosstalk Analysis TOOLS TO MEET SERIAL DATA ANALYSIS CHALLENGES Key Features Most complete jitter decomposition, eye diagram and analysis tools Up
More informationIBIS AMI Modeling of Retimer and Performance Analysis of Retimer based Active Serial Links
DesignCon 2014 IBIS AMI Modeling of Retimer and Performance Analysis of Retimer based Active Serial Links Kian Haur (Alfred) Chong, Texas Instruments Venkatesh Avula, LSI Research and Development, Bangalore,
More informationHMC-C060 HIGH SPEED LOGIC. 43 Gbps, D-TYPE FLIP-FLOP MODULE. Features. Typical Applications. General Description. Functional Diagram
HMC-C Features Typical Applications The HMC-C is ideal for: OC-78 and SDH STM-25 Equipment Serial Data Transmission up to 43 Gbps Digital Logic Systems up to 43 Gbps Broadband Test and Measurement Functional
More informationHow to overcome/avoid High Frequency Effects on Debug Interfaces Trace Port Design Guidelines
How to overcome/avoid High Frequency Effects on Debug Interfaces Trace Port Design Guidelines An On-Chip Debugger/Analyzer (OCD) like isystem s ic5000 (Figure 1) acts as a link to the target hardware by
More informationBrian Holden Kandou Bus, S.A. IEEE GE Study Group September 2, 2013 York, United Kingdom
Simulation results for NRZ, ENRZ & PAM-4 on 16-wire full-sized 400GE backplanes Brian Holden Kandou Bus, S.A. brian@kandou.com IEEE 802.3 400GE Study Group September 2, 2013 York, United Kingdom IP Disclosure
More informationAvoiding False Pass or False Fail
Avoiding False Pass or False Fail By Michael Smith, Teradyne, October 2012 There is an expectation from consumers that today s electronic products will just work and that electronic manufacturers have
More informationFast Ethernet Consortium Clause 25 PMD-EEE Conformance Test Suite v1.1 Report
Fast Ethernet Consortium Clause 25 PMD-EEE Conformance Test Suite v1.1 Report UNH-IOL 121 Technology Drive, Suite 2 Durham, NH 03824 +1-603-862-0090 Consortium Manager: Peter Scruton pjs@iol.unh.edu +1-603-862-4534
More informationAMI Modeling Methodology and Measurement Correlation of a 6.25Gb/s Link
May 26th, 2011 DAC IBIS Summit June 2011 AMI Modeling Methodology and Measurement Correlation of a 6.25Gb/s Link Ryan Coutts Antonis Orphanou Manuel Luschas Amolak Badesha Nilesh Kamdar Agenda Correlation
More informationVLSI System Testing. BIST Motivation
ECE 538 VLSI System Testing Krish Chakrabarty Built-In Self-Test (BIST): ECE 538 Krish Chakrabarty BIST Motivation Useful for field test and diagnosis (less expensive than a local automatic test equipment)
More informationEVALUATION KIT AVAILABLE 12.5Gbps Settable Receive Equalizer +2.5V +3.3V V CC1 V CC. 30in OF FR-4 STRIPLINE OR MICROSTRIP TRANSMISSION LINE SDI+ SDI-
19-2713; Rev 1; 11/03 EVALUATION KIT AVAILABLE 12.5Gbps Settable Receive Equalizer General Description The driver with integrated analog equalizer compensates up to 20dB of loss at 5GHz. It is designed
More informationMicrowave Interconnect Testing For 12G-SDI Applications
DesignCon 2016 Microwave Interconnect Testing For 12G-SDI Applications Jim Nadolny, Samtec jim.nadolny@samtec.com Corey Kimble, Craig Rapp Samtec OJ Danzy, Mike Resso Keysight Boris Nevelev Imagine Communications
More informationDraft 100G SR4 TxVEC - TDP Update. John Petrilla: Avago Technologies February 2014
Draft 100G SR4 TxVEC - TDP Update John Petrilla: Avago Technologies February 2014 Supporters David Cunningham Jonathan King Patrick Decker Avago Technologies Finisar Oracle MMF ad hoc February 2014 Avago
More informationHMC-C064 HIGH SPEED LOGIC. 50 Gbps, XOR / XNOR Module. Features. Typical Applications. General Description. Functional Diagram
HMC-C4 Features Typical Applications The HMC-C4 is ideal for: OC-78 and SDH STM-25 Equipment Serial Data Transmission up to 5 Gbps Digital Logic Systems up to 5 Gbps Broadband Test and Measurement Functional
More informationIn total 2 project plans are submitted. Deadline for Plan 1 is on at 23:59. The plan must contain the following information:
Electronics II 2014 final project instructions (version 1) General: Your task is to design and implement an electric dice, an electric lock for a safe, a heart rate monitor, an electronic Braille translator,
More informationCMOS Testing-2. Design for testability (DFT) Design and Test Flow: Old View Test was merely an afterthought. Specification. Design errors.
Design and test CMOS Testing- Design for testability (DFT) Scan design Built-in self-test IDDQ testing ECE 261 Krish Chakrabarty 1 Design and Test Flow: Old View Test was merely an afterthought Specification
More informationDigital Logic Design Sequential Circuits. Dr. Basem ElHalawany
Digital Logic Design Sequential Circuits Dr. Basem ElHalawany Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs
More informationAbout Giovanni De Poli. What is Model. Introduction. di Poli: Methodologies for Expressive Modeling of/for Music Performance
Methodologies for Expressiveness Modeling of and for Music Performance by Giovanni De Poli Center of Computational Sonology, Department of Information Engineering, University of Padova, Padova, Italy About
More informationBootstrap Methods in Regression Questions Have you had a chance to try any of this? Any of the review questions?
ICPSR Blalock Lectures, 2003 Bootstrap Resampling Robert Stine Lecture 3 Bootstrap Methods in Regression Questions Have you had a chance to try any of this? Any of the review questions? Getting class notes
More informationIBIS-AMI and Jitter. Mike LaBonte SiSoft. SPI 2018 IBIS Summit May 25, 2018 Brest, France
IBIS-AMI and Jitter Mike LaBonte SiSoft SPI 2018 IBIS Summit May 25, 2018 Brest, France Agenda Overview of Jitter and Noise Concepts IBIS-AMI Jitter and Noise Reserved_Parameters IBIS-AMI Jitter and Noise
More informationMeasurements and Simulation Results in Support of IEEE 802.3bj Objective
Measurements and Simulation Results in Support of IEEE 802.3bj Objective Jitendra Mohan, National Semiconductor Corporation Pravin Patel, IBM Zhiping Yang, Cisco Peerouz Amleshi, Mark Bugg, Molex Sep 2011,
More informationhomework solutions for: Homework #4: Signal-to-Noise Ratio Estimation submitted to: Dr. Joseph Picone ECE 8993 Fundamentals of Speech Recognition
INSTITUTE FOR SIGNAL AND INFORMATION PROCESSING homework solutions for: Homework #4: Signal-to-Noise Ratio Estimation submitted to: Dr. Joseph Picone ECE 8993 Fundamentals of Speech Recognition May 3,
More informationSV1C Personalized SerDes Tester
SV1C Personalized SerDes Tester Data Sheet SV1C Personalized SerDes Tester Data Sheet Revision: 1.0 2013-02-27 Revision Revision History Date 1.0 Document release Feb 27, 2013 The information in this
More informationASNT8140. ASNT8140-KMC DC-23Gbps PRBS Generator with the (x 7 + x + 1) Polynomial. vee. vcc qp. vcc. vcc qn. qxorp. qxorn. vee. vcc rstn_p.
ASNT8140-KMC DC-23Gbps PRBS Generator with the (x 7 + x + 1) Polynomial Full-length (2 7-1) pseudo-random binary sequence (PRBS) generator DC to 23Gbps output data rate Additional output delayed by half
More informationExceeding the Limits of Binary Data Transmission on Printed Circuit Boards by Multilevel Signaling
Exceeding the Limits of Binary Data Transmission on Printed Circuit Boards by Multilevel Signaling Markus Grözing, Manfred Berroth INT, in cooperation with Michael May Agilent Technologies, Böblingen Prof.
More informationAsynchronous counters
Asynchronous counters In the previous section, we saw a circuit using one J-K flip-flop that counted backward in a two-bit binary sequence, from 11 to 10 to 01 to 00. Since it would be desirable to have
More informationIBIS4.2 and VHDL-AMS for SERDES and DDR2 Analysis
IBIS4.2 and VHDL-AMS for SERDES and DDR2 Analysis Ian Dodd Architect, High Speed Tools Ian_dodd@mentor.com Gary Pratt Manager, High Speed Partnerships gary_pratt@mentor.com 31 st October 2006 Mentor Graphics
More information(Refer Slide Time 1:58)
Digital Circuits and Systems Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology Madras Lecture - 1 Introduction to Digital Circuits This course is on digital circuits
More informationA Way to Evaluate post-fec BER based on IBIS-AMI Model
A Way to Evaluate post-fec BER based on IBIS-AMI Model Yu Yangye, Guo Tao, Zhu Shunlin yu.yangye@zte.com.cn,guo.tao6@zte.com.cn,zhu.shunlin@zte.com.cn Asian IBIS Summit, Shanghai, China, November 13, 2017
More informationStandardization of Field Performance Measurement Methods for Product Acceptance
Standardization of Field Performance Measurement Methods for Product Acceptance Greg Twitty R & D Project Manager Product Test Factory Nokia Mobile Phones 1 Overview Current state of product acceptance
More information21.1. Unit 21. Hardware Acceleration
21.1 Unit 21 Hardware Acceleration 21.2 Motivation When designing hardware we have nearly unlimited control and parallelism at our disposal We can create structures that may dramatically improve performance
More informationA Serializer ASIC at 5 Gbps for Detector Front-end Electronics Readout
A Serializer ASIC at 5 Gbps for Detector Front-end Electronics Readout Jingbo Ye, on behalf of the ATLAS Liquid Argon Calorimeter Group Department of Physics, Southern Methodist University, Dallas, Texas
More informationWINTER 15 EXAMINATION Model Answer
Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate
More informationProcessor time 9 Used memory 9. Lost video frames 11 Storage buffer 11 Received rate 11
Processor time 9 Used memory 9 Lost video frames 11 Storage buffer 11 Received rate 11 2 3 After you ve completed the installation and configuration, run AXIS Installation Verifier from the main menu icon
More information