Professor Henry Selvaraj, PhD. November 30, CPE 302 Digital System Design. Super Project

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Morris Scott
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1 CPE 302 Digital System Design Super Project Problem (Design on the DE2 board using an ultrasonic sensor as varying input to display a dynamic changing video) All designs are verified using Quartus or Active-HDL, and implemented using DE2 board Department of EE and CPE

2 v Design Problem Statement: Design on the DE2 board using an ultrasonic sensor as varying input to display a dynamic changing video. Ø Introduction: The purpose of this project is to display a square shape via VGA and using ultrasonic sensors to control the X and Y axis. Ø Ultrasonic Sensor: The ultrasonic sensor works by sending a trigger signal out to the surrounding area. Once the signal leaves the sensor the counts begin until the echo is received. After a set period of time if the echo does not receive the signal to send out another trigger signal or pulse. FPGA Determining Distance: Take for example an object 10 away from the sensor. Now using. for the speed of sound. The sound needs to travel for 294 which is received by the echo pin. Since the value is doubled because the signal needs to travel back and forth the following equation calculates this. =. Department of Electrical and Computer Engineering 1 of 5

3 Implementing on DE2 VHDL Code: The VHDL code was implemented assuming a 50 clock and displaying each digit of the separately one for the tens place and another for the ones place. Displaying in hexadecimal. Department of Electrical and Computer Engineering 2 of 5

4 Ø VGA: The VGA connector consists of R, G, B, HS and VS pins. To keep the coding simple implementation of standard RGB will be used. The HS makes a new line and start drawing pixels as desired, and VS indicates when the bottom of the monitor has been reached and then starts back up top. Implementation of VGA: The VHDL code was implemented assuming a 25 clock and the following code below gives the dimensions of the box and the corresponding position on the screen. The color of the box is pink to make it easily visible. Department of Electrical and Computer Engineering 3 of 5

Implementation of Ultrasonic Sensor and VGA: The VHDL code was implemented assuming a 25 clock for the VGA and a 50 clock for the ultrasonic sensor.

5 Ø Ultrasonic Sensor and VGA: Using the DE2 board exposed pins to connect two ultrasonic sensors to act as varying inputs for the x and y axis. In addition, the expansion headers has VDD and GND connections for the ultrasonic sensors. Implementation of Ultrasonic Sensor and VGA: The VHDL code was implemented assuming a 25 clock for the VGA and a 50 clock for the ultrasonic sensor. The x-axis was divided up into 17 sections and the y-axis was divided up into 14 sections. If the ultrasonic sensor went below 3 the box would default in the starting position, and if the ultrasonic sensor went above 33 the box would default in the maximum position. Department of Electrical and Computer Engineering 4 of 5

6 Ø Conclusion: When implementing the VGA and ultrasonic sensor separately on the DE2 board. There was little to no trouble when debugging VHDL code, but when merging both projects there were incompatibilities among libraries and binary operations with integers. Solving these problems required a bit of research and learning how to use the CONV_INTEGER( ) function in VHDL. This function converted nearly any non-integer value into integers so that mathematical operations can be performed on them. Using this function the merger of the ultrasonic sensor outputting hexadecimal and VGA outputting binary were converted into integers. This allowed the ultrasonic sensors to act as varying input while the VGA display the corresponding box in the respective regions. Overall this project was successful but there needs to be improvement with smoothing the transitions of inputs of the ultrasonic sensor. Department of Electrical and Computer Engineering 5 of 5

Design and implementation (in VHDL) of a VGA Display and Light Sensor to run on the Nexys4DDR board Report and Signoff due Week 6 (October 4)

ECE 574: Modeling and synthesis of digital systems using Verilog and VHDL Fall Semester 2017 Design and implementation (in VHDL) of a VGA Display and Light Sensor to run on the Nexys4DDR board Report and