Table 1. EBI Bus Control Signals

Size: px
Start display at page:

Download "Table 1. EBI Bus Control Signals"

Transcription

1 HT32 Series EBI /N: AN0470E Overview The parallel bus interface used for the HT32 microcontroller family, named EBI or the External Bus Interface, allows access to external asynchronous parallel bus devices such as SRAM, Flash Memory, LC modules, etc. It can send these external signals to the internal address bus in the Cortex -M core using corresponding memory mapping. The HT32 Series EBI supports both data and address line multiplexing, thus effectively reducing the pin count required for external device connection. The bus read/write timing can be adjusted according to the external device timing requirements. Bus Control Signal The following table shows all the control signals, address and data line signals of the HT32 series external bus interface. It should be noted that some signals are only supported in the larger package types. For the smaller package types it may only support a reduced number of signals. Signal Input/output escription A[xx:0] Output Address bus A[xx:0] Input/output Address/data bus Output Chip select Output Output enable Output Write enable ALE Output Address latch enable BL[1:0] Output Bit group channel ARY Input Asynchronous ready Table 1. EBI Bus Control Signals Note that the BL[1:0] bit field is only used for some 16-bit data width SRAMs and the ARY bit is only applied for some NOR Flash memory types. EBI Operating Mode The EBI supports both multiplexed and non-multiplexed addressing modes. The nonmultiplexed address mode has a higher and faster work efficiency but also requires larger pin counts. The multiplexed addressing mode is slower and requires an additional address latch but has lower pin counts. AN0470E 1 / 10 November 14, 2017

2 Non-multiplexed Mode 8A8: This mode supports 8-bit address and 8-bit data. The signal high byte in the EBI_A signal line is address while the lower byte is data. 16: In the non-multiplexed mode, the 16-bit signal in the EBI_A signal line is data. The address is contained in the EBI_A signal line. Multiplexed Mode 8A24ALE: This mode allows a 24-bit address and 8-bits of data to be multiplexed in the EBI_ signal line to reduce pin count. These signals will be encoded by the EBI_ALE signal. The higher byte in the EBI_A signal line is bits EBI_A[15:8] and is the 8-bit address which has an order from the highest bit to the lowest. The lower byte in the EBI_A signal line, bits EBI_A[7:0] contain the middle 8-bit address and the 8-bit data. 16A16ALE: This mode supports the 16-bit address and 16-bits of data. It also requires an external latch and an additional signal EBI_ALE. The 16-bit address and 16-bit data are multiplexed on the EBI_A pin. Timing Configuration The EBI contains several timing setting parameters for use with different accessing protocols. RSETUP: Setup the number of cycles for the address setting before the bit is asserted. RSTRB: Setup the number of cycles that the bit is held active for. RHOL: Setup the number of cycles that the is held active for after the bit is de-asserted. SETUP: Setup the number of cycles for the address setting before the bit is asserted. STRB: Setup the number of cycles that the bit is held active for. HOL: Setup the number of cycles that the is held active for after the bit is de-asserted. RSETUP RSTRB RHOL EBI_ EBI_ Figure 1. EBI Non-multiplexed Read Timing AN0470E 2 / 10 November 14, 2017

3 SETUP STRB HOL EBI_ EBI_ Figure 2. EBI Non-multiplexed Write Timing Bits ARSETUP and ARHOL are used to control the external address latch timing in the multiplexed mode. Refer to the reference manual for more detailed information on the timing configuration. ARSETUP: Setup the number of cycles that the address is driven onto the A bus before the ALE bit is asserted. ARHOL: Setup the number of cycles the address is held on the A bus after the ALE bit is asserted. ARSETUP RSETUP RSTRB RHOL EBI_ALE EBI_ EBI_ Figure 3. EBI Multiplexed Read Timing ARSETUP ARHOL SETUP STRB HOL EBI_ALE EBI_ EBI_ Figure 4. EBI Multiplexed Write Timing Other Features Full page read operation Write buffer AHB processing width switch Read/write period extension Polarity configuration AN0470E 3 / 10 November 14, 2017

4 Asynchronous NOR Flash Interface EBI Configuration The EBI provides the following functions to control NOR Flash memory: Select Bank for NOR Flash memory mapping Select EBI mode: 8A8, 16A16ALE, 8A24ALE, 16 Enable or disable asynchronous ready or asynchronous ready overflow Configure control signal polarity Setup timing parameters Setup full page read function Asynchronous NOR Flash memory contains different AC specifications; therefore the timing parameter values for specific memory should be determined first. This document takes the MX29GL256F Memory as a reference. The read/write access timing parameters of the MX29GL256F Memory are listed in the Table 2. Symbol escription Value Unit Tcs Chip enable setting time 0 ns Twp # pulse width 35 ns Twph # pulse width high level time 30 ns Twc Write period time 100 ns Taa Toe Valid data output after address # valid data output after is de-asserted 100 ns 25 ns Trc Read period time 100 ns Table 2. MX29GL256F NOR Flash Memory Timing According to the memory timing listed in the Table 2, the EBI initialisation can be implemented by the following procedures. Here EBI Bank 0 in the 16 mode under a CPU operating frequency of 72MHz is taken as an example: AN0470E 4 / 10 November 14, 2017

5 Hardware Connection The following figures show the typical connections between the MX29GL256F NOR Flash Memory and four EBI modes. The unused EBI pins can be used as general I/O pins. 8A8 A[8] A[15:9] A[7:0] A[24:8] NOR [15] A[6:0] [7:0] A[23:7] BYTE# ARY Vss # # CE# RY/BY# Figure 5. Connection between NOR Flash and EBI in the 8A8 Mode 16 NOR [15:0] Vcc BYTE# A[23:0] ARY A[23:0] # # CE# RY/BY# Figure 6. Connection between NOR Flash and EBI in the 16 Mode 16A16ALE NOR A[23:16] A[23:16] Vcc A[15:0] ALE ARY BYTE# [15:0] # # CE# RY/BY# Figure 7. Connection between NOR Flash and EBI in the 16A16ALE Mode AN0470E 5 / 10 November 14, 2017

6 8A24ALE A[7:0] ALE A[15:9]/A[8] NOR A[14:7] [7:0] A[6:0]/[15] A[22:16]/A[15] Vss BYTE# A[24] A[23] CE Figure 8. Connection between NOR Flash and EBI in the 8A24ALEMode Asynchronous 16-bit SRAM Interface EBI Configuration The EBI provides the following functions to control SRAM: Select Bank for SRAM memory mapping Select EBI mode: 8A8, 16A16ALE, 8A24ALE, 16 Enable or disable bit group channel function Configure control signal polarity Setup timing parameters Asynchronous SRAM memory contains different AC specifications; therefore the timing parameter values for specific memory should be determined first. This document takes the IS61WV102416BLL Memory as a reference. The read/write access timing parameters of the IS61WV102416BLL Memory are listed in the Table 3. Symbol escription Value Unit Tsce Taw CE to write complete time Address setup and write complete time 8 ns 8 ns Tpwe pulse width 8 ns Twc Write period time 10 ns Taa Address accessing time 10 ns Tdoe accessing time 6.5 ns Trc Read period time 10 ns Table 3. IS61WV102416BLL SRAM Memory Timing AN0470E 6 / 10 November 14, 2017

7 According to the memory timing listed in the Table 3, the EBI initialisation can be implemented by the following procedures. Here EBI Bank 2 in the 16 mode under a CPU operating frequency of 72MHz is taken as an example: Considering the drive capability of the HT32 Series I/O, it may be necessary to increase some of the EBI timing parameters appropriately when the CPU is operating at 72 MHz. Hardware connection The following figures show the typical connections between the IS61WV102416BLL SRAM Memory and four EBI modes. The unused EBI pins can be used as general I/O pins. 8A8 A[15:8] A[7:0] SRAM A[7:0] [7:0] A[19:8] A[19:8] BL[1] BL[0] UB LB CE Figure 9. Connection between SRAM and EBI in the 8A8 Mode 16 A[19:0] BL[1] BL[0] SRAM [15:0] A[19:0] UB LB CE Figure 10. Connection between SRAM and EBI in the 16 Mode AN0470E 7 / 10 November 14, 2017

8 16A16ALE A[19:16] SRAM A[19:16] A[15:0] ALE BL[1] BL[0] [15:0] UB LB CE Figure 11. Connection between SRAM and EBI in the 16A16AL Mode SRAM A[15:8] 8A24ALE A[7:0] ALE A[15:8] [7:0] A[7:0] A[19:16] BL[1] UB BL[0] LB CE Figure 12. Connection between SRAM and EBI in the 8A24ALE Mode AN0470E 8 / 10 November 14, 2017

9 Intel 8080-like LC Module Interface EBI Configuration This is similar to the above description for an asynchronous NOR Flash or SRAM memory, but the EBI contains different accessing protocols. The related user LC protocol type must first be well-defined when operating with LC modules. The protocol type is determined by different control signals and the LC specific actions required for read/write processing. Hardware Connection The following figures show the typical connections between an Intel 8080 LC and four EBI modes. The unused EBI pins can be used as general I/O pins A16ALE A[0] LC [15:0] WR R RS Figure 13. Connection between LC 8080-like Interface and EBI in the 16/16A16ALE Mode 8A8 8A24ALE A[7:0] A[0] LC [7:0] WR R RS Figure14. Connection between LC 8080-like Interface and EBI in the 8A8/8A24ALE Mode Revision and Modification Information ate Author Issue 吳旭宏 Initial version AN0470E 9 / 10 November 14, 2017

10 isclaimer All information, trademarks, logos, graphics, videos, audio clips, links and other items appearing on this website ('Information') are for reference only and is subject to change at any time without prior notice and at the discretion of Holtek Semiconductor Inc. (hereinafter 'Holtek', 'the company', 'us', 'we' or 'our'). Whilst Holtek endeavors to ensure the accuracy of the Information on this website, no express or implied warranty is given by Holtek to the accuracy of the Information. Holtek shall bear no responsibility for any incorrectness or leakage. Holtek shall not be liable for any damages (including but not limited to computer virus, system problems or data loss) whatsoever arising in using or in connection with the use of this website by any party. There may be links in this area, which allow you to visit the websites of other companies. These websites are not controlled by Holtek. Holtek will bear no responsibility and no guarantee to whatsoever Information displayed at such sites. Hyperlinks to other websites are at your own risk. Limitation of Liability In any case, the Company has no need to take responsibility for any loss or damage caused when anyone visits the website directly or indirectly and uses the contents, information or service on the website. Governing Law This disclaimer is subjected to the laws of the Republic of China and under the jurisdiction of the Court of the Republic of China. Update of isclaimer Holtek reserves the right to update the isclaimer at any time with or without prior notice, all changes are effective immediately upon posting to the website. AN0470E 10 / 10 November 14, 2017

Using the HT1628 for Washing Machine Panel Display

Using the HT1628 for Washing Machine Panel Display Using the HT1628 for Washing Machine Panel Display D/N: AN0476E Introduction The HT1628 device is a RAM-mapped multifunction LCD control driver IC which operates with a 1/1 or 1/2 Duty. The device output

More information

HT8 MCU Integrated LCD Application Example (2) C Type Bias

HT8 MCU Integrated LCD Application Example (2) C Type Bias HT8 MCU Integrated LCD Application Example (2) C Type Bias D/N: AN0413E Introduction The Holtek LCD type MCUs provide four LCD driving schemes including the R type, C type, SCOM type as well as SCOM and

More information

Logic Devices for Interfacing, The 8085 MPU Lecture 4

Logic Devices for Interfacing, The 8085 MPU Lecture 4 Logic Devices for Interfacing, The 8085 MPU Lecture 4 1 Logic Devices for Interfacing Tri-State devices Buffer Bidirectional Buffer Decoder Encoder D Flip Flop :Latch and Clocked 2 Tri-state Logic Outputs

More information

SMPTE-259M/DVB-ASI Scrambler/Controller

SMPTE-259M/DVB-ASI Scrambler/Controller SMPTE-259M/DVB-ASI Scrambler/Controller Features Fully compatible with SMPTE-259M Fully compatible with DVB-ASI Operates from a single +5V supply 44-pin PLCC package Encodes both 8- and 10-bit parallel

More information

ADC Peripheral in Microcontrollers. Petr Cesak, Jan Fischer, Jaroslav Roztocil

ADC Peripheral in Microcontrollers. Petr Cesak, Jan Fischer, Jaroslav Roztocil ADC Peripheral in s Petr Cesak, Jan Fischer, Jaroslav Roztocil Czech Technical University in Prague, Faculty of Electrical Engineering Technicka 2, CZ-16627 Prague 6, Czech Republic Phone: +420-224 352

More information

Macronix OctaFlash Serial NOR Flash White Paper

Macronix OctaFlash Serial NOR Flash White Paper Macronix OctaFlash Serial NOR Flash White Paper Introduction Macronix, a leading provider of non-volatile memory solutions, is the world s leading supplier of ROM and Serial NOR Flash products. Macronix

More information

Comparing JTAG, SPI, and I2C

Comparing JTAG, SPI, and I2C Comparing JTAG, SPI, and I2C Application by Russell Hanabusa 1. Introduction This paper discusses three popular serial buses: JTAG, SPI, and I2C. A typical electronic product today will have one or more

More information

Configuring and using the DCU2 on the MPC5606S MCU

Configuring and using the DCU2 on the MPC5606S MCU Freescale Semiconductor Document Number: AN4187 Application Note Rev. 0, 11/2010 Configuring and using the DCU2 on the MPC5606S MCU by: Steve McAslan Microcontroller Solutions Group 1 Introduction The

More information

BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT

BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4, 8, AND 6 MBIT 28F4SC, 28F8SC, 28F6SC Includes Commercial and Extended Temperature Specifications n n n n n SmartVoltage Technology 2.7V (Read-Only), 3.3V

More information

Technical Note PowerPC Embedded Processors Video Security with PowerPC

Technical Note PowerPC Embedded Processors Video Security with PowerPC Introduction For many reasons, digital platforms are becoming increasingly popular for video security applications. In comparison to traditional analog support, a digital solution can more effectively

More information

5 VOLT FlashFile MEMORY

5 VOLT FlashFile MEMORY 5 VOLT FlashFile MEMORY 28F4S5, 28F8S5, 28F6S5 (x8) n n n n n n SmartVoltage Technology 5 Volt Flash: 5 V V CC and 5 V or 2 V V PP High-Performance 85 ns Read Access Time Enhanced Data Protection Features

More information

DLP Pico Chipset Interface Manual

DLP Pico Chipset Interface Manual Data Sheet TI DN 2510477 Rev A May 2009 DLP Pico Chipset Interface Manual Data Sheet TI DN 2510477 Rev A May 2009 IMPORTANT NOTICE BEFORE USING TECHNICAL INFORMATION, THE USER SHOULD CAREFULLY READ THE

More information

AT03716: Implementation of SAM L Configurable Custom Logic (CCL) Peripheral. Description. SMART ARM-based Microcontrollers APPLICATION NOTE

AT03716: Implementation of SAM L Configurable Custom Logic (CCL) Peripheral. Description. SMART ARM-based Microcontrollers APPLICATION NOTE SMART ARM-based Microcontrollers AT03716: Implementation of SAM L Configurable Custom Logic (CCL) Peripheral APPLICATION NOTE Description The Configurable Custom Logic (CCL) module contains programmable

More information

LY62L K X 16 BIT LOW POWER CMOS SRAM

LY62L K X 16 BIT LOW POWER CMOS SRAM REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jul.25.2004 Rev. 2.0 Revised ISB(max) : 0.5mA => 1.25mA May.11.2006 Rev. 2.1 Revised Package Outline Dimension(TSOP-II) Apr.12.2007

More information

Enable input provides synchronized operation with other components

Enable input provides synchronized operation with other components PSoC Creator Component Datasheet Pseudo Random Sequence (PRS) 2.0 Features 2 to 64 bits PRS sequence length Time Division Multiplexing mode Serial output bit stream Continuous or single-step run modes

More information

3 VOLT FlashFile MEMORY

3 VOLT FlashFile MEMORY 3 VOLT FlashFile MEMORY 28F4S3, 28F8S3, 28F6S3 (x8) n n n n n SmartVoltage Technology 2.7 V (Read-Only) or 3.3 V V CC and 3.3 V or 2 V V PP High-Performance 2 ns Read Access Time Enhanced Data Protection

More information

SOC Single Channel H264 + Audio Encoder module

SOC Single Channel H264 + Audio Encoder module SOC Single Channel H264 + Audio Encoder module Integration Manual Revision 1.1 06/16/2016 2016 SOC Technologies Inc. SOC is disclosing this user manual (the "Documentation") to you solely for use in the

More information

AN Cascading NXP LCD segment drivers. Document information. Keywords

AN Cascading NXP LCD segment drivers. Document information. Keywords Rev. 1 12 February 2014 Application note Document information Info Keywords Abstract Content PCF8576C, PCA8576C, PCF8576D, PCA8576D, PCA8576F, PCF8532, PCF8533, PCA8533, PCF8534, PCA8534, PCF8562, PCF85132,

More information

Design and Implementation of Timer, GPIO, and 7-segment Peripherals

Design and Implementation of Timer, GPIO, and 7-segment Peripherals Design and Implementation of Timer, GPIO, and 7-segment Peripherals 1 Module Overview Learn about timers, GPIO and 7-segment display; Design and implement an AHB timer, a GPIO peripheral, and a 7-segment

More information

M89 FAMILY In-System Programmable (ISP) Multiple-Memory and Logic FLASH+PSD Systems for MCUs

M89 FAMILY In-System Programmable (ISP) Multiple-Memory and Logic FLASH+PSD Systems for MCUs In-System Programmable (ISP) Multiple-Memory and Logic FLASH+PSD Systems for MCUs DATA BRIEFING Single Supply Voltage: 5V±10% for M9xxFxY 3 V (+20/ 10%) for M9xxFxW 1 or 2 Mbit of Primary Flash Memory

More information

MT8806 ISO-CMOS 8x4AnalogSwitchArray

MT8806 ISO-CMOS 8x4AnalogSwitchArray MT886 ISO-CMOS 8x4AnalogSwitchArray Features Internal control latches and address decoder Short set-up and hold times Wide operating voltage: 4.5 V to 3.2 V 2Vpp analog signal capability R ON 65 max. @

More information

Design and Implementation of an AHB VGA Peripheral

Design and Implementation of an AHB VGA Peripheral Design and Implementation of an AHB VGA Peripheral 1 Module Overview Learn about VGA interface; Design and implement an AHB VGA peripheral; Program the peripheral using assembly; Lab Demonstration. System

More information

STA2051E VESPUCCI 32-BIT SINGLE CHIP BASEBAND CONTROLLER FOR GPS AND TELEMATIC APPLICATIONS 1 FEATURES. Figure 1. Packages

STA2051E VESPUCCI 32-BIT SINGLE CHIP BASEBAND CONTROLLER FOR GPS AND TELEMATIC APPLICATIONS 1 FEATURES. Figure 1. Packages STA2051 VESPUCCI 32-BIT SINGLE CHIP BASEBAND CONTROLLER FOR GPS AND TELEMATIC APPLICATIONS DATA BRIEF 1 FEATURES ARM7TDMI 16/32 bit RISC CPU based host microcontroller. Complete Embedded Memory System:

More information

SignalTap Plus System Analyzer

SignalTap Plus System Analyzer SignalTap Plus System Analyzer June 2000, ver. 1 Data Sheet Features Simultaneous internal programmable logic device (PLD) and external (board-level) logic analysis 32-channel external logic analyzer 166

More information

MT x 12 Analog Switch Array

MT x 12 Analog Switch Array MT885 8 x 2 Analog Switch Array Features Internal control latches and address decoder Short set-up and hold times Wide operating voltage: 4.5V to 3.2V 2Vpp analog signal capability R ON 65 max. @ V DD

More information

MC54/74F568 MC54/74F569 4-BIT BIDIRECTIONAL COUNTERS (WITH 3-STATE OUTPUTS) 4-BIT BIDIRECTIONAL COUNTERS (WITH 3-STATE OUTPUTS)

MC54/74F568 MC54/74F569 4-BIT BIDIRECTIONAL COUNTERS (WITH 3-STATE OUTPUTS) 4-BIT BIDIRECTIONAL COUNTERS (WITH 3-STATE OUTPUTS) 4-BIT BIDIRECTIONAL COUNTERS (WITH 3-STATE OUTPUTS) The MC54/ 74F568 and MC54/74F569 are fully synchronous, reversible counters with 3-state outputs. The F568 is a BCD decade counter; the F569 is a binary

More information

Chapter 7 Memory and Programmable Logic

Chapter 7 Memory and Programmable Logic EEA091 - Digital Logic 數位邏輯 Chapter 7 Memory and Programmable Logic 吳俊興國立高雄大學資訊工程學系 2006 Chapter 7 Memory and Programmable Logic 7-1 Introduction 7-2 Random-Access Memory 7-3 Memory Decoding 7-4 Error

More information

NS8050U MICROWIRE PLUSTM Interface

NS8050U MICROWIRE PLUSTM Interface NS8050U MICROWIRE PLUSTM Interface National Semiconductor Application Note 358 Rao Gobburu James Murashige April 1984 FIGURE 1 Microwire Mode Functional Configuration TRI-STATE is a registered trademark

More information

Point System (for instructor and TA use only)

Point System (for instructor and TA use only) EEL 4744C - Drs. George and Gugel Spring Semester 2002 Final Exam NAME SS# Closed book and closed notes examination to be done in pencil. Calculators are permitted. All work and solutions are to be written

More information

LH28F320S3TD-L M-bit (2 MB x 8/1 MB x 16 x 2-Bank) Smart 3 Dual Work Flash Memory DESCRIPTION FEATURES LH28F320S3TD-L10

LH28F320S3TD-L M-bit (2 MB x 8/1 MB x 16 x 2-Bank) Smart 3 Dual Work Flash Memory DESCRIPTION FEATURES LH28F320S3TD-L10 DESCRIPTION The LH28F32S3TD-L Dual Work flash memory with Smart 3 technology is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications, having high programming

More information

Configuring the Élan SC300 Device s Internal CGA Controller for a Specific LCD Panel

Configuring the Élan SC300 Device s Internal CGA Controller for a Specific LCD Panel Configuring the Élan SC300 Device s Internal CGA Controller for a Specific LCD Panel Application Note This application note explains how to determine if a specific LCD panel is supported by the Élan TM

More information

FM25F01 1M-BIT SERIAL FLASH MEMORY

FM25F01 1M-BIT SERIAL FLASH MEMORY FM25F01 1M-BIT SERIAL FLASH MEMORY Dec. 2014 FM25F01 1M-BIT SERIAL FLASH MEMORY Ver. 1.2 1 INFORMATION IN THIS DOCUMENT IS INTENDED AS A REFERENCE TO ASSIST OUR CUSTOMERS IN THE SELECTION OF SHANGHAI FUDAN

More information

ST10F273M Errata sheet

ST10F273M Errata sheet Errata sheet 16-bit MCU with 512 KBytes Flash and 36 KBytes RAM memories Introduction This errata sheet describes all the functional and electrical problems known in the ABG silicon version of the ST10F273M.

More information

LH28F160SGED-L M-bit (512 kb x 16 x 2-Bank) SmartVoltage Dual Work Flash Memory DESCRIPTION FEATURES LH28F160SGED-L10

LH28F160SGED-L M-bit (512 kb x 16 x 2-Bank) SmartVoltage Dual Work Flash Memory DESCRIPTION FEATURES LH28F160SGED-L10 DESCRIPTION The LH28F6SGED-L Dual Work flash memory with SmartVoltage technology is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. The LH28F6SGED-

More information

V6118 EM MICROELECTRONIC - MARIN SA. 2, 4 and 8 Mutiplex LCD Driver

V6118 EM MICROELECTRONIC - MARIN SA. 2, 4 and 8 Mutiplex LCD Driver EM MICROELECTRONIC - MARIN SA 2, 4 and 8 Mutiplex LCD Driver Description The is a universal low multiplex LCD driver. The version 2 drives two ways multiplex (two blackplanes) LCD, the version 4, four

More information

Is Now Part of To learn more about ON Semiconductor, please visit our website at

Is Now Part of To learn more about ON Semiconductor, please visit our website at Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC

More information

82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE

82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE Y Y Y Y Y 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE Compatible with all Intel and Most Other Microprocessors High Speed Zero Wait State Operation with 8 MHz 8086 88 and 80186 188 24 Programmable I

More information

OBSOLETE. CMOS 80 MHz Monolithic (18) Color Palette RAM-DACs ADV478/ADV471

OBSOLETE. CMOS 80 MHz Monolithic (18) Color Palette RAM-DACs ADV478/ADV471 a FEATURES Personal System/2* Compatible 80 MHz Pipelined Operation Triple 8-Bit (6-Bit) D/A Converters 256 24(18) Color Palette RAM 15 24(18) Overlay Registers RS-343A/RS-170 Compatible Outputs Sync on

More information

Chapter 2. Digital Circuits

Chapter 2. Digital Circuits Chapter 2. Digital Circuits Logic gates Flip-flops FF registers IC registers Data bus Encoders/Decoders Multiplexers Troubleshooting digital circuits Most contents of this chapter were covered in 88-217

More information

HT162X HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 COM

HT162X HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 COM Crystalfontz Thiscontrolerdatasheetwasdownloadedfrom htp:/www.crystalfontz.com/controlers/ HT1620 RAM Mapping 324 LCD Controller for I/O MCU Features Logic operating voltage: 2.4V~3.3V LCD voltage: 3.6V~4.9V

More information

SignalTap Analysis in the Quartus II Software Version 2.0

SignalTap Analysis in the Quartus II Software Version 2.0 SignalTap Analysis in the Quartus II Software Version 2.0 September 2002, ver. 2.1 Application Note 175 Introduction As design complexity for programmable logic devices (PLDs) increases, traditional methods

More information

Comparing Low Density SPI EEPROM with Macronix Serial NOR Flash

Comparing Low Density SPI EEPROM with Macronix Serial NOR Flash Comparing Low Density SPI EEPROM with Macronix Serial NOR Flash 1. Introduction This application note serves as a guide to compare low density SPI EEPROM with Macronix 512Kb low density Serial NOR Flash.

More information

Multi-Media Card (MMC) DLL Tuning

Multi-Media Card (MMC) DLL Tuning Application Report Multi-Media Card (MMC) DLL Tuning Shiou Mei Huang ABSTRACT This application report describes how to perform DLL tuning with Multi-Media Cards (MMCs) at 192 MHz (SDR14, HS2) on the OMAP5,

More information

64CH SEGMENT DRIVER FOR DOT MATRIX LCD

64CH SEGMENT DRIVER FOR DOT MATRIX LCD 64CH SEGMENT DRIVER FOR DOT MATRIX LCD INTRODUCTION The (TQFP type: S6B2108) is a LCD driver LSI with 64 channel output for dot matrix liquid crystal graphic display systems. This device consists of the

More information

STi5105 High-performance advanced SD decoder for set-top box Features

STi5105 High-performance advanced SD decoder for set-top box Features High-performance advanced SD decoder for set-top box Data Brief Features Enhanced ST20 32-bit VL-RISC CPU 200 MHz, single cycle cache, 4 Kbyte instruction cache, 4 Kbyte data cache, 2 Kbyte SRAM Unified

More information

Mask Set Errata for Mask 1M07J

Mask Set Errata for Mask 1M07J Mask Set Errata MSE9S08SH32_1M07J Rev. 3, 4/2009 Mask Set Errata for Mask 1M07J Introduction This report applies to mask 1M07J for these products: MC9S08SH32 MCU device mask set identification The mask

More information

Clock Networks in the ArcticLink Solution Platform

Clock Networks in the ArcticLink Solution Platform Clock Networks in the ArcticLink Solution Platform QuickLogic Application Note 92 Introduction The ability to provide robust clocking to various logic elements in a device is critical. Poor clock networks

More information

LH28F800SG-L/SGH-L (FOR TSOP, CSP)

LH28F800SG-L/SGH-L (FOR TSOP, CSP) LH28F8SG-L/SGH-L (FOR TSOP, CSP) DESCRIPTION The LH28F8SG-L/SGH-L flash memories with SmartVoltage technology are high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications.

More information

HCS08 SG Family Background Debug Mode Entry

HCS08 SG Family Background Debug Mode Entry Freescale Semiconductor Application Note Document Number: AN3762 Rev. 0, 08/2008 HCS08 SG Family Background Debug Mode Entry by: Carl Hu Sr. Field Applications Engineer Kokomo, IN, USA 1 Introduction The

More information

Unit 3: Parallel I/O and Handshaking for LCD Control

Unit 3: Parallel I/O and Handshaking for LCD Control 1300 Henley Court Pullman, WA 99163 509.334.6306 www.store.digilentinc.com Unit 3: Parallel I/O and Handshaking for LCD Control Revised March 10, 2017 This manual applies to Unit 3 1 Introduction Throughout

More information

Lecture 2: Digi Logic & Bus

Lecture 2: Digi Logic & Bus Lecture 2 http://www.du.edu/~etuttle/electron/elect36.htm Flip-Flop (kiikku) Sequential Circuits, Bus Online Ch 20.1-3 [Sta10] Ch 3 [Sta10] Circuits with memory What moves on Bus? Flip-Flop S-R Latch PCI-bus

More information

SHA-256 Module Specification

SHA-256 Module Specification SHA-256 Module Specification 1 Disclaimer Systemyde International Corporation reserves the right to make changes at any time, without notice, to improve design or performance and provide the best product

More information

Integrated Circuit for Musical Instrument Tuners

Integrated Circuit for Musical Instrument Tuners Document History Release Date Purpose 8 March 2006 Initial prototype 27 April 2006 Add information on clip indication, MIDI enable, 20MHz operation, crystal oscillator and anti-alias filter. 8 May 2006

More information

WINTER 15 EXAMINATION Model Answer

WINTER 15 EXAMINATION Model Answer Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate

More information

STEVAL-IFN003V1. PMSM FOC motor driver based on the L6230 and STM32F103. Features. Description

STEVAL-IFN003V1. PMSM FOC motor driver based on the L6230 and STM32F103. Features. Description STEVAL-IFN003V1 Features PMSM FOC motor driver based on the L6230 and STM32F103 Data brief Input range: 8 V up to 48 V (up to 45 W) STMicroelectronics ARM Cortex-M3 corebased STM32F103 microcontroller

More information

FPGA Design. Part I - Hardware Components. Thomas Lenzi

FPGA Design. Part I - Hardware Components. Thomas Lenzi FPGA Design Part I - Hardware Components Thomas Lenzi Approach We believe that having knowledge of the hardware components that compose an FPGA allow for better firmware design. Being able to visualise

More information

PEEL 18CV8-5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device

PEEL 18CV8-5/-7/-10/-15/-25 CMOS Programmable Electrically Erasable Logic Device PEEL 18V8-5/-7/-10/-15/-25 MOS Programmable Electrically Erasable Logic Device Multiple Speed, Power, Temperature Options Speeds ranging from 5ns to 25ns Power as low as 37mA at 25MHz ommercial and ndustrial

More information

Interfacing the TLC5510 Analog-to-Digital Converter to the

Interfacing the TLC5510 Analog-to-Digital Converter to the Application Brief SLAA070 - April 2000 Interfacing the TLC5510 Analog-to-Digital Converter to the TMS320C203 DSP Perry Miller Mixed Signal Products ABSTRACT This application report is a summary of the

More information

Table 1. Summary of MCF5223x Errata

Table 1. Summary of MCF5223x Errata Freescale Semiconductor MCF52235DE Chip Errata Rev 9, 02/2015 MCF52235 Chip Errata Silicon Revision: All This document identifies implementation differences between the MCF5223x processors and the description

More information

LH28F160S3-L/S3H-L. 16 M-bit (2 MB x 8/1 MB x 16) Smart 3 Flash Memories (Fast Programming) DESCRIPTION FEATURES LH28F160S3-L/S3H-L

LH28F160S3-L/S3H-L. 16 M-bit (2 MB x 8/1 MB x 16) Smart 3 Flash Memories (Fast Programming) DESCRIPTION FEATURES LH28F160S3-L/S3H-L DESCRIPTION The LH28F6S3-L/S3H-L flash memories with Smart 3 technology are high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications, having high programming performance

More information

Integration Note. Any feature not specifically noted as supported should be assumed to be unsupported.

Integration Note. Any feature not specifically noted as supported should be assumed to be unsupported. Integration Note Manufacturer: Model Number(s): Crestron Processor Version: Driver Developer: Sky (UK) Sky+, Sky+ HD, Sky Multi-room Tested on 3 Series Processors, support for other versions not guaranteed

More information

L9822E OCTAL SERIAL SOLENOID DRIVER

L9822E OCTAL SERIAL SOLENOID DRIVER L9822E OCTAL SERIAL SOLENOID DRIVER EIGHT LOW RDSon DMOS OUTPUTS (0.5Ω AT IO = 1A @ 25 C VCC = 5V± 5%) 8 BIT SERIAL INPUT DATA (SPI) 8 BIT SERIAL DIAGNOSTIC OUTPUT FOR OVERLOAD AND OPEN CIRCUIT CONDITIONS

More information

VT5365. Single-chip optical mouse sensor for wireless applications. Features. Applications. Technical specifications. Description.

VT5365. Single-chip optical mouse sensor for wireless applications. Features. Applications. Technical specifications. Description. Single-chip optical mouse sensor for wireless applications Data Brief Features One chip solution with internal micro and minimal external circuitry 1.8V (single battery) or 2.0 V to 3.2 V (serial batteries)

More information

Side Street. Traffic Sensor. Main Street. Walk Button. Traffic Lights

Side Street. Traffic Sensor. Main Street. Walk Button. Traffic Lights 6.111 Laboratory 2 1 Laboratory 2 Finite State Machines Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 - Introductory Digital Systems Laboratory Handout

More information

A/D and D/A convertor 0(4) 24 ma DC, 16 bits

A/D and D/A convertor 0(4) 24 ma DC, 16 bits A/D and D/A convertor 0(4) 24 ma DC, 6 bits ZAT-DV The board contains independent isolated input A/D convertors for measurement of DC current signals 0(4) ma from technological convertors and sensors and

More information

TIL311 HEXADECIMAL DISPLAY WITH LOGIC

TIL311 HEXADECIMAL DISPLAY WITH LOGIC TIL311 Internal TTL MSI IC with Latch, Decoder, and Driver 0.300-Inch (7,62-mm) Character Height Wide Viewing Angle High Brightness Left-and-Right-Hand Decimals Constant-Current Drive for Hexadecimal Characters

More information

S6B CH SEGMENT DRIVER FOR DOT MATRIX LCD

S6B CH SEGMENT DRIVER FOR DOT MATRIX LCD 64 CH SEGMENT DRIVER FOR DOT MATRIX LCD June. 2000. Ver. 0.0 Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by

More information

StickIt! VGA Manual. How to install and use your new StickIt! VGA module

StickIt! VGA Manual. How to install and use your new StickIt! VGA module StickIt! VGA Manual How to install and use your new StickIt! VGA module XESS is disclosing this Document and Intellectual Property (hereinafter the Design ) to you for use in the development of designs

More information

description SCAS668A NOVEMBER 2001 REVISED MARCH 2003 Copyright 2003, Texas Instruments Incorporated

description SCAS668A NOVEMBER 2001 REVISED MARCH 2003 Copyright 2003, Texas Instruments Incorporated SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690 Choice of Memory Organizations SN74V3640 1024 36 Bit SN74V3650 2048 36 Bit SN74V3660 4096 36 Bit SN74V3670 8192 36 Bit SN74V3680 16384 36

More information

DUOLABS Spa. Conditional Access Module Hardware Brief. CA Module User Guide V0.2

DUOLABS Spa. Conditional Access Module Hardware Brief. CA Module User Guide V0.2 Conditional Access Module Hardware Brief CA Module User Guide V0.2 Index Conditional Access Module... 1 CA Module User Guide... 1 Revision history... Errore. Il segnalibro non è definito. Index... 1 Reference...

More information

HT9B92 RAM Mapping 36 4 LCD Driver

HT9B92 RAM Mapping 36 4 LCD Driver RAM Mapping 36 4 LCD Driver Feature Logic Operating Voltage: 2.4V~5.5V Integrated oscillator circuitry Bias: 1/2 or 1/3; Duty: 1/4 Internal LCD bias generation with voltage-follower buffers External pin

More information

IMS B007 A transputer based graphics board

IMS B007 A transputer based graphics board IMS B007 A transputer based graphics board INMOS Technical Note 12 Ray McConnell April 1987 72-TCH-012-01 You may not: 1. Modify the Materials or use them for any commercial purpose, or any public display,

More information

LAX_x Logic Analyzer

LAX_x Logic Analyzer Legacy documentation LAX_x Logic Analyzer Summary This core reference describes how to place and use a Logic Analyzer instrument in an FPGA design. Core Reference CR0103 (v2.0) March 17, 2008 The LAX_x

More information

Industrial Diode Laser (IDL) System IDL Series

Industrial Diode Laser (IDL) System IDL Series COMMERCIAL LASERS Industrial Diode Laser (IDL) System IDL Series Key Features Round, top-hat beam profile for uniform power distribution Warranted for full rated power in either pulsed or continuous wave

More information

Agilent I 2 C Debugging

Agilent I 2 C Debugging 546D Agilent I C Debugging Application Note1351 With embedded systems shrinking, I C (Inter-integrated Circuit) protocol is being utilized as the communication channel of choice because it only needs two

More information

PCI Express JPEG Frame Grabber Hardware Manual Model 817 Rev.E April 09

PCI Express JPEG Frame Grabber Hardware Manual Model 817 Rev.E April 09 PCI Express JPEG Frame Grabber Hardware Manual Model 817 Rev.E April 09 Table of Contents TABLE OF CONTENTS...2 LIMITED WARRANTY...3 SPECIAL HANDLING INSTRUCTIONS...4 INTRODUCTION...5 OPERATION...6 Video

More information

Using the Synchronized Pulse-Width Modulation etpu Function by:

Using the Synchronized Pulse-Width Modulation etpu Function by: Freescale Semiconductor Application Note Document Number: AN2854 Rev. 1, 10/2008 Using the Synchronized Pulse-Width Modulation etpu Function by: Geoff Emerson Microcontroller Solutions Group This application

More information

DT3162. Ideal Applications Machine Vision Medical Imaging/Diagnostics Scientific Imaging

DT3162. Ideal Applications Machine Vision Medical Imaging/Diagnostics Scientific Imaging Compatible Windows Software GLOBAL LAB Image/2 DT Vision Foundry DT3162 Variable-Scan Monochrome Frame Grabber for the PCI Bus Key Features High-speed acquisition up to 40 MHz pixel acquire rate allows

More information

SN74V263, SN74V273, SN74V283, SN74V , , , V CMOS FIRST-IN, FIRST-OUT MEMORIES

SN74V263, SN74V273, SN74V283, SN74V , , , V CMOS FIRST-IN, FIRST-OUT MEMORIES Choice of Memory Organizations SN74V263 8192 18/16384 9 SN74V273 16384 18/32768 9 SN74V283 32768 18/65536 9 SN74V293 65536 18/131072 9 166-MHz Operation 6-ns Read/Write Cycle Time User-Selectable Input

More information

MSP430-HG2231 development board Users Manual

MSP430-HG2231 development board Users Manual MSP0-HG development board Users Manual All boards produced by Olimex are ROHS compliant Revision Initial, June 0 Copyright(c) 0, OLIMEX Ltd, All rights reserved Page INTRODUCTION: MSP0-HG is header board

More information

Engineering Bulletin. General Description. Provided Files. AN2297/D Rev. 0.1, 6/2002. Implementing an MGT5100 Ethernet Driver

Engineering Bulletin. General Description. Provided Files. AN2297/D Rev. 0.1, 6/2002. Implementing an MGT5100 Ethernet Driver Engineering Bulletin AN2297/D Rev. 0.1, 6/2002 Implementing an MGT5100 Ethernet Driver General Description To write an ethernet driver for the MGT5100 Faster Ethernet Controller (FEC) under CodeWarrior

More information

Microcontrollers and Interfacing week 7 exercises

Microcontrollers and Interfacing week 7 exercises SERIL TO PRLLEL CONVERSION Serial to parallel conversion Microcontrollers and Interfacing week exercises Using many LEs (e.g., several seven-segment displays or bar graphs) is difficult, because only a

More information

WORD-WIDE FlashFile MEMORY FAMILY 28F160S3, 28F320S3

WORD-WIDE FlashFile MEMORY FAMILY 28F160S3, 28F320S3 WORD-WIDE FlashFile MEMORY FAMILY Includes Extended Temperature Specifications n Two 32-Byte Write Buffers 2.7 µs per Byte Effective Programming Time n Low Voltage Operation 2.7V or 3.3V V CC 2.7V, 3.3V

More information

Scan. This is a sample of the first 15 pages of the Scan chapter.

Scan. This is a sample of the first 15 pages of the Scan chapter. Scan This is a sample of the first 15 pages of the Scan chapter. Note: The book is NOT Pinted in color. Objectives: This section provides: An overview of Scan An introduction to Test Sequences and Test

More information

Memory Interfaces Data Capture Using Direct Clocking Technique Author: Maria George

Memory Interfaces Data Capture Using Direct Clocking Technique Author: Maria George Application Note: Virtex-4 Family R XAPP701 (v1.4) October 2, 2006 Memory Interfaces Data Capture Using Direct Clocking Technique Author: Maria George Summary This application note describes the direct-clocking

More information

M24LR04E-R, M24LR16E-R, M24LR64E-R Errata sheet

M24LR04E-R, M24LR16E-R, M24LR64E-R Errata sheet M24LR04E-R, M24LR16E-R, M24LR64E-R Errata sheet M24LR04E-R, M24LR16E-R and M24LR64E-R device limitations Silicon identification This errata sheet applies to STMicroelectronics M24LR04E-R, M24LR16E-R and

More information

FSM Cookbook. 1. Introduction. 2. What Functional Information Must be Modeled

FSM Cookbook. 1. Introduction. 2. What Functional Information Must be Modeled FSM Cookbook 1. Introduction Tau models describe the timing and functional information of component interfaces. Timing information specifies the delay in placing values on output signals and the timing

More information

Microincrements IP67-related solutions

Microincrements IP67-related solutions technology microincrements Keywords microincrements Distributed Clocks EtherCAT EtherCAT Box IP 67 EP50 encoder Microincrements IP67-related solutions This application example describes how an EP50 EtherCAT

More information

PRODUCT SPECIFICATIONS. Integrated Circuits Group LH28F160BJHE-TTL90. Flash Memory 16M (1MB 16 / 2MB 8) (Model No.: LHF16J04)

PRODUCT SPECIFICATIONS. Integrated Circuits Group LH28F160BJHE-TTL90. Flash Memory 16M (1MB 16 / 2MB 8) (Model No.: LHF16J04) PRODUCT SPECIFICATIONS Integrated Circuits Group LH28F6BJHE-TTL9 Flash Memory 6M (MB 6 / 2MB 8) (Model No.: LHF6J4) Spec No.: EL525 Issue Date: February 4, 23 LHF6J4 Handle this document carefully for

More information

ArcticLink III VX6 Solution Platform Data Sheet

ArcticLink III VX6 Solution Platform Data Sheet ArcticLink III VX6 Solution Platform Data Sheet Dual Output High Definition Visual Enhancement Engine (VEE HD+) and Display Power Optimizer (DPO HD+) Solution Platform Highlights High Definition Visual

More information

APPLICABILITY TABLE. SW Versions. GE Family ( Embedded ) GE910-QUAD V xx5 GE910-GNSS

APPLICABILITY TABLE. SW Versions. GE Family ( Embedded ) GE910-QUAD V xx5 GE910-GNSS APPLICABILITY TABLE GE Family ( Embedded ) GE910-QUAD GE910-GNSS GE910-QUAD AUTO GE910-QUAD V3 SW Versions 13.00.xx4 13.00.xx5 16.00.xx3 Note: the features described in the present document are provided

More information

Contents Circuits... 1

Contents Circuits... 1 Contents Circuits... 1 Categories of Circuits... 1 Description of the operations of circuits... 2 Classification of Combinational Logic... 2 1. Adder... 3 2. Decoder:... 3 Memory Address Decoder... 5 Encoder...

More information

Self Restoring Logic (SRL) Cell Targets Space Application Designs

Self Restoring Logic (SRL) Cell Targets Space Application Designs TND6199/D Rev. 0, SEPT 2015 Self Restoring Logic (SRL) Cell Targets Space Application Designs Semiconductor Components Industries, LLC, 2015 September, 2015 Rev. 0 1 Publication Order Number: TND6199/D

More information

Serial Peripheral Interface

Serial Peripheral Interface Serial Peripheral Interface ECE 362 https://engineering.purdue.edu/ee362/ Rick Reading Assignment Textbook, Chapter 22, Serial Communication Protocols, pp. 527 598 It s a long chapter. Let s first look

More information

Intel Ethernet SFP+ Optics

Intel Ethernet SFP+ Optics Product Brief Intel Ethernet SFP+ Optics Network Connectivity Intel Ethernet SFP+ Optics SR and LR Optics for the Intel Ethernet Server Adapter X520 Family Hot-pluggable SFP+ footprint Supports rate selectable

More information

MT8812 ISO-CMOS. 8 x 12 Analog Switch Array. Features. Description. Applications

MT8812 ISO-CMOS. 8 x 12 Analog Switch Array. Features. Description. Applications MT882 8 x 2 Analog Switch Array Features Internal control latches and address decoder Short set-up and hold times Wide operating voltage: 4.5V to 4.5V 4Vpp analog signal capability R ON 65 max. @ V DD

More information

Generates a selectable interrupt pulse at the entry and exit of the horizontal and vertical blanking intervals

Generates a selectable interrupt pulse at the entry and exit of the horizontal and vertical blanking intervals 1.61 Features Fully programmable screen size support up to HVGA resolution including: QVGA (320x240) @ 60 Hz 16 bpp WQVGA (480x272) @ 60 Hz 16 bpp HVGA (480x320) @ 60 Hz 16 bpp Supports virtual screen

More information

GM68020H. DisplayPort receiver. Features. Applications

GM68020H. DisplayPort receiver. Features. Applications DisplayPort receiver Data Brief Features DisplayPort 1.1a compliant receiver HDCP 1.3 support DisplayPort link comprising four main lanes and one auxiliary channel Input bandwidth sufficient to receive

More information

Application Note. Traffic Signal Controller AN-CM-231

Application Note. Traffic Signal Controller AN-CM-231 Application Note AN-CM-231 Abstract This application note describes how to implement a traffic controller that can manage traffic passing through the intersection of a busy main street and a lightly used

More information

STEVAL-IKR001V7D. Sub Ghz transceiver daughterboard with power amplifier based on the SPIRIT1. Features. Description

STEVAL-IKR001V7D. Sub Ghz transceiver daughterboard with power amplifier based on the SPIRIT1. Features. Description Sub Ghz transceiver daughterboard with power amplifier based on the SPIRIT1 Data brief Features SPIRIT1 low power sub GHz transceiver in a standalone RF module tuned for 169 MHz band with external power

More information