EMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP

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1 EMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP 1

2 Chapter Overview Latches Gated Latches Edge-triggered flip-flops Master-slave flip-flops Flip-flop operating characteristics Flip-flop applications 2

3 Introduction Latches and flip-flop are the basic single-bit memory elements used to build sequential circuit with one or two inputs/outputs, designed using individual logic gates and feedback loops. Latches are bistable devices whose state normally depend on asynchronous input. Edge triggered FFs are bistable devices which synchronous input whose state depend on the input only at trigerring transition of clock pulse. 3

4 Introduction (cond..) Latches: The output of a latch depends on its current inputs and on its previous output and its change of state can happen at any time when its inputs change. Flip-Flop: The output of a flip-flop also depends on current inputs and its previous output but the change of state occurs at specific times determined by a clock input. The basic difference between Latches & FFs: - the way in which they are changed from one state to the another state. 4

5 Introduction (cond..) Latches: S-R Latch (active high input & active low input) Gated S-R Latch Gated D-Latch Flip-Flops: Edge-Triggered Flip-Flop (S-R, J-K, D) (eg, J-K FFs = a type of FFs that can operate in set, reset, no change and toggle modes. Asynchronous Inputs Master-Slave Flip-Flop Flip-Flop Operating Characteristics Flip-Flop Applications 5

6 Latches Type of temporary storage device that has two stable (bistable) states Similar to flip-flop the outputs are connected back to opposite inputs S-R latch, Gated/Enabled S-R latch and Gated D latch (i) Eg, active high input SR latch form with 2 cross-coupled NOR gates. (ii) Eg, active low input SR latch form with 2 cross-coupled NAND gates. Output of each gate is connect to an input of opposite gate. Output of latch always complement of each others, - when Q is high, Q is low. - when Q is low, Q is high. 6

7 S-R Latch (Set-Reset Latch) (a) active-high input (b) active-low input 7

8 S-R latch (cont..) Active-HIGH SR latch. (a) Logic diagrams. (b) Function table where Q + denotes the output Q in response to the inputs. (c) Two logic symbols. 8

9 S-R latch (cont..) SR Active-LOW latch. (a) Logic diagrams. (b) Function table where Q + denotes the output Q in response to the inputs. (c) Two logic symbols. 9

10 S-R latch (cont..) Example 1 If S and R waveform is applied to the input of latch in given figures, determine the waveform that will be observed on the Q output. Assume Q is initially LOW. 10

11 S-R latch (cont..) Answer 1 If S and R waveform is applied to the input of latch in given figures, determine the waveform that will be observed on the Q output. Assume Q is initially LOW. 11

12 Gated S-R Latch Gated SR latch. (a) Logic diagram. (b) Function table where Q + denotes the output Q in response to the inputs. (c) Two logic symbols. 12

13 Gated S-R Latch (cont..) Example 2 Determine the Q output waveform if the input are applied to Gated S-R Latch that is initially RESET. 13

14 Gated S-R Latch (cont..) Answer 2 Determine the Q output waveform if the input are applied to Gated S-R Latch that is initially RESET. 14

15 Gated D Latch Gated D latch. (a) Logic diagram. (b) Logic symbol. 15

16 Gated D Latch (cont..) (a) Gated D latch with Logic IC 74LS75. (b) Truth table for Gated D latch 16

17 Edge-Triggered Flip-Flop Logic All the above flip-flops have the triggering input called clock (CLK/C) Dynamic input indicator (small triangular) shown the clock 17

18 Edge-Triggered Flip-Flop Logic (cont..) A clock signal is a periodic square wave that indefinitely switches values from 0 to 1 and 1 to 0 at fixed intervals. 1 Clock signal 0 Rising edges of the clock (Positive-edge triggered) Falling edges of the clock (Negative-edge triggered) Clock Cycle Time

19 Edge-Triggered Flip-Flop Logic (cont..) Example 3 Determine the Q and Q output waveform of FF for S-R FFs for SR and CLK input. Assume positive edge-triggered FF is RESET. 19

20 Edge-Triggered Flip-Flop Logic (cont..) Answer 3 Determine the Q and Q output waveform of FF for S-R FFs for SR and CLK input. Assume positive edge-triggered FF is RESET. 20

21 Edge-Triggered Flip-Flop Logic (cont..) Example 4 Given the waveform for D input and the clock, determine the Q output waveform if the FF start out RESET. 21

22 Edge-Triggered Flip-Flop Logic (cont..) Answer 4 Given the waveform for D input and the clock, determine the Q output waveform if the FF start out RESET. 22

23 Edge-Triggered JK Flip-Flop The J-K flip-flop is more versatile than the D flip flop. In addition to the clock input, it has two inputs, labeled J and K. When both J and K = 1, the output changes states (toggles) on the active clock edge (in this case, the rising edge). Inputs Outputs J K CLK Q Q Comments Q 0 0 Q 0 1 No change RESET SET 1 1 Q 0 Q 0 Toggle 23

24 Edge-Triggered JK Flip-Flop (cont..) Example 5 Positive edge-triggered. Draw the waveform for Q output. 24

25 Edge-Triggered JK Flip-Flop (cont..) Answer 5 Positive edge-triggered. Draw the waveform for Q output. 25

26 JK Flip-Flop with active-low preset and clear inputs Example 6 For positive edge triggered JK FF with preset and clear input, determine Q output for the input in timing diagram if Q initially LOW. 26

27 Master-slave SR FF Master-slave SR flip-flop (a) Logic diagram using gated SR latches. (b) Flip-flop action during the control signal. (c) Function table where Q + denotes the output Q in response to the inputs. (d) Two logic symbols. 27

28 Master-slave SR FF (cont..) Timing diagram for a master-slave SR flip-flop. 28

29 Flip-Flop Application Parallel Data Storage Frequency Division Counting 29

30 Flip-Flop Application (cont..) (a) Parallel Data Storage 30

31 Flip-Flop Application (cont..) (b) Frequency Division 31

32 Flip-Flop Application (cont..) Example 7 Two J-K flip-flops used to divide the clock frequency by 4. Q A is one-half and Q B is one-fourth the frequency of CLK. 32

33 Flip-Flop Application (cont..) (c) Counting 33

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