OBSOLETE FUNCTIONAL BLOCK DIAGRAM 256-COLOR/GAMMA PALETTE RAM. RED 256 x 10. GREEN 256 x 10 CONTROL REGISTERS PIXEL MASK REGISTER TEST REGISTERS MODE

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1 a FEATURES 22 MHz, 24-Bit (3-Bit Gamma Corrected) True Color Triple -Bit Gamma Correcting D/A Converters Triple 256 (256 3) Color Palette RAM On-Chip Clock Control Circuit Palette Priority Select Registers RS-343A/RS-7 Compatible Analog Outputs TTL Compatible Digital Inputs Standard MPU l/o Interface -Bit Parallel Structure +2 Byte Structure Programmable Piel Port: 24-Bit and -Bit (Pseudo) Piel Data Serializer Multipleed Piel Input Ports; :, 2: +5 V CMOS Monolithic Construction -Lead Plastic Quad Flatpack (QFP) Thermally Enhanced to Achieve JC <. C/W MODES OF OPERATION 24-Bit True Color (3-Bit Gamma MHz -Bit Pseudo Color 5-Bit True Color CMOS 22 MHz True-Color Graphics Triple -Bit Video RAM-DAC FUNCTIONAL BLOCK DIAGRAM APPLICATIONS High Resolution, True Color Graphics Professional Color Prepress Imaging GENERAL DESCRIPTION The (ADV ) is a complete analog output, Video RAM-DAC on a single CMOS monolithic chip. The part is specifically designed for use in high performance, color graphics workstations. The integrates a number of graphic functions onto one device allowing 24-bit direct True-Color operation at the maimum screen update rate of 22 MHz. The implements 3-bit True Color in 24-bit frame buffer designs. The part also supports other modes, including 5-bit True Color and -bit Pseudo or Indeed Color. Either the Red, Green or Blue input piel ports can be used for Pseudo Color. The device consists of three, high speed, -bit, video D/A converters (RGB), three 256 (one 256 3) color look-up tables, palette priority selects, a piel input data multipleer/ serializer and a clock generator/divider circuit. The implements : and 2: piel data multipleing. The onboard palette priority select inputs enable multiple palette devices to be connected together for use in multipalette and window (Continued on page ) ADV is a registered trademark of Analog Devices, Inc. V AA 256-COLOR/GAMMA PALETTE RAM (R R7), (G G7), (B B7) COLOR DATA A B PALETTE SELECTS (PS, PS) LOADIN LOAD PRGCK SCKIN SCK SYNC BLANK CLOCK CLOCK P I X E L P O R T 4 4 MUX 2: CLOCK CONTROL CLOCK DIVIDE & SYNCHRONIZATION CIRCUIT 32, 6,, 4, 2 ECL TO CMOS MUX 2: ADDRESS ADDR (A- A5) 2 MODE (MR) 256 CONTROL S PIXEL MASK TEST S ID MPU PORT COMMAND S (CR-CR3) REVISION (+2) -BIT IOR DAC IOR -BIT DAC -BIT DAC DATA TO PALETTES 3 SYNC PUT VOLTAGE REFERENCE CIRCUIT COLOR S IOG IOG IOB IOB I PLL SYNC V REF R SET COMP CE R/W C C D9 D GND Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Bo 96, Norwood, MA , U.S.A. Tel: 67/ Fa: 67/326-73

2 SPECIFICATIONS (V AA = +5 V; V REF = V; R SET = 2. IOR, IOG, IOB (R L = 37.5, C L = pf); IOR, IOG, IOB = GND. All specifications T MIN to T MAX 2 unless otherwise noted.) Parameter All Versions Unit Test Conditions/Comments STATIC PERFORMANCE Resolution (Each DAC) Bits Accuracy (Each DAC) Integral Nonlinearity ± LSB ma Differential Nonlinearity ± LSB ma Guaranteed Monotonic Gray Scale Error ± 5 % Gray Scale ma Coding Binary DIGITAL INPUTS (Ecluding CLOCK, CLOCK) Input High Voltage, V INH 2 V min Input Low Voltage, V INL. V ma Input Current, I IN ± µa ma V IN =.4 V or 2.4 V Input Capacitance, C IN pf typ CLOCK INPUTS (CLOCK, CLOCK) Input High Voltage, V INH V AA. V min Input Low Voltage, V INL V AA.6 V ma Input Current, I IN ± µa ma V IN =.4 V or 2.4 V Input Capacitance, C IN pf typ DIGITAL PUTS Output High Voltage, V OH 2.4 V min I SOURCE = 4 µa Output Low Voltage, V OL.4 V ma I SINK = 3.2 ma Floating-State Leakage Current 2 µa ma Floating-State Output Capacitance 2 pf typ ANALOG PUTS Gray Scale Current Range 5/22 ma min/ma Output Current White Level Relative to Blank 7.69/2.4 ma min/ma Typically 9.5 ma White Level Relative to Black 6.74/.5 ma min/ma Typically 7.62 ma Black Level Relative to Blank.95/.9 ma min/ma Typically.44 ma Blank Level on IOR, IOB /5 µa min Typically 5 µa Blank Level on IOG 6.29/.96 ma min/ma Typically 7.62 ma Sync Level on IOG /5 µa min/ma Typically 5 µa LSB Size 7.22 µa typ DAC-to-DAC Matching 3 % ma Typically % Output Compliance, V OC /+.4 V min/v ma Output Impedance, R kω typ Output Capacitance, C 3 pf ma I = ma VOLTAGE REFERENCE Voltage Reference Range, V REF.4/.26 V min/v ma V REF =.235 V for Specified Performance Input Current, I VREF +5 µa typ POWER REQUIREMENTS V AA 5 V nom 3 I AA 4 ma ma 22 MHz Parts I AA 37 ma ma 7 MHz Parts I AA 35 ma ma 35 MHz Parts I AA 33 ma ma MHz Parts I AA 35 ma ma 5 MHz Parts Power Supply Rejection Ratio.5 %/% ma Typically.2%/%, COMP =. µf DYNAMIC PERFORMANCE Clock and Data Feedthrough 4, 5 3 db typ Glitch Impulse 5 pv secs typ DAC-to-DAC Crosstalk 6 23 db typ NOTES ± 5% for all versions. 2 Temperature range (T MIN to T MAX ): C to +7 C; T J (Silicon Junction Temperature) C. 3 Piel Port is continuously clocked with data corresponding to a linear ramp. T J = C. 4 Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough. 5 TTL input values are to 3 volts, with input rise/fall times 3 ns, measured the % and 9% points. Timing reference points at 5% for inputs and outputs. 6 DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions. Specifications subject to change without notice. 2

3 TIMING CHARACTERISTICS CLOCK CONTROL AND PIXEL PORT 4 22 MHz 7 MHz 35 MHz MHz 5 MHz Parameter Version Version Version Version Version Units Conditions/Comments 2 (V AA = +5 V; V REF = V; R SET = 2. IOR, IOG, IOB (R L = 37.5, C L = pf); 3 IOR, IOG, IB = GND. All specifications T MIN to T MAX unless otherwise noted.) f CLOCK MHz ma Piel CLOCK Rate t ns min Piel CLOCK Cycle Time t ns min Piel CLOCK High Time t ns min Piel CLOCK Low Time t 4 ns ma Piel CLOCK to LOAD Delay f LOADIN LOADIN Clocking Rate : Multipleing 5 MHz ma 2: Multipleing MHz ma t 5 LOADIN Cycle Time : Multipleing ns min 2: Multipleing ns min t 6 LOADIN High Time : Multipleing ns min 2: Multipleing ns min t 7 LOADIN Low Time : Multipleing ns min 2: Multipleing ns min t ns min Piel Data Setup Time t ns min Piel Data Hold Time t ns min LOAD to LOADIN Delay 5 τ t τ 5 τ 5 τ 5 τ 5 τ 5 ns ma LOAD to LOADIN Delay 6 t PD Pipeline Delay : Multipleing CLOCKs ( CLOCK = t ) 2: Multipleing CLOCKs t 2 ns ma Piel CLOCK to PRGCK Delay t ns ma SCKIN to SCK Delay t ns min BLANK to SCKIN Setup Time t 5 ns min BLANK to SCKIN Hold Time 22 MHz 7 MHz 35 MHz MHz 5 MHz Parameter Version Version Version Version Version Units Conditions/Comments t ns typ Analog Output Delay t 7 ns typ Analog Output Rise/Fall Time t ns typ Analog Output Transition Time t SK ns ma Analog Output Skew (IOR, IOG, IOB) ns typ 22 MHz 7 MHz 35 MHz MHz 5 MHz Parameter Version Version Version Version Version Units Conditions/Comments t ns min R/W, C, C to CE Setup Time t 2 ns min R/W, C, C to CE Hold Time t ns min CE Low Time t ns min CE High Time t ns min CE Asserted to Databus Driven 9 t ns ma CE Asserted to Data Valid 9 t ns ma CE Disabled to Databus Three-Stated ns min t ns min Write Data (D D9) Setup Time t ns min Write Data (D D9) Hold Time 3

4 NOTES TTL input values are to 3 volts, with input rise/fall times 3 ns, measured between the % and 9% points. ECL inputs (CLOCK, CLOCK) are V AA. V to V AA. V, with input rise/fall times 2 ns, measured between the % and 9% points. Timing reference points at 5% for inputs and outputs. Analog output load pf. Databus (D D9) loaded as shown in Figure. Digital output load for LOAD, PRGCK, SCK, I PLL and SYNC 3 pf. 2 ± 5% for all versions. 3 Temperature range (T MIN to T MAX ): C to +7 C; T J (Silicon Junction Temperature) C. 4 Piel Port consists of the following inputs: Piel Inputs: [A, B]; [A, B]; [A, B], Palette Selects: PS [A, B]; PS [A, B]; Piel Controls: SYNC, BLANK; Clock Inputs: CLOCK, CLOCK, LOADIN, SCKIN; Clock Outputs: LOAD, PRGCK, SCK. 5 τ is the LOAD Cycle Time and is a function of the Piel CLOCK Rate and the Multipleing Mode: : multipleing; τ = CLOCK = t ns; 2: multipleing, τ = CLOCK 2 = 2 t ns. 6 These fied values for Pipeline Delay are valid under conditions where t and τ t are met. If either t or τ t are not met, the part will operate but the Pipeline Delay is increased by 2 clock cycles for 2: mode after calibration cycle is performed. 7 Output delay measured from the 5% point of the rising edge of CLOCK to the 5% point of full-scale transition. Output rise/fall time measured between the % and 9% points of full-scale transition. Settling time measured from the 5% point of full-scale transition to the output remaining within ± LSB. (Settling time does not include clock and data feedthrough.) t 23 and t 24 are measured with the load circuit of Figure and defined as the time required for an output to cross.4 V or 2.4 V. 9 t 25 is derived from the measured time taken by the data outputs to change by.5 V when loaded with the circuit of Figure. The measured number is then etrapolated back to remove the effects of charging the pf capacitor. This means that the time, t 25, quoted in the Timing Characteristics is the true value for the device and as such is independent of eternal databus loading capacitances. Specifications subject to change without notice. I SINK TO PUT PIN pf +2.V I SOURCE Figure. Load Circuit for Databus Access and Relinquish Times t 2 CLOCK t t 3 CLOCK LOAD (: MULTIPLEXING) t 4 LOAD (2: MULTIPLEXING) Figure 2. LOAD vs. Piel Clock Input (CLOCK, CLOCK) LOADIN t 5 t 6 t 7 t t 9 PIXEL INPUT DATA* VALID DATA VALID DATA VALID DATA *INCLUDES PIXEL DATA (R-R7, G-G7, B-B7); PALETTE SELECT INPUTS (PS-PS); SYNC; BLANK Figure 3. LOADIN vs. Piel Input Data 4

5 CLOCK t LOAD LOADIN PIXEL INPUT DATA* A N B N A N+ B N+ A N+2 B N+2 DIGITAL INPUT TO ANALOG PUT PIPELINE ANALOG PUT DATA IOR, IOR IOG, IOG IOB, IOB I PLL, SYNC t PD A N- B N- A N B N A N+ B N+ A N+2 B N+2 *INCLUDES PIXEL DATA (R R7, G G7, B B7); PALETTE SELECT INPUTS (PS-PS); SYNC; BLANK Figure 4. Piel Input to Analog Output Pipeline with Minimum LOAD to LOADIN Delay (2: Multiple Mode) CLOCK LOAD τ- t τ LOADIN PIXEL INPUT DATA* A N B N A N+ B N+ A N+2 B N+2 DIGITAL INPUT TO ANALOG PUT PIPELINE ANALOG PUT DATA IOR, IOR IOG, IOG IOB, IOB I PLL, SYNC A N- B N- A N B N A N+ B N+ A N+2 B N+2 t PD *INCLUDES PIXEL DATA (R R7, G G7, B B7); PALETTE SELECT INPUTS (PS PS); SYNC; BLANK Figure 5. Piel Input to Analog Output Pipeline with Maimum LOAD to LOADIN Delay (2: Multiple Mode) CLOCK PRGCK (CLOCK/4) PRGCK (CLOCK/) PRGCK (CLOCK/6) PRGCK (CLOCK/32) t 2 *INLCUDES PIXEL DATA (R-R7, G-G7, B-B7); PALETTE SELECT INPUTS (PS-PS); SYNC; BLANK Figure 6. Piel Clock Input vs. Programmable Clock Output (PRGCK) 5

6 t 3 t 4 SCKIN BLANK t 5 BLANKING PERIOD SCK END OF SCAN LINE (N) START OF SCAN LINE (N+) *INCLUDES PIXEL DATA (R-R7, G-G7, B-B7); PALETTE SELECT INPUTS (PS-PS); SYNC; BLANK Figure 7. Video Data Shift Clock Input (SCKIN) & BLANK vs. Video Data Shift Clock Output (SCK) CLOCK t 6 t ANALOG PUTS IOR, IOR IOG, IOG IOB, IOB I PLL, SYNC WHITE LEVEL 9 % 5 % FULL SCALE TRANSITION t 7 % BLACK LEVEL NOTE: THIS DIAGRAM IS NOT TO SCALE. FOR THE PURPOSES OF CLARITY, THE ANALOG PUT WAVEFORM IS MAGNIFIED IN TIME AND AMPLITUDE W.R.T. THE CLOCK WAVEFORM. I PLL AND SYNC ARE DIGITAL PUT SIGNALS. t 6 IS THE ONLY RELEVANT PUT TIMING SPECIFICATION FOR I PLL AND SYNC. R/W, C, C t 9 CE Figure. Analog Output Response vs. CLOCK t 2 VALID CONTROL DATA t 2 D D9 (READ MODE) D D9 (WRITE MODE) t 24 t 23 R/W = R/W = t 26 t 27 t 22 t 25 Figure 9. Microprocessor Port (MPU) Interface Timing 6

7 RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Ma Units Power Supply V AA Volts Ambient Operating Temperature T A +7 C Reference Voltage V REF Volts Output Load R L 37.5 Ω CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although the features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS V AA to GND V Voltage on Any Digital Pin.... GND.5 V to V AA +.5 V Ambient Operating Temperature (T A ) C to +25 C Storage Temperature (T S ) C to +5 C Junction Temperature (T J ) C Lead Temperature (Soldering, secs) C Vapor Phase Soldering ( minute) C Analog Outputs to GND GND.5 to V AA NOTES Stresses above those listed under Absolute Maimum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Eposure to absolute maimum rating conditions for etended periods may affect device reliability. 2 Analog Output Short Circuit to any Power Supply or Common can be of an indefinite duration. ORDERING GUIDE Speed, 2, 3 22 MHz LS22 MHz LS 7 MHz LS7 5 MHz LS5 35 MHz LS35 NOTES is packaged in a -pin plastic quad flatpack, QFP. 2 All devices are specified for C to +7 C operation. 3 Contact sales office for latest information on package design. ROW D -Lead QFP Configuration ROW C QFP Top View (Not to Scale) ROW A 3 PIN NO. IDENTIFIER 5 ROW B 3 5 WARNING! ESD SENSITIVE DEVICE PIN ASSIGNMENTS Pin Pin Pin No. Mnemonic No. Mnemonic No. Mnemonic SYNC 4 SCK D5 2 BLANK 42 SYNC 2 V AA 3 R A 43 GND 3 D6 4 R B 44 GND 4 D7 5 GND 45 GND 5 D 6 R A 46 GND 6 D9 7 R B 47 G6 A 7 GND R2 A 4 G6 B GND 9 R2 B 49 G7 A 9 IOB R3 A 5 G7 B 9 IOR R3 B 5 PS A 9 IOG 2 R4 A 52 PS B 92 IOB 3 R4 B 53 PS A 93 IOG 4 R5 A 54 PS B 94 V AA 5 R5 B 55 B A 95 I PLL 6 R6 A 56 B B 96 IOR 7 R6 B 57 B A 97 COMP R7 A 5 B B 9 V REF 9 R7 B 5 9 B2 A 99 R SET 2 G A 6 B2 B V AA 2 G B 6 B3 A 22 G A 62 B3 B 23 G B 63 B4 A 24 G2 A 64 B4 B 25 G2 B 65 B5 A 26 NC 66 B5 B 27 G3 A 67 B6 A 2 G3 B 6 B6 B 29 G4 A 69 B7 A 3 G4 B 7 B7 B 3 G5 A 7 CE 32 G5 B 72 R/W 33 CLOCK 73 C 34 CLOCK 74 C 35 LOADIN 75 D 36 LOAD 76 D 37 V AA 77 D2 3 V AA 7 GND 39 PRGCK 79 D3 4 SCKIN D4 NC = NO CONNECT. 7

8 Mnemonic Function PIN FUNCTION DESCRIPTION (R A... R B R7 A... R7 B ), Piel Port (TTL Compatible Inputs). 4 piel select inputs, with bits each for Red, (G A... G B G7 A... G7 B ), bits for Green and bits for Blue. Each bit is multipleed [A-B] 2: or :. It can be (B A... B B B7 A... B7 B ) configured for 24-Bit True-Color Data, -Bit Pseudo-Color Data and 5-Bit True-Color Data formats. Piel Data is latched into the device on the rising edge of LOADIN. PS A... PS B, PS A... PS B Palette Priority Selects (TTL Compatible Inputs): These piel port select inputs determine whether or not the device s piel data port is selected on a piel by piel basis. The palette selects allow switching between multiple palette devices. The device can be preprogrammed to completely shut off the DAC analog outputs. If the values of PS and PS match the values programmed into bits MR6 and MR7 of the Mode Register, then the device is selected. Each bit is multipleed [A-B] 2: or :. PS and PS are latched into the device on the rising edge of LOADIN. LOADIN Piel Data Load Input (TTL Compatible Input). This input latches the multipleed piel data, including PS PS, BLANK and SYNC into the device. LOAD Piel Data Load Output (TTL Compatible Output). This output control signal runs at a divided down frequency of the piel CLOCK input. Its frequency is a function of the multiple rate. It can be used to directly or indirectly drive LOADIN f LOAD = f CLOCK /M where (M = for : Multiple Mode) where (M = 2 for 2: Multiple Mode). PRGCK Programmable Clock Output (TTL Compatible Output). This output control signal runs at a divided down frequency of the piel CLOCK input. Its frequency is user programmable and is determined by bits CR3 and CR3 of Command Register 3 f PRGCK = f CLOCK /N where N = 4,, 6 and 32. SCKIN Video Shift Clock Input (TTL Compatible Input). The signal on this input is internally gated synchronously with the BLANK signal. The resultant output, SCK, is a video clocking signal that is stopped during video blanking periods. SCK Video Shift Clock Output (TTL Compatible Output). This output is a synchronously gated version of SCKIN and BLANK. SCK, is a video clocking signal that is stopped during video blanking periods. CLOCK, CLOCK Clock Inputs (ECL Compatible Inputs). These differential clock inputs are designed to be driven by ECL logic levels configured for single supply (+5 V) operation. The clock rate is normally the piel clock rate of the system. BLANK Composite Blank (TTL Compatible Input). This video control signal drives the analog outputs to the blanking level. SYNC Composite-Sync Input (TTL Compatible Input). This video control signal drives the IOG analog output to the SYNC level. It is only asserted during the blanking period. CR22 in Command Register 2 must be set if SYNC is to be decoded onto the analog output, otherwise the SYNC input is ignored. SYNC D D9 CE Composite SYNC O/P (TTL Compatible Output). This video output is a delayed version of SYNC. The delay corresponds to the number of pipeline stages of the device. Databus (TTL Compatible Input/Output Bus). Data, including color palette values and device control information is written to and read from the device over this -bit, bidirectional databus. -bit data or -bit data can be used. The databus can be configured for either -bit parallel data or byte data (+2) as well as standard -bit data. Any unused bits of the databus should be terminated through a resistor to either he digital power plane (V CC ) or GND. Chip Enable (TTL Compatible Input). This input must be at Logic when writing to or reading from the device over the databus (D D9). Internally, data is latched on the rising edge of CE.

9 Mnemonic Function R/W Read/Write Control (TTL Compatible Input). This input determines whether data is written to or read from the device s registers and color palette RAM. R/W and CE must be at Logic to write data to the part. R/W must be at Logic and CE at Logic to read from the device. C, C Command Controls (TTL Compatible Inputs). These inputs determine the type of read or write operation being performed on the device over the databus (see Interface Truth Table). Data on these inputs is latched on the falling edge of CE. IOR; IOR, IOG; IOG, IOB; Red, Green and Blue Current Outputs (High Impedance Current Sources). These RGB IOB video outputs are specified to directly drive RS-343A and RS-7 video levels into doubly terminated 75 Ω loads. IOR, IOG and IOB are the complementary outputs of IOR, IOG and IOB. These outputs can be tied to GND if it is not required to use differential outputs. V REF Voltage Reference Input (Analog Input). An eternal.235 V voltage reference is required to drive this input. An AD59 (2-terminal voltage reference) or equivalent is recommended. (Note: It is not recommended to use a resistor network to generate the voltage reference.) R SET Output Full-Scale Adjust Control (Analog Input). A resistor connected between this pin and analog ground controls the absolute amplitude of the output video signal. The value of R SET is derived from the full-scale output current on IOG according to the following equations: R SET (Ω) = C R REF /IOG (ma); SYNC on R SET (Ω) = C2 R REF /IOG (ma); No SYNC on. Full-Scale output currents on IOR and IOB for a particular value of R SET are given by: IOR (ma)= C2 R REF (V)/R SET (Ω) and IOB (ma) = C2 R REF (V)/R SET (Ω) where C = 6,5: PEDESTAL = 7.5 IRE where C = 5,723: PEDESTAL = IRE and where C2 = 4,323: PEDESTAL = 7.5 IRE where C = 3,996: PEDESTAL = IRE. COMP Compensation Pin. A. µf capacitor should be connected between this pin and V AA. I PLL Phase Lock Loop Output Current (High Impedance Current Source). This output is used to enable multiple ADV75/s along with ADV75s to be synchronized together with subpiel resolution when using an eternal PLL. This output is triggered either from the falling edge of SYNC or BLANK as determined by bit CR2 of Command Register 2. When activated, it supplies a current corresponding to I PLL (ma) =,72 R REF (V)/R SET (Ω) When not using the I PLL function, this output pin should be tied to GND. V AA Power Supply (+5 V ± 5%). The part contains multiple power supply pins, all should be connected together to one common +5 V filtered analog power supply. GND Analog Ground. The part contains multiple ground pins, all should be connected together to the system s ground plane. 9

10 (Continued from page ) applications. The part is controlled and programmed through the microprocessor (MPU) port. The part also contains a number of onboard test registers, associated with self diagnostic testing of the device. The individual Red, Green and Blue piel input ports allow True-Color, image rendition. True-Color image rendition, at speeds of up to 22 MHz, is achieved through the use of the onboard data multipleer/serializer. The piel input ports fleibility allows for direct interface to most standard frame buffer memory configurations. The 3 bits of resolution, associated with the color look-up table and triple -bit DAC, realizes 24-bit True-Color resolution, while also allowing for the onboard implementation of linearization algorithms, such as Gamma-Correction. This allows effective 3-bit True-Color operation. The on-chip video clock controller circuit generates all the internal clocking and some additional eternal clocking signals. An eternal ECL oscillator source with differential outputs is all that is required to drive the CLOCK and CLOCK inputs of the. The part can also be driven by an eternal clock generator chip circuit, such as the AD73. The is capable of generating RGB video output signals which are compatible with RS-343A and RS-7 video standards, without requiring eternal buffering. Test diagnostic circuitry has been included to complement the users system level debugging. The is fabricated in a +5 V CMOS process. Its monolithic CMOS construction ensures greater functionality with low power dissipation. The is packaged in a plastic -pin power quad flatpack (QFP). Superior thermal dissipation is achieved by inclusion of a copper heatslug, within the standard package outline to which the die is attached. CIRCUIT DETAILS AND OPERATION OVERVIEW Digital video or piel data is latched into the over the devices Piel Port. This data acts as a pointer to the onboard Color Palette RAM. The data at the RAM address pointed to is latched into the digital-to-analog converters (DACs) and output as an RGB analog video signal. For the purposes of clarity of description, the is broken down into three separate functional blocks. These are:. Piel port and clock control circuit 2. MPU port, registers and color palette 3. Digital-to-analog converters and video outputs Table I shows the architectural and packaging differences between other devices in the ADV75 series of workstation parts. (For more details consult the relevant data sheets.) Table I. Architectural and Packaging Differences of the ADV75 Series Description ADV75* ADV75* 24-Bit Gamma True Color 24-Bit Standard True Color -Bit Gamma Pseudo Color -Bit Standard Pseudo Color 5-Bit True Color 22 MHz True Color 22 MHz Pseudo Color Triple -Bit DACs 4: Multipleing 2: Multipleing : Multipleing 6-Lead QFP -Lead QFP *See ADV75 and ADV75 data sheets for more information on these parts. Piel Port and Clock Control Circuit The Piel Port of the is directly interfaced to the video/graphics pipeline of a computer graphics subsystem. It is connected directly or through a gate array to the video RAM of the systems Frame-Buffer (video memory). The piel port on the device consists of: Color Data,, Piel Controls SYNC, BLANK Palette Selects PS PS The associated clocking signals for the piel port include: Clock Inputs CLOCK, CLOCK, LOADIN, SCKIN Clock Outputs LOAD, PRGCK, SCK These onboard clock control signals are included to simplify interfacing between the part and the frame buffer. Only two control input signals are necessary to get the part operational, CLOCK and CLOCK (ECL Levels). No additional signals or eternal glue logic are required to get the Piel Port & Clock Control Circuit of the part operational. Piel Port (Color Data) The has 4 color data inputs. The part has two (for 2: multipleing) 24-bit wide direct color data inputs. These are user programmed to support a number of color data formats including 24-Bit True Color, 5-Bit True Color and -Bit Pseudo Color (see Color Data Formats section) in 2: and : multiple modes. A B MULTIPLEXER 24 Figure. Multipleed Color Inputs for the

11 Color data is latched into the parts piel port on every rising edge of LOADIN (see Timing Waveform, Figure 3). The required frequency of LOADIN is determined by the multiple rate, where f LOADIN = f CLOCK /2 2: Multiple Mode f LOADIN = f CLOCK : Multiple Mode Other piel data signals latched into the device by LOADIN include SYNC, BLANK and PS PS. Internally, data is pipelined through the part by the differential piel clock inputs, CLOCK and CLOCK. The LOADIN control signal needs only have a frequency synchronous relationship to the piel CLOCK (see Pipeline Delay & Onboard Calibration section). A completely phase independent LOADIN signal can be used with the, allowing the CLOCK to occur anywhere during the LOADIN cycle. Alternatively, the LOAD signal of the can be used. LOAD can be connected either directly or indirectly to LOADIN. Its frequency is automatically set to the correct LOADIN requirement. SYNC, BLANK The BLANK and SYNC video control signals drive the analog outputs to the blanking and SYNC levels respectively. These signals are latched into the part on the rising edge of LOADIN. The SYNC information is encoded onto the IOG analog signal when bit CR22 of Command Register 2 is set to a Logic. The SYNC input is ignored if CR22 is set to. SYNC In some applications where it is not permissible to encode SYNC on green (IOG), SYNC can be used as a separate TTL digital SYNC output. This has the advantage over an independent (of the ADV75) SYNC in that it does not necessitate knowing the absolute pipeline delay of the part. This allows complete independence between LOADIN/Piel Data and CLOCK. The SYNC input is connected to the device as normal with Bit CR22 of Command Register 2 set to thereby preventing SYNC from being encoded onto IOG. Bit CR2 of Command Register is set to, enabling SYNC. The output signal generates a TTL SYNC with correct pipeline delay that is capable of directly driving the composite SYNC signal of a computer monitor. PS PS (Palette Priority Select Inputs) These piel port select inputs determine whether or not the device is selected. These controls effectively determine whether the devices RGB analog outputs are turned-on or shut down. When the analog outputs are shut down, IOR, IOG and IOB are forced to ma regardless of the state of the piel and control data inputs. This state is determined on a piel by piel basis as the PS PS inputs are multipleed in eactly the same format as the piel port color data. These controls allow for switching between multiple palette devices (see Appendi 4). If the values of PS and PSI match the values programmed into bits MR6 and MR7 of the Mode Register, then the device is selected, if there is no match the device is effectively shut down. Multipleing The onboard multipleers of the eliminate the need for eternal data serializer circuits. Multiple video memory devices can be connected, in parallel, directly to the device. Figure shows two memory banks of 5 MHz memory connected to the, running in 2: multiple mode, giving a resultant piel or dot clock rate of MHz. As mentioned in the previous section, the supports a number of color data formats in 2: and : multiple modes. In : multiple mode, the is clocked using the LOADIN signal. This means that there is no requirement for differential ECL inputs on CLOCK and CLOCK. The piel clock is connected directly to LOADIN. (Note: The ECL CLOCK can still be used to generate LOAD PRGCK, etc.) VRAM (BANK A) VRAM (BANK B) VIDEO MEMORY/ FRAME BUFFER 5MHz 5MHz A MULTIPLEXER 24 B MHz (2 5MHz) Figure. Direct Interfacing of Video Memory to CLOCK CONTROL CIRCUIT The has an integrated Clock Control Circuit (Figure 2). This circuit is capable of both generating the s internal clocking signals as well as eternal graphics subsystem clocking signals. Total system synchronization can be attained by using the parts output clocking signals to drive the controlling graphics processor s master clock as well as the video frame buffers shift clock signals. CLOCK, CLOCK Inputs The Clock Control Circuit is driven by the piel clock inputs, CLOCK and CLOCK. These inputs can be driven by a differential ECL oscillator running from a +5 V supply. CLOCK CLOCK PRGCK LOAD SCK BLANK SYNC SCKIN LOADIN ECL TO TTL DIVIDE BY N ( N) TO COLOR DATA MULTIPLEXER M IS A FUNCTION OF MULTIPLEX RATE M = 2 IN 2: MULTIPLEX MODE M = IN : MULTIPLEX MODE LATCH ENABLE DIVIDE BY M ( M) N IS INDEPENDENTLY PROGRAMMABLE N= (4,, 6, 32) Figure 2. Clock Control Circuit of the

12 Alternatively, the CLOCK inputs can be driven by a Programmable Clock Generator (Figure 3), such as the ICS562. The ICS562 is a monolithic, phase-locked-loop, clock generator chip. It is capable of synthesizing differential ECL output frequencies in a range up to 22 MHz from a single low frequency reference crystal. LOW FREQUENCY OSCILLATOR V CLOCK +5V D D3 GND ECL + ECL CLOCK GENERATOR V REF CS R/W GND V CC GND 22Ω 33Ω V CC GND 22Ω 33Ω. µf V AA V AA +5V CLOCK CLOCK V REF GND Figure 3. PLL Generator Driving CLOCK, CLOCK of the CLOCK CONTROL SIGNALS LOAD The generates a LOAD control signal which runs at a divided down frequency of the piel CLOCK. The frequency is automatically set to the programmed multiple rate, controlled by CR36 of Command Register 3. f LOAD = f CLOCK /2 2: Multiple Mode f LOAD = f CLOCK : Multiple Mode The LOAD signal is used to directly drive the LOADIN piel latch signal of the. This is most simply achieved by tying the LOAD and LOADIN pins together. Alternatively, the LOAD signal can be used to drive the frame buffer s shift clock signals, returning to the LOADIN input delayed with respect to LOAD. VIDEO FRAME BUFFER LOAD LOAD LOADIN PIXEL DATA VIDEO FRAME BUFFER LOAD() LOAD() LOAD(2) LOAD LOADIN PIXEL DATA If it is not necessary to have a known fied number of pipeline delays, then there is no limitation on the delay between LOAD- and LOADIN (LOAD() and LOAD(2)). LOADIN and Piel Data must conform to the setup and hold times (t and t 9 ). If however, it is required that the has a fied number of pipeline delays (t PD ), LOAD and LOADIN must conform to timing specifications t and τ-t as illustrated in Figures 4 and 5. PRGCK The PRGCK control signal outputs a user programmable clock frequency. It is a divided down frequency of the piel CLOCK (see Figure ). The rising edge of PRGCK is synchronous to the rising edge of LOAD f PRGCK = f CLOCK /N where N = 4,, 6 or 32. One application of the PRGCK is to use it as the master clock frequency of the graphics subsystems processor or controller. SCKIN, SCK These video memory signals are used to minimize eternal support chips. Figure 5 illustrates the function that is provided. An input signal applied to SCKIN is synchronously AND-ed with the video blanking signal (BLANK). The resulting signal is output on SCK. Figure 7 of the Timing Waveform section shows the relationship between SCK, SCKIN and BLANK. SCK BLANK SYNC SCKIN LATCH ENABLE Figure 5. SCK Generation Circuit The SCK signal is essentially the video memory shift control signal. It is stopped during the screen retrace. Figure 6 shows a suggested frame buffer to interface. This is a minimum chip solution and allows the control the overall graphics system clocking and synchronization. VIDEO FRAME BUFFER LOAD LOADIN SCKIN BLANK SCK LOADIN LOAD(2) DELAY PIXEL DATA Figure 4. LOAD vs. Piel Clock Input (CLOCK, CLOCK) Figure 6. Interface Using SCKIN and SCK 2

13 Pipeline Delay and On-Board Calibration The has a fied number of pipeline delays (t PD ), so long as timings t and τ-t are met. However, if a fied pipeline delay is not a requirement, timings t and τ-t can be ignored, a calibration cycle must be run and there is no restriction on LOADIN to LOAD timing. If timings t and τ-t are not met, the part will function correctly though with an increased number of pipeline delays, t PD + N CLOCKS (for 2: mode N = 2, for : mode N = ). The has onboard calibration circuitry which synchronizes piel data and LOADIN with the internal clocking signals. Calibration can be performed in two ways: during the devices initialization sequence by toggling two bits of the Mode Register, MR followed by MR5, or by writing a to Bit CR of Command Register which eecutes a calibration on every Vertical Sync. COLOR VIDEO MODES The supports a number of color video modes all at the maimum video rate. Command bits CR24 CR27 of Command Register 2 along with Bit MR of Mode Register determine the color mode. 24-Bit Gamma True Color (CR25, CR26, CR27 =,, and MR = ) The part is set to 24-bit/3-bit True-Color operation. The piel port accepts 24 bits of color data which is directly mapped to the Look-Up Table RAM. The Look-Up Table is configured as a 256 location by 3 bits deep RAM ( bits each for Red, Green and Blue). The output of the RAM drives the DACs with 3-bit data ( bits each for Red, Green and Blue). The RAM is preloaded with a user determined, nonlinear function, such as a gamma correction curve. 24-BIT PIXEL DATA 24-BIT TO 24-BIT LOOK-UP-TABLE BIT COLOR DATA -BIT DAC -BIT DAC -BIT DAC ANALOG VIDEO PUTS Figure. 24-Bit to 24-Bit Direct True-Color Configuration -Bit Gamma Pseudo Color (CR25, CR26, CR27 = X,, or X,, or X,, and MR = ) This mode sets the part into -bit Pseudo-Color operation. The piel port accepts bits of piel data which indees a 3-bit word in the Look-Up Table RAM. The Look-Up Table is configured as a 256 location by 3 bits deep RAM ( bits each for Red, Green and Blue). The output of the RAM drives the DACs with 3-bit data ( bits each for Red, Green and Blue). -BIT PIXEL DATA -BIT TO 3-BIT LOOK-UP-TABLE BIT COLOR DATA -BIT DAC -BIT DAC -BIT DAC ANALOG VIDEO PUTS 24-BIT PIXEL DATA 24-BIT TO 3-BIT LOOK-UP-TABLE BIT COLOR DATA -BIT DAC -BIT DAC -BIT DAC ANALOG VIDEO PUTS Figure Bit to 3-Bit True-Color Configuration This mode allows for the display of full 24-bit, Gamma- Corrected True-Color Images. 24-Bit Standard True Color (CR25, CR26, CR27 =,, and MR = ) This mode sets the part into direct 24-bit True-Color operation. The piel port accepts 24 bits of color data which is directly mapped to Look-Up Table RAM. The Look-Up Table is configured as a 256 location by 24 bits deep RAM ( bits each for Red, Green and Blue) and essentially acts as a bypass RAM. The output of the RAM drives the DACs with 24-bit data ( bits each for Red, Green and Blue). The RAM is preloaded with a linear function. This mode allows for the display of full 24-bit True-Color Images. Figure 9. -Bit to 3-Bit Pseudo-Color Configuration This mode allows for the display of 256 simultaneous colors out of a total palette of millions of addressable colors. -Bit Standard Pseudo Color (CR25, CR26, CR27 = X,, or X,, or X,, and MR = ) This mode sets the part into -bit Pseudo-Color operation. The piel port accepts bits of piel data which indees a 24-bit word in the Look-Up Table RAM. The Look-Up Table is configured as a 256 location by 24 bits deep RAM ( bits each for Red, Green and Blue). The output of the RAM drives the DACs with 24-bit data ( bits each for Red, Green and Blue). -BIT PIXEL DATA -BIT TO 24-BIT LOOK-UP-TABLE BIT COLOR DATA -BIT DAC -BIT DAC -BIT DAC ANALOG VIDEO PUTS Figure 2. -Bit to 24-Bit Pseudo-Color Configuration 3

14 This mode allows for the display of 256 simultaneous colors out of a total palette of millions of addressable colors. 5-Bit Gamma True Color (CR24, CR25, CR26, CR27 =,,, or,,, and MR = ) The part is set to 5-bit True-Color operation. The piel port accepts 5 bits of color data which is mapped to the 5 LSBs of each of the red, green and blue palettes of the Look-Up Table RAM. The Look-Up Table is configured as a 32 location by 3 bits deep RAM ( bits each for Red, Green and Blue). The output of the RAM drives the DACs with 3-bit data ( bits each for Red, Green and Blue). 5-BIT PIXEL DATA BIT TO 3-BIT LOOK-UP-TABLE BIT COLOR DATA -BIT DAC -BIT DAC -BIT DAC ANALOG VIDEO PUTS Figure 2. 5-Bit to 3-Bit True-Color Configuration This mode allows for the display of 5-bit, Gamma-Corrected True-Color Images. 5-Bit Standard True Color (CR24, CR25, CR26, CR27 =,,, or,,, and MR = ) The part is set to 5-bit True-Color operation. The piel port accepts 5 bits of color data which is mapped to the 5 LSBs of each of the red, green and blue palettes of the Look-Up Table RAM. The Look-Up Table is configured as a 32 location by 24 bits deep RAM ( bits each for Red, Green and Blue). The output of the RAM drives the DACs with 24-bit data ( bits each for Red, Green and Blue). 5-BIT PIXEL DATA BIT TO 24-BIT LOOK-UP TABLE BIT COLOR DATA -BIT DAC -BIT DAC -BIT DAC ANALOG VIDEO PUTS Figure Bit to 24-Bit True-Color Configuration This mode allows for the display of 5-bit True-Color Images. PIXEL PORT MAPPING The piel data to the is automatically mapped in the parts piel port as determined by the piel data mode programmed (Bits CR24 CR27 of Command Register 2). Piel data in the 24-bit True-Color modes is directly mapped to the 24 color inputs R R7, G G7 and B B7. R4 R3 R2 R R G4 G3 G2 G G B4 B3 B2 B B PIXEL INPUT DATA R7 R6 R5 R4 R3 R2 R R G7 G6 G5 G4 G3 G2 G G B7 B6 B5 B4 B3 B2 B B PIN ASSIGN- MENTS R4 R3 R2 R R B4 B3 B2 B B DATA LATCHED TO PIXEL PORT R4 R3 R2 R R G4 G3 G2 G G B4 B3 B2 B B DATA INTERNALLY SHIFTED TO 5 LSBS 256 RAM ( LUT) G4 G3 G2 G G LOCATION "3" LOCATION "" 256 RAM ( LUT) LOCATION "3" LOCATION "" 256 RAM ( LUT) LOCATION "3" LOCATION "" DATA LATCHES FIRST 32 LOCATIONS OF RAM TO DAC TO DAC TO DAC Figure Bit True-Color Mapping Using R3 R7, G3 G7 and B3 B7 There are three modes of operation for -bit Pseudo Color. Each mode maps the input piel data differently. Data can be input one of the three color channels, R R7 or G G7 or B B7. The part has two modes of operation for 5-bit True Color. In the first mode, data is input to the device over the red, green and blue channel (R3 R7, G3 G7 and B3 B7) and is internally mapped to locations to 3 of the Look-Up Table (LUT) according to Figure 23. In the second mode, data is input to the device over just two of the color ports, red and green (R R7 and G G6) and is internally mapped to LUT locations to 3 according to Figure 24. (Note: Data on unused piel inputs is ignored.) 4

15 R4 R3 R2 R R G4 G3 G2 R7 R6 R5 R4 R3 R2 R R R4 R3 R2 R R G4 G3 G2 R4 R3 R2 R R RAM ( LUT) LOCATION "3" LOCATION "" TO DAC Table II. Databus Width Table Databus RAM/DAC Read/Write Width Resolution Mode Bit Bit -Bit Parallel Bit Bit -Bit Parallel Bit Bit +2 Byte Bit Bit -Bit Parallel G G B4 B3 B2 B B PIXEL INPUT DATA G7 G6 G5 G4 G3 G2 G G B7 B6 B5 B4 B3 B2 B B PIN ASSIGN- MENTS G G B4 B3 B2 B B DATA LATCHED TO PIXEL PORT G4 G3 G2 G G RAM ( LUT) B4 B3 5 LOCATION "3" B2 B TO B LOCATION "" DAC DATA INTERNALLY SHIFTED TO 5 LSBS 256 RAM ( LUT) LOCATION "3" LOCATION "" DATA LATCHES FIRST 32 LOCATIONS OF RAM TO DAC Figure Bit True-Color Mapping Using R R7 and G G6 MICROPROCESSOR (MPU) PORT The supports a standard MPU Interface. All the functions of the part are controlled via this MPU port. Direct access is gained to the Address Register, Mode Register and all the Control Registers as well as the Color Palette. The following sections describe the setup for reading and writing to all of the devices registers. MPU Interface The MPU interface (Figure 25) consists of a bidirectional, -bit wide databus and interface control signals CE, C, C and R/W. The -bit wide databus is user configurable as illustrated. Register Mapping The contains a number of onboard registers including the Mode Register (MR7 MR), Address Register (A7 A) and nine Control Registers as well as Red (R9 R), Green (G9 G) and Blue (B9 B) Color Registers. These registers control the entire operation of the part. Figure 26 shows the internal register configuration. Control lines C and C determine which register the MPU is accessing. C and C also determine whether the Address Register is pointing to the color registers and look-up table RAM or the control registers. If C, C =,, the MPU has access to whatever control register is pointed to by the Address Register (A7 A). If C, C =,, the MPU has access to the Look-Up Table RAM (Color Palette) through the associated color registers. The CE input latches data to or from the part. The R/W control input determines between read or write accesses. The Truth Tables III and IV show all modes of access to the various registers and color palette for both the -bit wide databus configuration and -bit wide databus configuration. It should be noted that after power-up, the devices MPU port is automatically set to -bit wide operation (see Power-On Reset section). Color Palette Accesses Data is written to the color palette by first writing to the address register of the color palette location to be modified. The MPU performs three successive write cycles for each of the red, green and blue registers ( bit or bit). An internal pointer moves from red to green to blue after each write is completed. This pointer is reset to red after a blue write or whenever the address register is written. During the blue write cycle, the three bytes of red, green and blue are concatenated into a single 3-bit/24-bit word and written to the RAM location as specified in the address register (A7 A). The address register then automatically increments to point to the net RAM location and a similar red, green and blue palette write sequence is performed. The address register resets to H following a blue write cycle to color palette RAM location FFH. CONTROL S ADDRESS ADDR (A7 A) MODE (MR) PIXEL MASK TEST S ID COMMAND S (CR CR3) REVISION DATA TO PALETTES 3 COLOR S MPU PORT (+2) CE R/W C C D D9 Figure 25. MPU Port and Register Configuration 5

16 Data is read from the color palette by first writing to the address register of the color palette location to be read. The MPU performs three successive read cycles from each of the red, green and blue locations (-bit or -bit) of the RAM. An internal pointer moves from red to green to blue after each read is completed. This pointer is reset to red after a blue read or whenever the address register is written. The address register then automatically increments to point to the net RAM location, and a similar red, green and blue palette read sequence is performed. The address register resets to H following a blue read cycle of color palette RAM location FFH. Register Accesses The MPU can write to or read from all of the s registers. C and C determine whether the Mode Register or Address Register is being accessed. Access to these registers is direct. The Control Registers are accessed indirectly. The Address Register must point to the desired Control Register. Figure 2 along with the -bit and -bit Interface Truth Tables illustrate the structure and protocol for device communication over the MPU port. C = C = ADDRESS CONTROL S (A7 A) H PIXEL TEST R G B H DAC TEST R G B 2H SYNC, BLANK & I PLL TEST 3H ID (READ ONLY) 4H PIXEL MASK 5H COMMAND 6H COMMAND 2 7H COMMAND 3 H RESERVED* (READ ONLY) 9H RESERVED* (READ ONLY) AH RESERVED* (READ ONLY) BH REVISION * THIS IS READ ONLY. MODE (MR7 MR) ADDRESS (A7 A) C = C = C = C = POINTS TO LOCATION CORRESPONDING TO ADDRESS REG (A7 A) (R9 R) C = C = (G9 G) LOOK-UP TABLE RAM (256 3) Figure 26. Internal Register Configuration and Address Decoding (B9 B) ADDRESS REG = ADDRESS REG + Table III. Interface Truth Table (-Bit Databus Mode) R/W C C Databus (D9 D) Operation Result DB7 DB Write to Mode Register DB7 DB MR7 MR DB7 DB Write to Address Register DB7 DB A7 A DB7 DB Write to Control Registers DB7 DB Control Register (Particular Control Register Determined by Address Register) DB9 DB Write to Register DB9 DB R9 R DB9 DB Write to Register DB9 DB G9 G DB9 DB Write to Register DB9 DB B9 B Write RGB Data to RAM Location Pointed to by Address Register (A7 A) Address Register = Address Register + DB7 DB Read Mode Register MR7 MR DB7 DB DB7 DB Read Address Register A7 A DB7 DB DB7 DB Read Control Registers Register Data DB7 DB (Particular Control Register Determined by Address Register) DB9 DB Read RAM Location R9 R DB9 DB DB9 DB Read RAM Location G9 G DB9 DB DB9 DB Read RAM Location B9 B DB9 DB (RAM Location Pointed to by Address Reg (A7 A)) Address Register = Address Register + DB = Data Bit. 6

17 Table IV. Interface Truth Table (-Bit Databus Mode)* Databus R/W C C (D9 D) Operation Result DB7 DB Write to Mode Register DB7 DB MR7 MR DB7 DB Write to Address Register DB7 DB A7 A DB7 DB Write to Control Registers DB7 DB Control Registers (Particular Control Register Determined by Address Register (A7 A)) DB9 DB2 Write to Register DB9 DB2 R9 R2 DB DB Write to Register DB DB R R DB9 DB2 Write to Register DB9 DB2 G9 G2 DB DB Write to Register DB DB G G DB9 DB2 Write to Register DB9 DB2 B9 B2 DB DB Write to Register DB DB B B Write RGB Data to RAM Location Pointed to by Address Register (A7-A) Address Register = Address Register + DB7 DB Read Mode Register MR7 MR DB7 DB DB7 DB Read Address Register A7 A DB7 DB DB7 DB Read Control Registers Register Data DB7 DB (Particular Control Register Determined by Address Register) DB9 DB2 Read RAM Location R9 R2 DB9 DB2 DB DB Read RAM Location R R DB DB DB9 DB2 Read RAM Location G9 G2 DB9 DB2 DB DB Read RAM Location G G DB DB DB9 DB2 Read RAM Location B9 B2 DB9 DB2 DB DB Read RAM Location B B DB DB (RAM Location Pointed to by Address Register (A7 A)) Address Register = Address Register + *Writing or reading -bit data (DB9 DB) over an -bit databus (D7 D) requires two write or two read cycles. :DB9 DB2 is mapped to D7 D on the first cycle. :DB DB is mapped to D D on the second cycle. DB = Data Bit. Power-On Reset On power-up of the eecutes a power-on reset operation. This initializes the piel port such that the piel sequence AB starts at A. The Mode Register (MR7 MR), Command Register 2 (CR27 CR2) and Command Register 3 (CR37 CR3) have all bits set to a Logic. Command Register (CR7 CR) has all bits set to a Logic. The output clocking signals are also set during this reset period. PRGCK = CLOCK/32 LOAD = CLOCK/2 The power-on reset is activated when V AA goes from V to 5 V. This reset is active for µs. The should not be accessed during this reset period. The piel clock should be applied at power-up. 7

18 PROGRAMMING The following section describes each register, including Address Register, Mode Register and each of the nine Control Registers in terms of its configuration. Address Register (A7 A) As illustrated in the previous tables, the C and C control inputs, in conjunction with this address register specify which control register, or color palette location is accessed by the MPU port. The address register is -bits wide and can be read from as well as written to. When writing to or reading from the color palette on a sequential basis, only the start address needs to be written. After a red, green and blue write sequence, the address register is automatically incremented. MODE MR (MR9 MR) The mode register is a -bit wide register. However for programming purposes, it may be considered as an -bit wide register (MR and MR9 are both reserved). It is denoted as MR7 MR for simplification purposes. The diagram shows the various operations under the control of the mode register. This register can be read from as well written to. In read mode, if MR and MR9 are read back, they are both returned as zeros. MODE (MR7 MR) BIT DESCRIPTION Reset Control (MR) This bit is used to reset the piel port sampling sequence. This ensures that the piel sequence AB starts at A. It is reset by writing a followed by a followed by a. This bit must be run through this cycle during the initialization sequence. RAM-DAC Resolution Control (MR) When this is programmed with a, the RAM is 3 bits deep ( bits each for red, green and blue) and each of the three DACs is configured for -bit resolution. When MR is programmed with a, the RAM is 24 bits deep ( bits each for red, green and blue) and the DACs are configured for -bit resolution. The two LSBs of the -bit DACs are pulled down to zero in -bit RAM-DAC mode. MPU Databus Width (MR2) This bit determines the width of the MPU port. It is configured as either a -bit wide (D9 D) or -bit wide (D7 D) bus. -bit data can be written to the device when configured in -bit wide mode. The MSBs are first written on D7 D, then the two LSBs are written over D D. Bits D9 D are zeros in -bit mode. Operational Mode Control (MR4 MR3) When MR4 is and MR3 is, the part operates in normal mode. Calibrate LOADIN (MR5) This bit automatically calibrates the onboard LOADIN/ LOAD synchronization circuit. A to transition initiates calibration. This bit is set to in normal operation. See Pipeline Delay and Calibration section. This bit must be run through this cycle during the initialization sequence. Palette Select Match Bits Control (MR7 MR6) These bits allow multiple palette devices to work together. When bits PSI and PS match MR7 and MR6 respectively, the device is selected. If these bits do not match, the device is not selected and the analog video outputs drive ma, see Palette Priority Select Inputs section. Control Registers The has 9 control registers. To access each register, two write operations must be performed. The first write to the address register specifies which of the 9 registers is to be accessed. The second access determines the value written to that particular control register. Piel Test Register (Address Reg (A7 A) = H) This register is used when the device is in test/diagnostic mode. It is a 24-bit ( bits each for, and ) wide read-only register which allows the MPU to read data on the piel port, see Test Diagnostic section. MR9 MR MR7 MR6 MR5 MR4 MR3 MR2 MR MR RESERVED* PALETTE SELECT MATCH BITS CONTROL MR6 PS MR7 PS CALIBRATE LOADIN MR5 OPERATIONAL MODE CONTROL MR4 MR3 RESERVED NORMAL OPERATION RESERVED RESERVED * THESE BITS ARE READ-ONLY RESERVED BITS. A READ CYCLE WILL RETURN ZEROS "." MPU DATA BUS WIDTH MR2 -BIT (D7 D) -BIT (D9 D) RAM-DAC RESOLUTION CONTROL MR -BIT -BIT RESET CONTROL MR Mode Register (MR) (MR9 MR)