MANAGING POWER SYSTEM FAULTS. Xianyong Feng, PhD Center for Electromechanics The University of Texas at Austin November 14, 2017
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1 MANAGING POWER SYSTEM FAULTS Xianyong Feng, PhD Center for Electromechanics The University of Texas at Austin November 14, 2017
2 2 Outline 1. Overview 2. Methodology 3. Case Studies 4. Conclusion
3 3 Power System Fault Management Detection Real-time monitoring Detect electrical abnormal Fault type identification (permanent or temporary) Location Quickly and accurately locate fault Minimize system impact Isolation Open protective device Minimize load interruption Restoration Quick recovery Restore interrupted loads to normal
4 4 Power System Protection Research DC distribution system protection 1. Ultra-fast dc fault protection [1], [2] 2. Power converter fault current handling [3] 3. Meshed dc network short-circuit fault current analysis [4] Protection study for AC system with high penetration DERs 1. Intelligent sensor development 2. Fault type identification 3. Fault location 4. Islanding detection 5. Optimal sensor placement 1. X. Feng, et.al., "Fault inductance based protection for DC distribution systems, Proc. IET 13th Conference on Development of Power System Protection, March X. Feng, et.al., A novel fault location method for DC distribution protection, IEEE Trans. Industrial Applications, vol. 53, no. 3, pp , May-June, L. Qi, J. Pan, X. Huang, and X. Feng, Solid state fault current limiting for dc distribution protection, Proc. of Electric Ship Technology Symposium, Aug. 2017, pp X. Feng, et.al., Estimation of short circuit currents in mesh DC networks, Proc. IEEE PES General Meeting, July 2014.
5 5 CEM Approach - Protection Control Simulation Test: Power Hardware-in-the-Loop (PHIL) Simulation Test: New protection strategies are initially implemented in modeling software and verified in numerical environment Implement the interface between HIL simulator and real power systems Tools: 1. Matlab / Simulink 2. PSCAD 3. ETAP 4. OpenDSS Simulated control block 1 Simulated control block N Numerical simulation environment Control signal Measured signal The protection algorithms are implemented numerically The performance is evaluated and optimized offline Simulated circuit 1 Features: 1. Network model in simulator 2. Power converters and active sources serve as power interface 3. NI FPGA simulator enables the fast PE switching Real Hardware Microgrid System MV bus HIL simulator Controlled voltage source ~ Voltage signal Hardware Interface Current measurement I/Os Simulated network Power Amplifier Current signal Active Source 3 Control Hardware-in-the-Loop (CHIL) Simulation Test: Real Hardware Test and Field Demonstration: Protection strategies are implemented in hardware controllers The controller is validated in the HIL simulation environment Procedure: 1. Model the circuit 2. Implement control strategy in hardware 3. Configure the interface 4. Perform HIL tests Distributed control Advanced protection strategies Simulated switching devices in NI PXI simulator PXIe Real-Time/FPGA HIL System Sensors High speed communication link Control and Protection Hardware Control Center Simulated Distribution Network in Opal-RT Opal-RT Simulator I/O or other comm. Interfaces NI controllers Tertiary Controls SCADA System IED 2 The protection strategy test in real microgrid. Benefits: 1. Obtain validated engineering data 2. Demonstrate system performance in the real operation environment MW-scale Microgrid 4
6 6 DC Distribution System Protection DC protection challenges 1. No fault current zero-crossing 2. Lower line impedance 3. High di/dt 4. Power electrics device can not tolerate high fault current 5. Fast capacitor discharge DC fault current DC distribution system example DC Power Supply Fault 1 Fault 2 ~ = = = L Fault 3 L AC fault current L L
7 7 Fast DC Fault Location Algorithm Inductance-based dc fault location* 1. Estimate fault inductance with local measured v(t) and i(t) 2. Use estimated L to locate fault Line inductance distribution Equivalent inductance L 2 L 3 L 1 Distance + - v Equivalent fault circuit i R L RF DC UPS 380 VDC ~ = = = level 1 level 2 level 3 Fault 1 Fault 2 Zone 1 (20 m) Zone 2 (65 m) Zone 3 (10.2 m) L L L L L L Fault 3 Zone 4 (1.5 m) *X. Feng, et.al., A novel fault location method for dc distribution protection, IEEE Trans. Industrial Applications, vol. 53, no. 3, May-June, 2017.
8 8 Protection Control Prototype Protection strategy design 1. Online moving-window least square method 2. Algorithm on embedded controller Start Fault detected? Yes k = 0 No Go to next time interval Fault detection v i di/dt and location routine ADC ADC ADC k = k + 1 Read in measurements v(k), i(k), and di/dt(k) if k < M Yes v (1) i (1) di/dt (1) PRUs read data sequentially and store them in memory 7 analog inputs with A/D converters Yes di ( k M + 1) dt di A = ( k M + 2) dt! di ( k) dt No i( k M + 1) v ( k M + 1) i( k M + 2) v ( k M + 2 ) B =!! i( k) v ( k ) di (0) i(0) dt v(0) di = (1) i(1) v(1) A dt B =!!! di ( k) i( k) v( k ) dt Request new data once finishing the previous cycle Main program executes the fault detection and location routine PRUs 65 digital I/Os Processor (AM3358) if t < T max No L R + R F = T 1 T ( A A) A B if 0 < L < L th N Locate fault? Y Send tripping No Yes Send tripping signal End
9 9 Protection Algorithm Test Control-HIL test 1. Opal-RT simulator Simulated a 380 V dc system Convert v(t)/i(t) to analog Read in breaker status 2. Embedded controller Read in v(t)/i(t) signals Execute prot. algorithm Send a trip signal for internal fault Ethernet Opal-RT simulator Analog outputs: current/ voltage signal Microcontroller A/D converters Fault detection and location algorithm User interface Trip command 24 V 47uF Simulated DC network Breaker status wired back to Opal-RT simulator Breaker
10 10 Protection Algorithm Test Hardware test 1. Low voltage circuit 7.07 mf capacitor is charged to 12 V Inductors are used to emulate lines Short-circuit fault is created by closing a breaker 2. Embedded controller Read in v(t), i(t), di/dt Execute prot. algorithm Send a trip signal for internal fault + 12 V DC - Switch Capacitor (7.07 mf) Inductor (6 µh) Voltage Diagram Current Current sensor Analog circuit of di/dt calculation Test Circuit Line (6-12 µh) BeagleBone Black board with Tripping fault detection & signal location Emax
11 11 Protection Algorithm Test Results Control-HIL test results 1. L estimation error < 8.4% 2. Fault detection/location time < 0.7 ms current signal tripping signal current signal voltage signal
12 12 Protection Algorithm Improvement Level 1 Level 2 Level 3 No boundary inductor ΔL 1 ΔL 2 Zonal boundary inductors Equivalent inductance ΔL 3 Level 4 L 4 Equivalent inductance L 2 L 3 Inserted ΔL 3 L 3 L 1 Distance L 2 Inserted ΔL 2 level 1 level 2 level 3 L 1 Inserted ΔL 1 level 1 level 2 level 3 level 4 Distance DC UPS 380 VDC ~ = = = Fault 1 Fault 2 Zone 1 (20 m) Zone 2 (65 m) Zone 3 (10.2 m) L L L L L L Fault 3 Zone 4 (1.5 m)
13 13 Result Summary 1. The prot. method uses local measurements only to locate fault Detection and location time < 0.7 ms L estimation error in HIL test < 8.4% L estimation error in hardware test < 20% 2. The prot. Method accurately locates short-circuit faults if: Voltage measurement error < 0.5% Current measurement error < 1% 3. Boundary inductors improve prot. selectivity Ongoing work: 1. Protection algorithm test on real MV dc microgrid
14 14 MVDC Shipboard System Protection System Description 1. Two PGMs FCL in dc-dc converters 2. One propulsion load VFD + motor 3. One pulse load High di/dt 4. DC circuit breakers Isolate fault 5. Protection strategy* FCL + diff. protection 1.1 kv 2 MW 200 Hz M PMM PROPULSON LOAD PGM 850 V 0.8 MW 60 Hz 3-ph PGM 850 V 1.2 MW 60 Hz 3-ph PCM PFN Railgun MISSION LOAD 1.15 kvdc/ 1.0 kvdc PCM1-A = = = = 60 Hz Loads IPNC 1.15 kvdc 60 Hz AC Distribution 400 Hz Loads 60 Hz Loads 1.15 kvdc 60 Hz Loads 60 Hz AC Distribution IPNC = = = = 1.15 kvdc/ 1.0 kvdc PCM1-A 400 Hz Loads *S. Strank, et. al., Experimental test bed to de-risk the navy advanced development model, Proc. of Electric Ship Technology Symposium, Arlington, VA, Aug. 2017, pp
15 15 MVDC Shipboard System Protection Voltage (V) Main results 1. Fault: ms, 20 mω, on dc bus 2. Prot. strategy: FCL + diff. prot. Ongoing work 1. Validate the protection method on real dc microgrid Current (A) time (ms) time (ms) PGM V 60 Hz 3-Ph ac PGM V 60 Hz 3-Ph ac = = = = 5 mf Current differential: i 1 (t) + i 2 (t) 0.39 mh 0.39 mh Reactor mh 5 mf 0.5 mf Reactor mh 0.5 mf Diff. prot. zone CB1 Load MW 1 MW Load 2 CB2 i 1 (t) i 2 (t) 80 µh 9 mω 80 µh 9 mω Main dc bus 1150 V dc
16 16 AC Distribution System Protection Current (p.u.) Supported by DOE Fault type identification o Permanent or temporary Fault location Islanding detection Optimal sensor placement Permanent fault s 3 s 2 GPS signals s 4 s 1 Proposed intelligent sensors s 1 s 2 s 3 s 4 Legends fault intelligent sensor fuse Fault Fuse blow t Current (p.u.) Time (Seconds) Transient fault Time (Seconds) page 16
17 17 AC Distribution System Protection Impedance fault location 1. Requirement Network model Fault waveforms 2. Benefit Locate fault segment Do not need synch. Traveling wave method 1. Requirement GPS synchronization High bandwidth sensor Fast processing speed 2. Benefit Incipient fault location (subcycle fault) Simple algorithm
18 18 Conclusion 1. Fault management is critical for power system safety and reliability 2. Our dc prot. approach reduces fault clearing time and system recovery time 3. The fast prot. method significantly improves power system resilience
19 19 Thanks for your attention Contact information: Xianyong Feng, PhD Center for Electromechanics The University of Texas at Austin Phone:
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