CprE 281: Digital Logic
|
|
|
- Russell McKinney
- 5 years ago
- Views:
Transcription
1 CprE 281: igital Logic Instructor: Alexander Stoytchev
2 Registers CprE 281: igital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
3 Administrative Stuff Homework 8 is due next Monday. The second midterm exam is next Friday.
4 Midterm Exam #2 Administrative Stuff When: Friday October 4pm. Where: This classroom What: Chapters 1, 2, 3, 4 and The exam will be open book and open notes (you can bring up to 3 pages of handwritten notes).
5 Midterm 2: Format The exam will be out of 130 points You need 95 points to get an A for this exam It will be great if you can score more than 100 points. but you can t roll over your extra points L
6 Midterm 2: Topics Binary Numbers and Hexadecimal Numbers 1 s complement and 2 s complement representation Addition and subtraction of binary numbers Circuits for adders and fast adders Single and ouble precision IEEE floating point formats Converting a real number to the IEEE format Converting a floating point number to base 10 Multiplexers (circuits and function) Synthesis of logic functions using multiplexers Shannon s Expansion Theorem
7 Midterm 2: Topics ecoders (circuits and function) emultiplexers Encoders (binary and priority) Code Converters K-maps for 2, 3, and 4 variables Synthesis of logic circuits using adders, multiplexers, encoders, decoders, and basic logic gates Synthesis of logic circuits given constraints on the available building blocks that you can use Latches (circuits, behavior, timing diagrams) Flip-Flops (circuits, behavior, timing diagrams) Registers and Register Files
8 Review of Flip-Flops
9 A simple memory element with NOT Gates x x x
10 A simple memory element with NAN Gates x x x
11 A simple memory element with NOR Gates x x x
12 Basic Latch
13 A simple memory element with NOR Gates
14 A simple memory element with NOR Gates
15 A simple memory element with NOR Gates Set Reset
16 A memory element with NOR gates Reset Set [ Figure 5.3 from the textbook ]
17 Two ifferent Ways to raw the Same Circuit [ Figure 5.3 & 5.4 from the textbook ]
18 R S SR Latch: Circuit and Truth Table a b S R a b 0 0 0/1 1/ (no change) (Undesirable) (a) Circuit (b) Truth table [ Figure 5.4a,b from the textbook ] NOR Gate NOR Gate Truth table x 1 x 2 f
19 Gated SR Latch
20 Circuit iagram for the Gated SR Latch [ Figure 5.5a from the textbook ]
21 Circuit iagram for the Gated SR Latch This is the gate of the gated latch
22 Circuit iagram for the Gated SR Latch Notice that these are complements of each other
23 Gated SR Latch: Circuit iagram, Characteristic Table, and Graphical Symbol (Undesirable) [ Figure 5.5 from the textbook ]
24 Gated SR latch with NAN gates S Clk R [ Figure 5.6 from the textbook ]
25 Gated SR latch with NAN gates S Clk R In this case the gate is constructed using NAN gates! Not AN gates.
26 Gated SR latch with NAN gates S Clk R Also, notice that the positions of S and R are now swapped.
27 Gated SR latch with NAN gates S 1 S Clk = 1 R 1 R Finally, notice that when Clk=1 this turns into the basic latch with NAN gates, i.e., the SR Latch.
28 Gated SR latch with NOR gates Gated SR latch with NAN gates S Clk R
29 Gated SR latch with NOR gates Gated SR latch with NAN gates S Clk R Graphical symbols are the same
30 Gated SR latch with NOR gates (undesirable) Gated SR latch with NAN gates S Clk R (undesirable) Characteristic tables are the same
31 Gated Latch
32 Circuit iagram for the Gated Latch [ Figure 5.7a from the textbook ]
33 Gated Latch: Alternative esign Clk [
34 Gated Latch: Circuit iagram, Characteristic Table, and Graphical Symbol Note that it is now impossible to have S=R=1. When Clk=1 the output follows the input. When Clk=0 the output cannot be changed. [ Figure 5.7a,b from the textbook ]
35 Setup and hold times for Gated latch t su t h Clk Setup time (t su ) the minimum time that the signal must be stable prior to the the negative edge of the Clock signal Hold time (t h ) the minimum time that the signal must remain stable after the the negative edge of the Clock signal [ Figure 5.8 from the textbook ]
36 Master-Slave Flip-Flop
37 Constructing a Master-Slave Flip-Flop From Two Latches Master Slave
38 Constructing a Master-Slave Flip-Flop From Two Latches Master Slave
39 Constructing a Master-Slave Flip-Flop From Two Latches Master Slave
40 Constructing a Master-Slave Flip-Flop From Two Latches [ Figure 5.9a from the textbook ]
41 Constructing a Master-Slave Flip-Flop From one Latch and one Gated SR Latch (This version uses one less NOT gate) Master Slave
42 Constructing a Master-Slave Flip-Flop From one Latch and one Gated SR Latch (This version uses one less NOT gate) Master Slave
43 Edge-Triggered Flip-Flops
44 Master-Slave Flip-Flop Master Slave m s Clock Clk Clk (a) Circuit [ Figure 5.9a from the textbook ]
45 Negative-Edge-Triggered Master-Slave Flip-Flop Master Slave m s Clock Clk Clk Positive-Edge-Triggered Master-Slave Flip-Flop Master Slave m s Clock Clk Clk
46 Negative-Edge-Triggered Master-Slave Flip-Flop Master Slave m s Clock Clk Clk Positive-Edge-Triggered Master-Slave Flip-Flop Master Slave m s Clock Clk Clk
47 Negative-Edge-Triggered Master-Slave Flip-Flop Master Slave m s Clock Clk Clk Positive-Edge-Triggered Master-Slave Flip-Flop Master Slave m s Clock Clk Clk
48 T Flip-Flop
49 T Flip-Flop [ Figure 5.15a from the textbook ]
50 T Flip-Flop Positive-edge-triggered Flip-Flop [ Figure 5.15a from the textbook ]
51 T Flip-Flop What is this? [ Figure 5.15a from the textbook ]
52 What is this? T
53 What is this? T + =?
54 T Flip-Flop T 0 1 Clock
55 T Flip-Flop T 0 1 Clock Note that the two inputs to the multiplexer are inverses of each other.
56 Another Way to raw This T 0 1 Clock
57 Another Way to raw This T 0 1 Clock What is this?
58 What is this? T
59 What is this? T = T + T
60 It is an XOR T = + T
61 It is an XOR T = + T
62 What is this? + =?
63 T Flip-Flop T Clock
64 T Flip-Flop (circuit, truth table and graphical symbol) [ Figure 5.15a-c from the textbook ]
65 T Flip-Flop (How it Works) If T=0 then it stays in its current state If T=1 then it reverses its current state In other words the circuit toggles its state when T=1. This is why it is called T flip-flop.
66 JK Flip-Flop
67 JK Flip-Flop = J + K [ Figure 5.16a from the textbook ]
68 JK Flip-Flop J K Clock (a) Circuit J K ( t + 1) t ( ) 0 J t ( ) K (b) Truth table (c) Graphical symbol [ Figure 5.16 from the textbook ]
69 JK Flip-Flop (How it Works) A versatile circuit that can be used both as a SR flip-flop and as a T flip flop If J=0 and S =0 it stays in the same state Just like SR It can be set and reset J=S and K=R If J=K=1 then it behaves as a T flip-flop
70 Complete Wiring iagrams
71 Positive-Edge-Triggered Flip-Flop
72 Negative-Edge-Triggered Flip-Flop
73 The Complete Wiring iagram for a Positive-Edge-Triggered Flip-Flop Clock
74 The Complete Wiring iagram for a Negative-Edge-Triggered Flip-Flop Clock
75 The Complete Wiring iagram for a Negative-Edge-Triggered Flip-Flop Clock
76 Positive-Edge-Triggered T Flip-Flop T Clock
77 Negative-Edge-Triggered T Flip-Flop T Clock
78 The Complete Wiring iagram for a Positive-Edge-Triggered Flip-Flop T Clock
79 The Complete Wiring iagram for a Negative-Edge-Triggered Flip-Flop T Clock
80 Positive-Edge-Triggered JK Flip-Flop Clock J K
81 Negative-Edge-Triggered JK Flip-Flop Clock J K
82 The Complete Wiring iagram for a Positive-Edge-Triggered JK Flip-Flop J K Clock
83 The Complete Wiring iagram for a Negative-Edge-Triggered JK Flip-Flop J K Clock
84 Registers
85 Register (efinition) An n-bit structure consisting of flip-flops.
86 Parallel-Access Register
87 1-Bit Parallel-Access Register Load In 0 1 Out Clock
88 1-Bit Parallel-Access Register Load In 0 1 Out Clock The 2-to-1 multiplexer is used to select whether to load a new value into the flip-flop or to retain the old value. The output of this circuit is the output of the flip-flop.
89 1-Bit Parallel-Access Register Load 0 In 0 1 Out Clock If Load = 0, then retain the old value.
90 1-Bit Parallel-Access Register Load 1 In 0 1 Out Clock If Load = 1, then load the new value from In.
91 1-Bit Parallel-Access Register Load In 0 1 Out Clock If Load = 0, then retain the old value. If Load = 1, then load the new value from In.
92 2-Bit Parallel-Access Register Out_1 Out_0 Load Clock In_1 In_0
93 2-Bit Parallel-Access Register Parallel Output Out_1 Out_0 Load Clock In_1 In_0 Parallel Input
94 3-Bit Parallel-Access Register Out_2 Out_1 Out_0 Load Clock In_2 In_1 In_0 Notice that all flip-flops are on the same clock cycle.
95 3-Bit Parallel-Access Register Parallel Output Out_2 Out_1 Out_0 Load Clock In_2 In_1 In_0 Parallel Input
96 4-Bit Parallel-Access Register Out_3 Out_2 Out_1 Out_0 Load Clock In_3 In_2 In_1 In_0
97 4-Bit Parallel-Access Register Parallel Output Out_3 Out_2 Out_1 Out_0 Load Clock In_3 In_2 In_1 In_0 Parallel Input
98 4-Bit Parallel-Access Register Out_3 Out_2 Out_1 Out_0 Load Clock In_3 In_2 In_1 In_0
99 4-Bit Parallel-Access Register Out_3 Out_2 Out_1 Out_0 Load Clock In_3 In_2 In_1 In_0
100 4-Bit Parallel-Access Register Out_3 Out_2 Out_1 Out_0 Load Clock In_3 In_2 In_1 In_0
101 Shift Register
102 A simple shift register In Out Clock [ Figure 5.17a from the textbook ]
103 A simple shift register In Out Clock Positive-edge-triggered Flip-Flop
104 A simple shift register In Out Clock Master Slave m s Clock Clk Clk
105 A simple shift register In Out Clock Flip-Flop Master Slave m s Clock Clk Clk Gated -Latch Gated -Latch
106 A simple shift register In Out Clock
107 A simple shift register In Out Clock In Clock Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk
108 A simple shift register In Out Clock In Clock Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk
109 A simple shift register In Out Clock In Clock Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk
110 A simple shift register In Out Clock In Clock Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk
111 A simple shift register In Out Clock In Clock Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk
112 A simple shift register In Clock Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk
113 A simple shift register In Clock Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Clock
114 A simple shift register In Clock Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Clock
115 A simple shift register In Clock Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Clock
116 A simple shift register In Clock Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Clock
117 A simple shift register In Out Clock (a) Circuit t 0 In = Out t t t t t t t (b) A sample sequence [ Figure 5.17 from the textbook ]
118 Parallel-Access Shift Register
119 Parallel-access shift register [ Figure 5.18 from the textbook ]
120 Parallel-access shift register 0 When Load=0, this behaves like a shift register. [ Figure 5.18 from the textbook ]
121 Parallel-access shift register 1 When Load=1, this behaves like a parallel-access register. [ Figure 5.18 from the textbook ]
122 Shift Register With Parallel Load and Enable
123 A shift register with parallel load and enable control inputs [ Figure 5.59 from the textbook ]
124 A shift register with parallel load and enable control inputs The directions of the input and output lines are switched relative to the previous slides. [ Figure 5.59 from the textbook ]
125 A shift register with parallel load and enable control inputs Parallel Input Parallel Output [ Figure 5.59 from the textbook ]
126 A shift register with parallel load and enable control inputs 0 0 [ Figure 5.59 from the textbook ]
127 A shift register with parallel load and enable control inputs 0 1 [ Figure 5.59 from the textbook ]
128 A shift register with parallel load and enable control inputs 1 0 [ Figure 5.59 from the textbook ]
129 A shift register with parallel load and enable control inputs 1 1 [ Figure 5.59 from the textbook ]
130 Parallel-access shift left / right register
131 Parallel-access shift left/right register Complete the following circuit diagram to implement a 4-bit register that has both parallel load and shift left/right functionality. The register has two control inputs (C1 and C0), four parallel input lines (I3, I2, I1, and I0), and four output lines (3, 2, 1, and 0). epending on the values of C1 and C0, the register performs one of the following four operations:
132 Parallel-access shift left/right register
133 Parallel-access shift left/right register Clock
134 Parallel-access shift left/right register Clock
135 Parallel-access shift left/right register Out_3 Out_2 Out_1 Out_ Clock
136 Parallel-access shift left/right register Out_3 Out_2 Out_1 Out_ Clock In_0
137 Parallel-access shift left/right register Out_3 Out_2 Out_1 Out_ Clock In_3 In_0
138 Parallel-access shift left/right register Out_3 Out_2 Out_1 Out_ Clock In_3 In_2 In_1 In_0
139 Parallel-access shift left/right register Out_3 Out_2 Out_1 Out_ Clock In_3 In_2 In_1 In_0
140 Parallel-access shift left/right register Out_3 Out_2 Out_1 Out_0 C 0 C Clock In_3 In_2 In_1 In_0
141 Parallel-access shift left/right register Out_3 Out_2 Out_1 Out_0 C 0 C Clock In_3 In_2 In_1 In_0
142 Multiplexer Tricks (select one of two 2-bit numbers)
143 Select Either A=A 1 A 0 or B=B 1 B 0 s A 0 B F 0 A 1 B F 1
144 Select Either A=A 1 A 0 or B=B 1 B 0 s 0 A 0 B F 0 = A 0 A 1 B F 1 = A 1
145 Select Either A=A 1 A 0 or B=B 1 B 0 s 1 A 0 B F 0 = B 0 A 1 B F 1 = B 1
146 Multiplexer Tricks (select one of four 2-bit numbers)
147 Select A=A 1 A 0 or B=B 1 B 0 or C=C 1 C 0 or = 1 0 s s 1 0 A 0 B 0 C F A 1 B 1 C F
148 Select A=A 1 A 0 or B=B 1 B 0 or C=C 1 C 0 or = s s 1 0 A 0 B 0 C F = A 0 A 1 B 1 C F = A 1
149 Select A=A 1 A 0 or B=B 1 B 0 or C=C 1 C 0 or = s s 1 0 A 0 B 0 C F = B 0 A 1 B 1 C F = B 1
150 Select A=A 1 A 0 or B=B 1 B 0 or C=C 1 C 0 or = s s 1 0 A 0 B 0 C F = C 0 A 1 B 1 C F = C 1
151 Select A=A 1 A 0 or B=B 1 B 0 or C=C 1 C 0 or = s s 1 0 A 0 B 0 C F = 0 A 1 B 1 C F = 1
152 Register File
153 Complete the following circuit diagram to implement a register file with four 2-bit registers, one write port, one read port, and one write enable line.
154
155 Register 0 Register 1 Register 2 Register 3
156 Register A Register B Register C Register
157 A 1 A 0 Register A B 1 B 0 Register B C 1 C 0 Register C 1 0 Register
158 In 1 In 0 A 1 A 0 Register A B 1 B 0 Register B C 1 C 0 Register C 1 0 Register
159 In 1 In 0 A 1 A 0 Register A B 1 B 0 Register B C 1 C 0 Register C 1 0 Register Write_address_0 Write_address_1 Write_enable
160 In 1 In 0 A 1 A 0 Register A B 1 B 0 Register B C 1 C 0 Register C 1 0 Register Write_address_0 Write_address_1 Write_enable
161 In 1 In 0 A 1 A 0 Register A B 1 B 0 Register B C 1 C 0 Register C 1 0 Register Write_address_0 Write_address_1 Write_enable Out 1 Out 0 Read_address_1 Read_address_0
162 In 1 In 0 A 1 A 0 Register A B 1 B 0 Register B C 1 C 0 Register C 1 0 Register Clock Write_address_0 Write_address_1 Write_enable Out 1 Out 0 Read_address_1 Read_address_0
163 In 1 In 0 A 1 A 0 B 1 B 0 C 1 C Clock Write_address_0 Write_address_1 Write_enable Out 1 Out 0 Read_address_1 Read_address_0
164 uestions?
165 THE EN
CprE 281: Digital Logic
CprE 281: igital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Registers CprE 281: igital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Administrative
CprE 281: Digital Logic
CprE 281: igital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Registers CprE 281: igital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Administrative
CprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ T Flip-Flops & JK Flip-Flops CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander
CprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Registers and Counters CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
CprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Registers and Counters CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
Sequential Logic. E&CE 223 Digital Circuits and Systems (A. Kennings) Page 1
Sequential Logic E&CE 223 igital Circuits and Systems (A. Kennings) Page 1 Sequential Circuits Have considered only combinational circuits in which circuit outputs are determined entirely by current circuit
Logic Design. Flip Flops, Registers and Counters
Logic Design Flip Flops, Registers and Counters Introduction Combinational circuits: value of each output depends only on the values of inputs Sequential Circuits: values of outputs depend on inputs and
1. True/False Questions (10 x 1p each = 10p) (a) I forgot to write down my name and student ID number.
CprE 281: Digital Logic Midterm 2: Friday Oct 30, 2015 Student Name: Student ID Number: Lab Section: Mon 9-12(N) Mon 12-3(P) Mon 5-8(R) Tue 11-2(U) (circle one) Tue 2-5(M) Wed 8-11(J) Wed 6-9(Y) Thur 11-2(Q)
Engr354: Digital Logic Circuits
Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flip-flops;
ECE 341. Lecture # 2
ECE 341 Lecture # 2 Instructor: Zeshan Chishti zeshan@pdx.edu October 1, 2014 Portland State University Announcements Course website reminder: http://www.ece.pdx.edu/~zeshan/ece341.htm Homework 1: Will
Chapter 6. Flip-Flops and Simple Flip-Flop Applications
Chapter 6 Flip-Flops and Simple Flip-Flop Applications Basic bistable element It is a circuit having two stable conditions (states). It can be used to store binary symbols. J. C. Huang, 2004 Digital Logic
EECS 270 Midterm Exam Spring 2011
EES 270 Midterm Exam Spring 2011 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: Page # Points 2 /15 3 /10 4 /6 5 /12
Unit 11. Latches and Flip-Flops
Unit 11 Latches and Flip-Flops 1 Combinational Circuits A combinational circuit consists of logic gates whose outputs, at any time, are determined by combining the values of the inputs. For n input variables,
Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012
1 McGill University Faculty of Engineering ECSE-221B Introduction to Computer Engineering Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012 Examiner: Rola Harmouche Date:
EECS 270 Group Homework 4 Due Friday. June half credit if turned in by June
EES 270 Group Homework 4 ue Friday. June 1st @9:45am, half credit if turned in by June 1st @4pm. Name: unique name: Name: unique name: Name: unique name: This is a group assignment; all of the work should
problem maximum score 1 28pts 2 10pts 3 10pts 4 15pts 5 14pts 6 12pts 7 11pts total 100pts
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2002 4/5/02 Midterm Exam II Name: Solutions ID number:
AIM: To study and verify the truth table of logic gates
EXPERIMENT: 1- LOGIC GATES AIM: To study and verify the truth table of logic gates LEARNING OBJECTIVE: Identify various Logic gates and their output. COMPONENTS REQUIRED: KL-31001 Digital Logic Lab( Main
EMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP
EMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP 1 Chapter Overview Latches Gated Latches Edge-triggered flip-flops Master-slave flip-flops Flip-flop operating characteristics Flip-flop applications
1. Convert the decimal number to binary, octal, and hexadecimal.
1. Convert the decimal number 435.64 to binary, octal, and hexadecimal. 2. Part A. Convert the circuit below into NAND gates. Insert or remove inverters as necessary. Part B. What is the propagation delay
MODULE 3. Combinational & Sequential logic
MODULE 3 Combinational & Sequential logic Combinational Logic Introduction Logic circuit may be classified into two categories. Combinational logic circuits 2. Sequential logic circuits A combinational
Logic Design ( Part 3) Sequential Logic- Finite State Machines (Chapter 3)
Logic esign ( Part ) Sequential Logic- Finite State Machines (Chapter ) Based on slides McGraw-Hill Additional material 00/00/006 Lewis/Martin Additional material 008 Roth Additional material 00 Taylor
Introduction to Digital Logic Missouri S&T University CPE 2210 Flip-Flops
Introduction to igital Logic Missouri S&T University CPE 2210 Flip-Flops Egemen K. Çetinkaya Egemen K. Çetinkaya epartment of Electrical & Computer Engineering Missouri University of Science and Technology
Other Flip-Flops. Lecture 27 1
Other Flip-Flops Other types of flip-flops can be constructed by using the D flip-flop and external logic. Two flip-flops less widely used in the design of digital systems are the JK and T flip-flops.
12/31/2010. Overview. 12-Latches and Flip Flops Text: Unit 11. Sequential Circuits. Sequential Circuits. Feedback. Feedback
2/3/2 Overview 2-atches and Flip Flops Text: Unit equential Circuits et/eset atch Flip-Flops ECEG/IC 2 igital Operations and Computations Winter 2 r. ouie 2 equential Circuits equential circuits: Output
CS 261 Fall Mike Lam, Professor. Sequential Circuits
CS 261 Fall 2018 Mike Lam, Professor Sequential Circuits Circuits Circuits are formed by linking gates (or other circuits) together Inputs and outputs Link output of one gate to input of another Some circuits
CMSC 313 Preview Slides
CMSC 33 Preview Slides These are draft slides. The actual slides presented in lecture may be different due to last minute changes, schedule slippage,... UMBC, CMSC33, Richard Chang CMSC
Principles of Computer Architecture. Appendix A: Digital Logic
A-1 Appendix A - Digital Logic Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic A-2 Appendix A - Digital Logic Chapter Contents A.1 Introduction A.2 Combinational
Switching Circuits & Logic Design, Fall Final Examination (1/13/2012, 3:30pm~5:20pm)
Switching Circuits & Logic Design, Fall 2011 Final Examination (1/13/2012, 3:30pm~5:20pm) Problem 1: (15 points) Consider a new FF with three inputs, S, R, and T. No more than one of these inputs can be
D Latch (Transparent Latch)
D Latch (Transparent Latch) -One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that inputs S and R are never equal to 1 at the same time. This is done
ECE321 Electronics I
ECE321 Electronics I Lecture 25: Sequential Logic: Flip-flop Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: pzarkesh.unm.edu Slide: 1 Review of Last
ELE2120 Digital Circuits and Systems. Tutorial Note 7
ELE2120 Digital Circuits and Systems Tutorial Note 7 Outline 1. Sequential Circuit 2. Gated SR Latch 3. Gated D-latch 4. Edge-Triggered D Flip-Flop 5. Asynchronous and Synchronous reset Sequential Circuit
DALHOUSIE UNIVERSITY Department of Electrical & Computer Engineering Digital Circuits - ECED 220. Experiment 4 - Latches and Flip-Flops
DLHOUSIE UNIVERSITY Department of Electrical & Computer Engineering Digital Circuits - ECED 0 Experiment - Latches and Flip-Flops Objectives:. To implement an RS latch memory element. To implement a JK
Introduction to Sequential Circuits
Introduction to Sequential Circuits COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Introduction to Sequential Circuits Synchronous
Chapter 2. Digital Circuits
Chapter 2. Digital Circuits Logic gates Flip-flops FF registers IC registers Data bus Encoders/Decoders Multiplexers Troubleshooting digital circuits Most contents of this chapter were covered in 88-217
MODU LE DAY. Class-A, B, AB and C amplifiers - basic concepts, power, efficiency Basic concepts of Feedback and Oscillation. Day 1
DAY MODU LE TOPIC QUESTIONS Day 1 Day 2 Day 3 Day 4 I Class-A, B, AB and C amplifiers - basic concepts, power, efficiency Basic concepts of Feedback and Oscillation Phase Shift Wein Bridge oscillators.
1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. [4] Figure 1.
![1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. [4] Figure 1.](/thumbs/88/117492374.jpg "1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. [4] Figure 1.")
[Question 1 is compulsory] 1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. Figure 1.1 b) Minimize the following Boolean functions:
Sequential Logic Circuits
Sequential Logic Circuits By Dr. M. Hebaishy Digital Logic Design Ch- Rem.!) Types of Logic Circuits Combinational Logic Memoryless Outputs determined by current values of inputs Sequential Logic Has memory
Chapter Contents. Appendix A: Digital Logic. Some Definitions
A- Appendix A - Digital Logic A-2 Appendix A - Digital Logic Chapter Contents Principles of Computer Architecture Miles Murdocca and Vincent Heuring Appendix A: Digital Logic A. Introduction A.2 Combinational
Flip-Flops and Registers
The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and were used with permission from Cengage Learning. Flip-Flops and
6. Sequential Logic Flip-Flops
ection 6. equential Logic Flip-Flops Page of 5 6. equential Logic Flip-Flops ombinatorial components: their output values are computed entirely from their present input values. equential components: their
Chapter 5 Sequential Circuits
Logic and Computer Design Fundamentals Chapter 5 Sequential Circuits Part 2 Sequential Circuit Design Charles Kime & Thomas Kaminski 28 Pearson Education, Inc. (Hyperlinks are active in View Show mode)
Final Exam review: chapter 4 and 5. Supplement 3 and 4
Final Exam review: chapter 4 and 5. Supplement 3 and 4 1. A new type of synchronous flip-flop has the following characteristic table. Find the corresponding excitation table with don t cares used as much
Registers & Counters. Logic and Digital System Design - CS 303 Erkay Savaş Sabanci University
Registers & ounters Logic and igital System esign - S 33 Erkay Savaş Sabanci University Registers Registers like counters are clocked sequential circuits A register is a group of flip-flops Each flip-flop
Digital Logic Design ENEE x. Lecture 19
Digital Logic Design ENEE 244-010x Lecture 19 Announcements Homework 8 due on Monday, 11/23. Agenda Last time: Timing Considerations (6.3) Master-Slave Flip-Flops (6.4) This time: Edge-Triggered Flip-Flops
COE 202: Digital Logic Design Sequential Circuits Part 1. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:
COE 202: Digital Logic Design Sequential Circuits Part 1 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Objectives Sequential Circuits Memory Elements Latches Flip-Flops Combinational
L4: Sequential Building Blocks (Flip-flops, Latches and Registers)
L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements: Lecture material adapted from R. Katz, G. Borriello, Contemporary Logic esign (second edition), Prentice-Hall/Pearson
DIGITAL SYSTEM DESIGN UNIT I (2 MARKS)
DIGITAL SYSTEM DESIGN UNIT I (2 MARKS) 1. Convert Binary number (111101100) 2 to Octal equivalent. 2. Convert Binary (1101100010011011) 2 to Hexadecimal equivalent. 3. Simplify the following Boolean function
Experiment 8 Introduction to Latches and Flip-Flops and registers
Experiment 8 Introduction to Latches and Flip-Flops and registers Introduction: The logic circuits that have been used until now were combinational logic circuits since the output of the device depends
Course Administration
EE 224: INTRODUCTION TO DIGITAL CIRCUITS & COMPUTER DESIGN Lecture 5: Sequential Logic - 2 Analysis of Clocked Sequential Systems 4/2/2 Avinash Kodi, kodi@ohio.edu Course Administration 2 Hw 2 due on today
Computer Architecture and Organization
A-1 Appendix A - Digital Logic Computer Architecture and Organization Miles Murdocca and Vincent Heuring Appendix A Digital Logic A-2 Appendix A - Digital Logic Chapter Contents A.1 Introduction A.2 Combinational
CHAPTER 4: Logic Circuits
CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits
Solution to Digital Logic )What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it,
Solution to Digital Logic -2067 Solution to digital logic 2067 1.)What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it, A Magnitude comparator is a combinational
Digital Logic Design Sequential Circuits. Dr. Basem ElHalawany
Digital Logic Design Sequential Circuits Dr. Basem ElHalawany Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs
Flip-Flops. Because of this the state of the latch may keep changing in circuits with feedback as long as the clock pulse remains active.
Flip-Flops Objectives The objectives of this lesson are to study: 1. Latches versus Flip-Flops 2. Master-Slave Flip-Flops 3. Timing Analysis of Master-Slave Flip-Flops 4. Different Types of Master-Slave
CHAPTER 4: Logic Circuits
CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits
CHAPTER1: Digital Logic Circuits
CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits 1 Sequential Circuits Introduction Composed of a combinational circuit to which the memory elements are connected to form a feedback
PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops
PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops Objective Construct a two-bit binary decoder. Study multiplexers (MUX) and demultiplexers (DEMUX). Construct an RS flip-flop from discrete gates.
Chapter 6 Digital Circuit 6-5 Department of Mechanical Engineering
MEMS1082 Chapter 6 Digital Circuit 6-5 General digital system D Flip-Flops, The D flip-flop is a modification of the clocked SR flip-flop. The D input goes directly into the S input and the complement
Sequential Design Basics
Sequential Design Basics Lecture 2 topics A review of devices that hold state A review of Latches A review of Flip-Flops Unit of text Set-Reset Latch/Flip-Flops/D latch/ Edge triggered D Flip-Flop 8/22/22
Advanced Devices. Registers Counters Multiplexers Decoders Adders. CSC258 Lecture Slides Steve Engels, 2006 Slide 1 of 20
Advanced Devices Using a combination of gates and flip-flops, we can construct more sophisticated logical devices. These devices, while more complex, are still considered fundamental to basic logic design.
Chapter 5: Synchronous Sequential Logic
Chapter 5: Synchronous Sequential Logic NCNU_2016_DD_5_1 Digital systems may contain memory for storing information. Combinational circuits contains no memory elements the outputs depends only on the inputs
DIGITAL CIRCUIT COMBINATORIAL LOGIC
DIGITAL CIRCUIT COMBINATORIAL LOGIC Logic levels: one zero true false high low CMOS logic levels: 1 => 0.7 V DD 0.4 V DD = noise margin 0 =< 0.3 V DD Positive logic: high = 1 = true low = 0 = false Negative
LATCHES & FLIP-FLOP. Chapter 7
LATCHES & FLIP-FLOP Chapter 7 INTRODUCTION Latch and flip flops are categorized as bistable devices which have two stable states,called SET and RESET. They can retain either of this states indefinitely
Topic D-type Flip-flops. Draw a timing diagram to illustrate the significance of edge
Topic 1.3.2 -type Flip-flops. Learning Objectives: At the end of this topic you will be able to; raw a timing diagram to illustrate the significance of edge triggering; raw a timing diagram to illustrate
MUX AND FLIPFLOPS/LATCHES
MUX AN FLIPFLOPS/LATCHES BY: SURESH BALPANE Multiplexers 2:1 multiplexer chooses between two inputs S 1 0 Y 0 X 0 0 0 0 0 X 1 1 1 0 X 0 1 1 X 1 1 1 S Y @BALPANECircuits and Slide 2 Gate-Level Mux esign
EXPERIMENT: 1. Graphic Symbol: OR: The output of OR gate is true when one of the inputs A and B or both the inputs are true.
EXPERIMENT: 1 DATE: VERIFICATION OF BASIC LOGIC GATES AIM: To verify the truth tables of Basic Logic Gates NOT, OR, AND, NAND, NOR, Ex-OR and Ex-NOR. APPARATUS: mention the required IC numbers, Connecting
Flip-Flops and Sequential Circuit Design
Flip-Flops and Sequential Circuit Design ECE 52 Summer 29 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6
UNIT III. Combinational Circuit- Block Diagram. Sequential Circuit- Block Diagram
UNIT III INTRODUCTION In combinational logic circuits, the outputs at any instant of time depend only on the input signals present at that time. For a change in input, the output occurs immediately. Combinational
ELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 7 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
Lecture 8: Sequential Logic
Lecture 8: Sequential Logic Last lecture discussed how we can use digital electronics to do combinatorial logic we designed circuits that gave an immediate output when presented with a given set of inputs
Chapter. Synchronous Sequential Circuits
Chapter 5 Synchronous Sequential Circuits Logic Circuits- Review Logic Circuits 2 Combinational Circuits Consists of logic gates whose outputs are determined from the current combination of inputs. Performs
UNIVERSITY OF MASSACHUSSETS LOWELL Department of Electrical & Computer Engineering Course Syllabus for Logic Design Fall 2013
UNIVERSITY OF MASSACHUSSETS LOWELL Department of Electrical & Computer Engineering Course Syllabus for 16.265 Logic Design Fall 2013 I. General Information Section 201 Instructor: Professor Anh Tran Office
Midterm Exam 15 points total. March 28, 2011
Midterm Exam 15 points total March 28, 2011 Part I Analytical Problems 1. (1.5 points) A. Convert to decimal, compare, and arrange in ascending order the following numbers encoded using various binary
CSE Latches and Flip-flops Dr. Izadi. NOR gate property: A B Z Cross coupled NOR gates: S M S R Q M
CSE-4523 Latches and Flip-flops Dr. Izadi NOR gate property: A B Z A B Z Cross coupled NOR gates: S M S R M R S M R S R S R M S S M R R S ' Gate R Gate S R S G R S R (t+) S G R Flip_flops:. S-R flip-flop
Latches, Flip-Flops, and Registers. Dr. Ouiem Bchir
Latches, Flip-Flops, and Registers (Chapter #7) Dr. Ouiem Bchir The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney. Sequential
EE292: Fundamentals of ECE
EE292: Fundamentals of ECE Fall 2012 TTh 10:00-11:15 SEB 1242 Lecture 23 121120 http://www.ee.unlv.edu/~b1morris/ee292/ 2 Outline Review Combinatorial Logic Sequential Logic 3 Combinatorial Logic Circuits
Bachelor Level/ First Year/ Second Semester/ Science Full Marks: 60 Computer Science and Information Technology (CSc. 151) Pass Marks: 24
2065 Computer Science and Information Technology (CSc. 151) Pass Marks: 24 Time: 3 hours. Candidates are required to give their answers in their own words as for as practicable. Attempt any TWO questions:
Clocks. Sequential Logic. A clock is a free-running signal with a cycle time.
Clocks A clock is a free-running signal with a cycle time. A clock may be either high or low, and alternates between the two states. The length of time the clock is high before changing states is its high
YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall
YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall Objective: - Dealing with the operation of simple sequential devices. Learning invalid condition in
Sequential Digital Design. Laboratory Manual. Experiment #3. Flip Flop Storage Elements
The Islamic University of Gaza Engineering Faculty Department of Computer Engineering Spring 2018 ECOM 2022 Khaleel I. Shaheen Sequential Digital Design Laboratory Manual Experiment #3 Flip Flop Storage
IT T35 Digital system desigm y - ii /s - iii
UNIT - III Sequential Logic I Sequential circuits: latches flip flops analysis of clocked sequential circuits state reduction and assignments Registers and Counters: Registers shift registers ripple counters
Unit 9 Latches and Flip-Flops. Dept. of Electrical and Computer Eng., NCTU 1
Unit 9 Latches and Flip-Flops Dept. of Electrical and Computer Eng., NCTU 1 9.1 Introduction Dept. of Electrical and Computer Eng., NCTU 2 What is the characteristic of sequential circuits in contrast
1 Hour Sample Test Papers: Sample Test Paper 1. Roll No.
6.1.2 Sample Test Papers: Sample Test Paper 1 Roll No. Institute Name: Course Code: EJ/EN/ET/EX/EV/IC/IE/IS/MU/DE/ED/ET/IU Subject: Principles of Digital Techniques Marks: 25 1 Hour 1. All questions are
ECE 25 Introduction to Digital Design. Chapter 5 Sequential Circuits ( ) Part 1 Storage Elements and Sequential Circuit Analysis
EE 25 Introduction to igital esign hapter 5 Sequential ircuits (5.1-5.4) Part 1 Storage Elements and Sequential ircuit Analysis Logic and omputer esign Fundamentals harles Kime & Thomas Kaminski 2008 Pearson
ELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter
Chapter 6. sequential logic design. This is the beginning of the second part of this course, sequential logic.
Chapter 6. sequential logic design This is the beginning of the second part of this course, sequential logic. equential logic equential circuits simple circuits with feedback latches edge-triggered flip-flops
Sequential Circuits. Output depends only and immediately on the inputs Have no memory (dependence on past values of the inputs)
Sequential Circuits Combinational circuits Output depends only and immediately on the inputs Have no memory (dependence on past values of the inputs) Sequential circuits Combination circuits with memory
Logic and Computer Design Fundamentals. Chapter 7. Registers and Counters
Logic and Computer Design Fundamentals Chapter 7 Registers and Counters Registers Register a collection of binary storage elements In theory, a register is sequential logic which can be defined by a state
Chapter 5 Synchronous Sequential Logic
Chapter 5 Synchronous Sequential Logic Chih-Tsun Huang ( 黃稚存 ) http://nthucad.cs.nthu.edu.tw/~cthuang/ Department of Computer Science National Tsing Hua University Outline Introduction Storage Elements:
Introduction. NAND Gate Latch. Digital Logic Design 1 FLIP-FLOP. Digital Logic Design 1
2007 Introduction BK TP.HCM FLIP-FLOP So far we have seen Combinational Logic The output(s) depends only on the current values of the input variables Here we will look at Sequential Logic circuits The
Chapter 11 Latches and Flip-Flops
Chapter 11 Latches and Flip-Flops SKEE1223 igital Electronics Mun im/arif/izam FKE, Universiti Teknologi Malaysia ecember 8, 2015 Types of Logic Circuits Combinational logic: Output depends solely on the
Synchronous Sequential Logic
Synchronous Sequential Logic Ranga Rodrigo August 2, 2009 1 Behavioral Modeling Behavioral modeling represents digital circuits at a functional and algorithmic level. It is used mostly to describe sequential
Find the equivalent decimal value for the given value Other number system to decimal ( Sample)
VELAMMAL COLLEGE OF ENGINEERING AND TECHNOLOGY, MADURAI 65 009 Department of Information Technology Model Exam-II-Question bank PART A (Answer for all Questions) (8 X = 6) K CO Marks Find the equivalent
1.b. Realize a 5-input NOR function using 2-input NOR gates only.
. [3 points] Short Questions.a. Prove or disprove that the operators (,XOR) form a complete set. Remember that the operator ( ) is implication such that: A B A B.b. Realize a 5-input NOR function using
Objectives. Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath
Objectives Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath In the previous chapters we have studied how to develop a specification from a given application, and
Counters
Counters A counter is the most versatile and useful subsystems in the digital system. A counter driven by a clock can be used to count the number of clock cycles. Since clock pulses occur at known intervals,
INTRODUCTION TO SEQUENTIAL CIRCUITS
NOTE: Explanation Refer Class Notes Digital Circuits(15EECC203) INTRODUCTION TO SEQUENTIAL CIRCUITS by Nagaraj Vannal, Asst.Professor, School of Electronics Engineering, K.L.E. Technological University,
MC9211 Computer Organization
MC9211 Computer Organization Unit 2 : Combinational and Sequential Circuits Lesson2 : Sequential Circuits (KSB) (MCA) (2009-12/ODD) (2009-10/1 A&B) Coverage Lesson2 Outlines the formal procedures for the
Digital Networks and Systems Laboratory 2 Basic Digital Building Blocks Time 4 hours
Digital Networks and Systems Laboratory 2 Basic Digital Building Blocks Time 4 hours Aim To investigate the basic digital circuit building blocks constructed from combinatorial logic or dedicated Integrated
CSE140: Components and Design Techniques for Digital Systems. More D-Flip-Flops. Tajana Simunic Rosing. Sources: TSR, Katz, Boriello & Vahid
CSE140: Components and esign Techniques for igital Systems More -Flip-Flops Tajana Simunic Rosing Where we are now. What we covered last time: SRAM cell, SR latch, latch, -FF What we ll do next: -FF review,