ELCT201: DIGITAL LOGIC DESIGN

Transcription

1 ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, Dr. Eng. Wassim Alexan, Lecture 7 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter 2018

2 COURSE OUTLINE 1. Introduction 2. Gate-Level Minimization 3. Combinational Logic 4. Synchronous Sequential Logic 5. Registers and Counters 6. Memories and Programmable Logic 2

3 LECTURE OUTLINE Sequential Circuits Flip flops Master-Slave SR and D flip-flops Edge-Triggered D, JK and T flip-flops Flip-flops: Representation Summary of Terminology 3

4 FLIP-FLOP TYPES The commonly-used solution replaces the controlled D latch with a flip-flop We have two types of flip-flops Master-slave Edge-triggered 4

5 MASTER-SLAVE D FF USING LATCHES Clk D Y Q Timing diagram D Y Q Clk Circuit 5

6 MASTER-SLAVE D FF USING LATCHES The circuit samples the D input and changes its output Q only at the negative edge of the synchronizing or controlling clock When Clk = 0, the output of the inverter is 1 The slave latch is enabled and its output Q is equal to the master output Y The master latch is disabled because Clk = 0 D Y Q Clk Circuit 6

7 MASTER-SLAVE D FF USING LATCHES When the input pulse changes to the logic-1 level, the data from the external D is transferred to the master. The slave, however, is disabled as long as the clock remains at the logic-1 level, because its enable input is equal to 0 Any change in the input changes the master output at Y, but cannot affect the slave output D Y Q Clk Circuit 7

8 MASTER-SLAVE D FF USING LATCHES The value that is produced at the output of the flip-flop is the value that was stored in the master stage immediately before the negative edge occurred How to design a similar master-slave D flip-flop such that the output changes on the positive edge of the clock? D Y Q Clk Circuit 8

9 EDGE-TRIGGERED D FLIP-FLOP Sensitive to inputs only near the edge of the clock signal (not while high) signifies a positive edge Q(t) D Clk Q t Q pos Q neg Q pos Q neg 9

10 EDGE-TRIGGERED D FLIP-FLOP Sensitive to inputs only near the edge of the clock signal (not while high) This timing diagram is for a positive edge triggered D flip-flop Clk D Q Q Timing diagram 10

11 JK FLIP-FLOP USING D FLIP-FLOP Q t + 1 = D = JQ + K Q When J = K = 1, the output is complemented J sets the flip-flop to 1 K resets the flip-flop to 0 J K Clk Q Q Circuit Graphic symbol 11

12 T FLIP-FLOP USING JK FLIP-FLOP Q t + 1 = T Q T (toggle) flip-flop is a complementing flip-flop T = 0, no change T = 1, complement (toggle) T Q Q Circuit form JK FF Graphic symbol 12

13 T FF USING D FF Q t + 1 = D = T Q T (toggle) flip-flop is a complementing flip-flop T = 0, no change T = 1, complement (toggle) T Circuit form D FF Graphic symbol 13

14 FLIP-FLOPS: REPRESENTATION To represent any combinational circuit, we needed to write the truth table or logic function of the output To represent any flip-flop, we need to write the characteristic table, characteristic equation or excitation table A characteristic table defines the operation of a FF in a tabular form The next state is defined in terms of the current state and the inputs Q(t) refers to the current state (before the clock arrives) Q(t + 1) refers to the next state (after the clock arrives) Similar to the truth table in combinational circuits 14

15 FLIP-FLOPS: REPRESENTATION A characteristic equation defines the operation of a flipflop in an algebraic form For a D flip-flop: Q t + 1 For a JK flip-flop: Q t + 1 For a T flip-flop: Q t + 1 = D = JQ + K Q = T Q 15

16 Q t + 1 = JQ + K Q Q t + 1 = D Q t + 1 = T Q 16

17 FLIP-FLOPS: EXCITATION TABLES If we have the present and next output, what would be the input to the flip-flop that would lead to this output? Q(t) Q(t + 1) J K T D X X X X

18 STANDARD SYMBOLS FOR STORAGE ELEMENTS Latches Master-Slave Flip-flops Edge-Triggered Flip-flops 18

19 DIRECT INPUT (ASYNCHRONOUS INPUT) An example of an asynchronous sequential circuit is a counter circuit that counts the number of occurrences of some event Such a circuit is usually built using a number of flip-flops, whose outputs are interpreted as a number The counter circuit should be able to increment or decrement the number It is also important to be able to force the counter into a known initial state (count = 0), which means that all flip-flops must have Q = 0 Moreover, we should be able to preset each flip-flop to Q = 1, to insert some specific count as the initial value in the counter 19

20 DIRECT INPUT (ASYNCHRONOUS INPUT) These requirements can all be satisfied by incorporating a Clear and Preset inputs into the design of a flip-flop These extra inputs are called asynchronous because they can set or reset the flip-flop regardless of the status of the Clk signal Negative edge triggered D flip flop with Clear and Preset 20

21 SUMMARY OF TERMINOLOGY A basic latch is a feedback connection of two NOR gates or two NAND gates, which can store one bit of information. The NORbased latch can be set to 1 using the S input and reset to 0 using the R input A gated (clocked) latch is a basic latch that includes input gating and a control input signal. The latch retains its existing state when the control input is equal to 0. Its state may be changed when the control signal is equal to 1. We referred to this control input as the clock A gated (clocked) SR latch uses the S and R inputs to set the latch to 1 or reset it to 0, respectively A gated (clocked) D latch uses the input D to force the latch into a state that has the same logic value as the D input 21

22 SUMMARY OF TERMINOLOGY A flip-flop is a storage element based on the gated latch principle, which can have its output state changed only on the edge of the controlling clock signal A Master-slave flip-flop is built with two gated latches. The master stage is active during half of the clock cycle, and the slave stage is active during the other half. The output value of the flip-flop changes on the edge of the clock that activates the transfer into the slave stage An edge-triggered flip-flop is affected only by the input values present when the active edge of the clock occurs 22