Digital Logic & Computer Design CS Professor Dan Moldovan Spring Chapter 3 :: Sequential Logic Design

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1 igital Logic & Computer esign CS 4341 Professor an Moldovan Spring 21 Copyright 27 Elsevier 3-<1> Chapter 3 :: Sequential Logic esign igital esign and Computer Architecture avid Money Harris and Sarah L. Harris Copyright 27 Elsevier 3-<2> 1

2 Chapter 3 :: Topics Introduction Latches and Flip-Flops Synchronous Logic esign Finite State Machines Timing of Sequential Logic Parallelism Copyright 27 Elsevier 3-<3> Introduction Outputs of sequential logic depend on current and prior input values it has memory. Some definitions: State: all the information about a circuit necessary to explain its future behavior Latches and flip-flops: state elements that store one bit of state Synchronous sequential circuits: combinational logic followed by a bank of flip-flops Copyright 27 Elsevier 3-<4> 2

3 Sequential Circuits Give sequence to events Have memory (short-term) Use feedback from output to input to store information Copyright 27 Elsevier 3-<5> State Elements The state of a circuit influences its future behavior State elements store state Bistable circuit S Latch Latch Flip-flop Copyright 27 Elsevier 3-<6> 3

4 Bistable Circuit Fundamental building block of other state elements Two outputs:, No inputs I2 I1 I1 I2 Copyright 27 Elsevier 3-<7> Bistable Circuit Analysis Consider the two possible cases: = : then = 1 and = (consistent) 1 I1 I2 1 = 1: then = and = 1 (consistent) I1 1 1 I2 Bistable circuit stores 1 bit of state in the state variable, (or ) But there are no inputs to control the state Copyright 27 Elsevier 3-<8> 4

5 S (Set/eset) Latch S Latch N1 S N2 Consider the four possible cases: S = 1, = S =, = 1 S =, = S = 1, = 1 Copyright 27 Elsevier 3-<9> S Latch Analysis S = 1, = : then = 1 and = N1 S 1 N2 S =, = 1: then = and = 1 1 N1 S N2 Copyright 27 Elsevier 3-<1> 5

6 S Latch Analysis S = 1, = : then = 1 and = N1 1 S 1 N2 S =, = 1: then = and = N1 S N2 1 Copyright 27 Elsevier 3-<11> S Latch Analysis S =, = : then = prev prev = prev = 1 N1 N1 S N2 S N2 S = 1, = 1: then = and = 1 N1 1 N2 S Copyright 27 Elsevier 3-<12> 6

7 S Latch Analysis S =, = : then = prev and = prev (memory!) prev = prev = 1 1 N1 N1 1 S N2 1 1 S N2 S = 1, = 1: then = and = (invalid state: NOT ) 1 N1 1 N2 S Copyright 27 Elsevier 3-<13> S Latch Symbol S stands for Set/eset Latch Stores one bit of state () Control what value is being stored with S, inputs Set: Make the output 1 (S = 1, =, = 1) eset: Make the output (S =, = 1, = ) S Latch Symbol Must do something to avoid invalid state (when S = = 1) S Copyright 27 Elsevier 3-<14> 7

8 Latch Two inputs:, : controls when the output changes (the data input): controls what the output changes to Function When = 1, passes through to (the latch is transparent) When =, holds its previous value (the latch is opaque) Avoids invalid case when NOT Latch Symbol Copyright 27 Elsevier 3-<15> Latch Internal Circuit S S X S Copyright 27 Elsevier 3-<16> 8

9 Latch Internal Circuit S S X X 1 S prev prev 1 Copyright 27 Elsevier 3-<17> Flip-Flop Two inputs:, Function The flip-flop samples on the rising edge of When rises from to 1, passes through to Otherwise, holds its previous value changes only on the rising edge of A flip-flop is called an edge-triggered device because it is activated on the clock edge Flip-Flop Symbols Copyright 27 Elsevier 3-<18> 9

10 Flip-Flop Internal Circuit Two back-to-back latches (L1 and L2) controlled by complementary clocks When = L1 is transparent L2 is opaque passes through to N1 When = 1 L2 is transparent L1 is opaque N1 passes through to Thus, on the edge of the clock (when rises from 1) passes through to L1 N1 L2 Copyright 27 Elsevier 3-<19> Flip-Flop vs. Latch (latch) (flop) Copyright 27 Elsevier 3-<2> 1

11 Flip-Flop vs. Latch (latch) (flop) Copyright 27 Elsevier 3-<21> egisters 1 1 3: 4 4 3: Copyright 27 Elsevier 3-<22> 11

12 Enabled Flip-Flops Inputs:,, EN The enable input (EN) controls when new data () is stored Function EN = 1 passes through to on the clock edge EN = the flip-flop retains its previous state Internal Circuit Symbol EN 1 EN Copyright 27 Elsevier 3-<23> esettable Flip-Flops Inputs:,, eset Function: eset = 1 is forced to eset = the flip-flop behaves like an ordinary flip-flop Symbols eset r Copyright 27 Elsevier 3-<24> 12

13 esettable Flip-Flops Two types: Synchronous: resets at the clock edge only Asynchronous: resets immediately when eset = 1 Asynchronously resettable flip-flop requires changing the internal circuitry of the flip-flop (see Exercise 3.1) Synchronously resettable flip-flop? Copyright 27 Elsevier 3-<25> esettable Flip-Flops Two types: Synchronous: resets at the clock edge only Asynchronous: resets immediately when eset = 1 Asynchronously resettable flip-flop requires changing the internal circuitry of the flip-flop (see Exercise 3.1) Synchronously resettable flip-flop? Internal Circuit eset Copyright 27 Elsevier 3-<26> 13

14 Settable Flip-Flops Inputs:,, Set Funtion: Set = 1 is set to 1 Set = the flip-flop behaves like an ordinary flip-flop Symbols Set s Copyright 27 Elsevier 3-<27> Sequential Logic Sequential circuits: all circuits that aren t combinational A problematic circuit: X Y Z X Y Z time (ns) This circuit has no inputs and 1-3 outputs Copyright 27 Elsevier 3-<28> 14

15 Sequential Logic Sequential circuits: all circuits that aren t combinational A problematic circuit: X Y Z X Y Z time (ns) This circuit has no inputs and 1-3 outputs It is an astable circuit that oscillates Its period depends on the delay of the inverters which depends on the manufacturing process, temperature, etc The circuit has a cyclic path: output fed back to input Copyright 27 Elsevier 3-<29> Synchronous Sequential Logic esign Breaks cyclic paths by inserting registers These registers contain the state of the system The state changes at the clock edge, so we say the system is synchronized to the clock ules of synchronous sequential circuit composition: Every circuit element is either a register or a combinational circuit At least one circuit element is a register All registers receive the same clock signal Every cyclic path contains at least one register Two common synchronous sequential circuits Finite State Machines (FSMs) Pipelines Copyright 27 Elsevier 3-<3> 15

16 Finite State Machine (FSM) Consists of: State register that Store the current state and Load the next state at the clock edge S S Next State Current State Combinational logic that Computes the next state Computes the outputs Next State Logic C L Output Logic C L Next State Outputs Copyright 27 Elsevier 3-<31> Finite State Machines (FSMs) Next state is determined by the current state and the inputs Two types of finite state machines differ in the output logic: Moore FSM: outputs depend only on the current state Mealy FSM: outputs depend on the current state and the inputs Moore FSM inputs M next state logic k next state k state output logic N outputs Mealy FSM M inputs next state logic k next state k output logic N outputs Copyright 27 Elsevier 3-<32> state 16

17 Finite State Machine Example Traffic light controller Traffic sensors: T A, T B (TUE when there s traffic) Lights: L A, L B Academic Labs L A T A Bravado Blvd. T B T B ining Hall L B L A T A L B Fields Ave. orms Copyright 27 Elsevier 3-<33> FSM Black Box Inputs:, eset, T A, T B Outputs: L A, L B T A T B Traffic Light Controller L A L B eset Copyright 27 Elsevier 3-<34> 17

18 FSM State Transition iagram Moore FSM: outputs labeled in each state States: Circles Transitions: Arcs eset S L A : green L B : red Copyright 27 Elsevier 3-<35> FSM State Transition iagram Moore FSM: outputs labeled in each state States: Circles Transitions: Arcs eset S L A : green L B : red T A TA S1 L A : yellow L B : red S3 L A : red L B : yellow T B S2 L A : red L B : green T B Copyright 27 Elsevier 3-<36> 18

19 FSM State Transition Table Current State Inputs Next State S T A T B S' S X S 1 X S1 X X S2 X S2 X 1 S3 X X Copyright 27 Elsevier 3-<37> FSM State Transition Table Current State Inputs Next State S T A T B S' S X S1 S 1 X S S1 X X S2 S2 X S3 S2 X 1 S2 S3 X X S Copyright 27 Elsevier 3-<38> 19

20 FSM Encoded State Transition Table Current State Inputs Next State S 1 S T A T B S' 1 S' X 1 X 1 X X 1 X 1 X X X State Encoding S S1 1 S2 1 S3 11 Copyright 27 Elsevier 3-<39> FSM Encoded State Transition Table Current State Inputs Next State S 1 S T A T B S' 1 S' X 1 1 X 1 X X 1 1 X X X X State Encoding S S1 1 S2 1 S3 11 S' 1 = S 1 S S' = S 1 S T A + S 1 S T B Copyright 27 Elsevier 3-<4> 2

21 FSM Output Table Current State Outputs S 1 S L A1 L A L B1 L B Output Encoding green yellow 1 red 1 Copyright 27 Elsevier 3-<41> FSM Output Table Current State Outputs S 1 S L A1 L A L B1 L B Output Encoding green yellow 1 red 1 L A1 = S 1 L A = S 1 S L B1 = S 1 L B = S 1 S Copyright 27 Elsevier 3-<42> 21

22 FSM Schematic: State egister S' 1 S 1 S' r eset S state register Copyright 27 Elsevier 3-<43> FSM Schematic: Next State Logic S' 1 S 1 T A T B S 1 S S' r eset S inputs next state logic state register Copyright 27 Elsevier 3-<44> 22

23 FSM Schematic: Output Logic L A1 S' 1 S 1 L A T A S' r S L B1 T B eset S 1 S L B inputs next state logic state register output logic outputs Copyright 27 Elsevier 3-<45> FSM Timing iagram Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 1 C LK es et T A T B S ' 1:?? S () S1 ( 1) S2 (1 ) S3 (1 1) S ( ) S1 (1 ) S 1 :?? S ( ) S1 ( 1) S2 (1 ) S3 (1 1) S () L A 1 :?? Green () Yellow (1 ) ed (1 ) Green ( ) L B 1 :?? ed (1) Green ( ) Yellow (1) ed (1) eset S L A : green L B : red T A TA S1 L A : yellow L B : red t (se c) S3 S2 Copyright 27 Elsevier L A : red L A : red 3-<46> L B : yellow T B L B : green T B 23

24 FSM State Encoding Binary encoding: i.e., for four states,, 1, 1, 11 One-hot encoding One state bit per state Only one state bit is HIGH at once I.e., for four states, 1, 1, 1, 1 equires more flip-flops Often next state and output logic is simpler Copyright 27 Elsevier 3-<47> Moore vs. Mealy FSM Alyssa P. Hacker has a snail that crawls down a paper tape with 1 s and s on it. The snail smiles whenever the last four digits it has crawled over are 111. esign Moore and Mealy FSMs of the snail s brain. Copyright 27 Elsevier 3-<48> 24

25 State Transition iagrams reset Moore FSM S S1 S2 S3 1 S4 1 Mealy FSM: arcs indicate input/output Mealy FSM reset 1/ 1/ / 1/1 S S1 S2 S3 / 1/ / / Copyright 27 Elsevier 3-<49> Moore FSM State Transition Table Current State Inputs Next State S 2 S 1 S A S' 2 S' 1 S' State Encoding S S1 1 S2 1 S3 11 S4 1 Copyright 27 Elsevier 3-<5> 25

26 Moore FSM State Transition Table Current State Inputs Next State S 2 S 1 S A S' 2 S' 1 S' State Encoding S S1 1 S2 1 S3 11 S Copyright 27 Elsevier 3-<51> Moore FSM Output Table Current State Output S 2 S 1 S Y Copyright 27 Elsevier 3-<52> 26

27 Moore FSM Output Table Current State Output S 2 S 1 S Y Y = S 2 Copyright 27 Elsevier 3-<53> Mealy FSM State Transition and Output Table Current State Input Next State Output S 1 S A S' 1 S' Y State Encoding S S1 1 S2 1 S Copyright 27 Elsevier 3-<54> 27

28 Mealy FSM State Transition and Output Table Current State Input Next State Output S 1 S A S' 1 S' Y State Encoding S S1 1 S2 1 S3 11 Copyright 27 Elsevier 3-<55> Moore FSM Schematic A S' 2 S 2 Y S' 1 S 1 S' S eset S 2 S 1 S Copyright 27 Elsevier 3-<56> 28

29 Mealy FSM Schematic A S' 1 S 1 Y S' eset S S S 1 Copyright 27 Elsevier 3-<57> Moore and Mealy Timing iagram Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 1 eset A S Y S Moore Machine?? S S1 S2 S2 S3 S4 S2 S3 S4 S Mealy Machine?? S S1 S2 S2 S3 S1 S2 S3 S1 S Y Copyright 27 Elsevier 3-<58> 29

30 Factoring State Machines Break complex FSMs into smaller interacting FSMs Example: Modify the traffic light controller to have a Parade Mode. The FSM receives two more inputs: P, When P = 1, it enters Parade Mode and the Bravado Blvd. light stays green. When = 1, it leaves Parade Mode Copyright 27 Elsevier 3-<59> Parade FSM Unfactored FSM P T A T B Controller FSM L A L B Factored FSM P Mode FSM M T A T B Lights FSM L A L B Controller FSM Copyright 27 Elsevier 3-<6> 3

31 Unfactored FSM State Transition iagram PT A eset S L A : green L B : red P P S3 L A : red L B : yellow T A P P T A P P T B T A P T B S1 L A : yellow L B : red P S2 L A : red L B : green P T A T A S4 L A : green L B : red S7 L A : red L B : yellow T A T A S5 L A : yellow L B : red S6 L A : red L B : green P T B T B Copyright 27 Elsevier 3-<61> Factored FSM State Transition iagram eset S L A : green L B : red T A TA S1 L A : yellow L B : red S3 L A : red L B : yellow MT B S2 L A : red L B : green eset S M: P P S1 M: 1 M + T B Lights FSM Mode FSM Copyright 27 Elsevier 3-<62> 31

32 FSM esign Procedure Identify the inputs and outputs Sketch a state transition diagram Write a state transition table Select state encodings For a Moore machine: ewrite the state transition table with the selected state encodings Write the output table For a Mealy machine: ewrite the combined state transition and output table with the selected state encodings Write Boolean equations for the next state and output logic Sketch the circuit schematic Copyright 27 Elsevier 3-<63> Timing Flip-flop samples at clock edge must be stable when it is sampled Similar to a photograph, must be stable around the clock edge If is changing when it is sampled, metastability can occur Copyright 27 Elsevier 3-<64> 32

33 Input Timing Constraints Setup time: t setup = time before the clock edge that data must be stable (i.e. not changing) Hold time: t hold = time after the clock edge that data must be stable Aperture time: t a = time around clock edge that data must be stable (t a = t setup + t hold ) t setup t hold t Copyright 27 Elsevier a 3-<65> Output Timing Constraints Propagation delay: t pcq = time after clock edge that the output is guaranteed to be stable (i.e., to stop changing) Contamination delay: t ccq = time after clock edge that might be unstable (i.e., start changing) t ccq t pcq Copyright 27 Elsevier 3-<66> 33

34 ynamic iscipline The input to a synchronous sequential circuit must be stable during the aperture (setup and hold) time around the clock edge. Specifically, the input must be stable at least t setup before the clock edge at least until t hold after the clock edge Copyright 27 Elsevier 3-<67> ynamic iscipline The delay between registers has a minimum and maximum delay, dependent on the delays of the circuit elements 1 CL 2 (a) 1 2 T c 1 2 (b) Copyright 27 Elsevier 3-<68> 34

35 Setup Time Constraint The setup time constraint depends on the maximum delay from register 1 through the combinational logic. The input to register 2 must be stable at least t setup before the clock edge C L T c 2 t pcq t pd t setup 1 2 T c Copyright 27 Elsevier 3-<69> Setup Time Constraint The setup time constraint depends on the maximum delay from register 1 through the combinational logic. The input to register 2 must be stable at least t setup before the clock edge. 1 C L T c t pcq + t pd + t setup T c t pd 1 2 t pcq t pd t setup Copyright 27 Elsevier 3-<7> 35

36 Setup Time Constraint The setup time constraint depends on the maximum delay from register 1 through the combinational logic. The input to register 2 must be stable at least t setup before the clock edge. 1 C L T c t pcq + t pd + t setup T c t pd T c (t pcq + t setup ) 1 2 t pcq t pd t setup Copyright 27 Elsevier 3-<71> Hold Time Constraint The hold time constraint depends on the minimum delay from register 1 through the combinational logic. The input to register 2 must be stable for at least t hold after the clock edge. 1 C L t hold < t ccq t cd t hold Copyright 27 Elsevier 3-<72> 36

37 Hold Time Constraint The hold time constraint depends on the minimum delay from register 1 through the combinational logic. The input to register 2 must be stable for at least t hold after the clock edge. 1 C L t hold < t ccq + t cd t cd > t ccq t cd t hold Copyright 27 Elsevier 3-<73> Hold Time Constraint The hold time constraint depends on the minimum delay from register 1 through the combinational logic. The input to register 2 must be stable for at least t hold after the clock edge. 1 C L t hold < t ccq + t cd t cd > t hold - t ccq t ccq t cd t hold Copyright 27 Elsevier 3-<74> 37

38 Timing Analysis A B C X' X Timing Characteristics t ccq = 3 ps t pcq = 5 ps t setup = 6 ps t hold = 7 ps t pd = t cd = Setup time constraint: T c f c = 1/T c = Y' Y per gate t pd = 35 ps t cd = 25 ps Hold time constraint: t ccq + t pd > t hold? Copyright 27 Elsevier 3-<75> Timing Analysis A B C X' X Timing Characteristics t ccq = 3 ps t pcq = 5 ps t setup = 6 ps t hold = 7 ps Y' t pd = 3 x 35 ps = 15 ps t cd = 25 ps Setup time constraint: T c ( ) ps = 215 ps f c = 1/T c = 4.65 GHz Y per gate t pd = 35 ps t cd = 25 ps Hold time constraint: t ccq + t pd > t hold? (3 + 25) ps > 7 ps? No! Copyright 27 Elsevier 3-<76> 38

39 Fixing Hold Time Violation Add buffers to the short paths: A B C X' X Timing Characteristics t ccq = 3 ps t pcq = 5 ps t setup = 6 ps t hold = 7 ps t pd = Y' Y per gate t pd = 35 ps t cd = 25 ps t cd = Setup time constraint: Hold time constraint: T c t ccq + t pd > t hold? f c = Copyright 27 Elsevier 3-<77> Fixing Hold Time Violation Add buffers to the short paths: A B C X' X Timing Characteristics t ccq = 3 ps t pcq = 5 ps t setup = 6 ps t hold = 7 ps Y' Y t pd = 3 x 35 ps = 15 ps t cd = 2 x 25 ps = 5 ps Setup time constraint: T c ( ) ps = 215 ps f c = 1/T c = 4.65 GHz per gate t pd = 35 ps t cd = 25 ps Hold time constraint: t ccq + t pd > t hold? (3 + 5) ps > 7 ps? Yes! Copyright 27 Elsevier 3-<78> 39

40 Clock Skew The clock doesn t arrive at all registers at the same time Skew is the difference between two clock edges Examine the worst case to guarantee that the dynamic discipline is not violated for any register many registers in a system! delay C L t skew 1 2 Copyright 27 Elsevier 3-<79> Setup Time Constraint with Clock Skew In the worst case, the 2 is earlier than CL T c T c 1 2 t pcq t pd t setup t skew Copyright 27 Elsevier 3-<8> 4

41 Setup Time Constraint with Clock Skew In the worst case, the 2 is earlier than CL T c T c t pcq + t pd + t setup + t skew t pd 2 t pcq t pd t setup t skew Copyright 27 Elsevier 3-<81> Setup Time Constraint with Clock Skew In the worst case, the 2 is earlier than CL T c T c t pcq + t pd + t setup + t skew t pd T c (t pcq + t setup + t skew ) 2 t pcq t pd t setup t skew Copyright 27 Elsevier 3-<82> 41

42 Hold Time Constraint with Clock Skew In the worst case, 2 is later than C L t ccq + t cd > t cd > 2 t ccq t cd t skew t hold Copyright 27 Elsevier 3-<83> Hold Time Constraint with Clock Skew In the worst case, 2 is later than C L t ccq + t cd > t hold + t skew t cd > 2 t ccq t cd t skew t hold Copyright 27 Elsevier 3-<84> 42

43 Hold Time Constraint with Clock Skew In the worst case, 2 is later than C L t ccq + t cd > t hold + t skew t cd > t hold + t skew t ccq 2 t ccq t cd t skew t hold Copyright 27 Elsevier 3-<85> Violating the ynamic iscipline Asynchronous (for example, user) inputs might violate the dynamic discipline t setup t hold button t aperture Case I Case II Copyright 27 Elsevier 3-<86>??? Case III 43

44 Metastability Any bistable device has two stable states and a metastable state between them A flip-flop has two stable states (1 and ) and one metastable state If a flip-flop lands in the metastable state, it could stay there for an undetermined amount of time metastable stable stable Copyright 27 Elsevier 3-<87> Flip-flop Internals Because the flip-flop has feedback, if is somewhere between 1 and, the cross-coupled gates will eventually drive the output to either rail (1 or, depending on which one it is closer to). N1 S N2 A signal is considered metastable if it hasn t resolved to 1 or If a flip-flop input changes at a random time, the probability that the output is metastable after waiting some time, t, is: P(t res > t) = (T /T c ) e -t/τ t res : time to resolve to 1 or T, τ : properties of the circuit Copyright 27 Elsevier 3-<88> 44

45 Metastability Intuitively: T /T c describes the probability that the input changes at a bad time, i.e., during the aperture time P(t res > t) = (T /T c ) e -t/τ τ is a time constant indicating how fast the flip-flop moves away from the metastable state; it is related to the delay through the cross-coupled gates in the flip-flop P(t res > t) = (T /T c ) e -t/τ In short, if a flip-flop samples a metastable input, if you wait long enough (t), the output will have resolved to 1 or with high probability. Copyright 27 Elsevier 3-<89> Synchronizers Asynchronous inputs () are inevitable (user interfaces, systems with different clocks interacting, etc.). The goal of a synchronizer is to make the probability of failure (the output still being metastable) low. A synchronizer cannot make the probability of failure. SYNC Copyright 27 Elsevier 3-<9> 45

46 Synchronizer Internals A synchronizer can be built with two back-to-back flip-flops. Suppose the input is transitioning when it is sampled by flip-flop 1, F1. The amount of time the internal signal 2 can resolve to a 1 or is (T c - t setup ). F1 2 T c F2 2 metastable Copyright 27 Elsevier t t 3-<91> res setup t pcq Synchronizer Probability of Failure For each sample, the probability of failure of this synchronizer is: P(failure) = (T /T c ) e -(T c - t setup )/τ 2 F1 T c F2 2 metastable Copyright 27 Elsevier t t 3-<92> res setup t pcq 46

47 Synchronizer Mean Time Before Failure If the asynchronous input changes once per second, the probability of failure per second of the synchronizer is simply P(failure). In general, if the input changes N times per second, the probability of failure per second of the synchronizer is: P(failure)/second = (NT /T c ) e -(T c - t setup )/τ Thus, the synchronizer fails, on average, 1/[P(failure)/second] This is called the mean time between failures, MTBF: MTBF = 1/[P(failure)/second] = (T c /NT ) e (T c - t setup )/τ Copyright 27 Elsevier 3-<93> Example Synchronizer F1 2 F2 Suppose: T c = 1/5 MHz = 2 ns τ = 2 ps T = 15 ps t setup = 1 ps N = 1 events per second What is the probability of failure? MTBF? P(failure) = P(failure)/second = MTBF = Copyright 27 Elsevier 3-<94> 47

48 Example Synchronizer F1 2 F2 Suppose: T c = 1/5 MHz = 2 ns τ = 2 ps T = 15 ps t setup = 1 ps N = 1 events per second What is the probability of failure? MTBF? P(failure) = (15 ps/2 ns) e-(1.9 ns)/2 ps = P(failure)/second = 1 ( ) = / second MTBF = 1/[P(failure)/second] 5 hours Copyright 27 Elsevier 3-<95> Parallelism Two types of parallelism: Spatial parallelism duplicate hardware performs multiple tasks at once Temporal parallelism task is broken into multiple stages also called pipelining for example, an assembly line Copyright 27 Elsevier 3-<96> 48

49 Parallelism efinitions Some definitions: Token: A group of inputs processed to produce a group of outputs Latency: Time for one token to pass from start to end Throughput: The number of tokens that can be produced per unit time Parallelism increases throughput. Copyright 27 Elsevier 3-<97> Parallelism Example Ben Bitdiddle is baking cookies to celebrate the installation of his traffic light controller. It takes 5 minutes to roll the cookies and 15 minutes to bake them. After finishing one batch he immediately starts the next batch. What is the latency and throughput if Ben doesn t use parallelism? Latency = Throughput = Copyright 27 Elsevier 3-<98> 49

50 Parallelism Example Ben Bitdiddle is baking cookies to celebrate the installation of his traffic light controller. It takes 5 minutes to roll the cookies and 15 minutes to bake them. After finishing one batch he immediately starts the next batch. What is the latency and throughput if Ben doesn t use parallelism? Latency = = 2 minutes = 1/3 hour Throughput = 1 tray/ 1/3 hour = 3 trays/hour Copyright 27 Elsevier 3-<99> Parallelism Example What is the latency and throughput if Ben uses parallelism? Spatial parallelism: Ben asks Allysa P. Hacker to help, using her own oven Temporal parallelism: Ben breaks the task into two stages: roll and baking. He uses two trays. While the first batch is baking he rolls the second batch, and so on. Copyright 27 Elsevier 3-<1> 5

51 Spatial Parallelism Latency: time to first tray Spatial Parallelism Tray 1 Tray 2 Tray 3 Tray 4 Ben 1 Ben 1 Alyssa 1 Alyssa 1 Ben 2 Ben 2 Alyssa 2 Alyssa 2 Time oll Bake Legend Latency = Throughput = Copyright 27 Elsevier 3-<11> Spatial Parallelism Latency: time to first tray Spatial Parallelism Tray 1 Tray 2 Tray 3 Tray 4 Ben 1 Ben 1 Alyssa 1 Alyssa 1 Ben 2 Ben 2 Alyssa 2 Alyssa 2 Time oll Bake Legend Latency = = 2 minutes = 1/3 hour Throughput = 2 trays/ 1/3 hour = 6 trays/hour Copyright 27 Elsevier 3-<12> 51

52 Temporal Parallelism Latency: time to first tray Temporal Parallelism Tray 1 Tray 2 Tray 3 Ben 1 Ben 1 Ben 2 Ben 2 Ben 3 Ben 3 Time Latency = Throughput = Copyright 27 Elsevier 3-<13> Temporal Parallelism Latency: time to first tray Temporal Parallelism Tray 1 Tray 2 Tray 3 Ben 1 Ben 1 Ben 2 Ben 2 Ben 3 Ben 3 Time Latency = = 2 minutes = 1/3 hour Throughput = 1 trays/ 1/4 hour = 4 trays/hour Using both techniques, the throughput would be 8 trays/hour Copyright 27 Elsevier 3-<14> 52