ELCT201: DIGITAL LOGIC DESIGN

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ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.

1 ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, Dr. Eng. Wassim Alexan, Lecture 8 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter 2018

2 COURSE OUTLINE 1. Introduction 2. Gate-Level Minimization 3. Combinational Logic 4. Synchronous Sequential Logic 5. Registers and Counters 6. Memories and Programmable Logic 2

3 LECTURE OUTLINE Describing Sequential Circuits Finite State Machines Analysis of Sequential Circuits Designing of Sequential Circuits 3

DESCRIBING SEQUENTIAL CIRCUITS In previous lectures, we covered various memory elements and now we are ready to implement sequential circuits But first we need to know how to analyze or deal

4 DESCRIBING SEQUENTIAL CIRCUITS In previous lectures, we covered various memory elements and now we are ready to implement sequential circuits But first we need to know how to analyze or deal with a sequential circuit, which has outputs that are a function of not only the inputs, but also previous outputs Basically, we need a tool to help us describe the behavior of such circuits 4

5 FINITE STATE MACHINES (FSM) A FSM is a tool to model the desired behavior of a sequential system A designer would develop a finite state model of the system behavior and then design a circuit that implements this model A FSM consists of several states. Inputs into the machine are combined with the current state of the machine to determine the new state or next state of the machine 5

6 DESCRIBING A FSM We can describe a FSM using: A state equation (transition equation) Input variables, present states, next states equation A state table Input variables, present states, next states, truth table A state diagram 6

7 x ANALYSIS OF SEQUENTIAL CIRCUITS Example I A t + 1 = A t x t + B t x t B t + 1 = A t x t A y t = [A t + B t ]x t A State equations B B Example of a Sequental Circuit y The logic diagram of this sequential circuit could also be expressed algebraically with two FF input equations and an output equation: D A = Ax + Bx D B = A x y = (A + B)x State table 7

8 ANALYSIS OF SEQUENTIAL CIRCUITS Example I A t + 1 = Ax + Bx B t + 1 = A x y t = (A + B)x State equations State diagram State table 8

9 x y ANALYSIS WITH D FLIP-FLOPS Example II A D A = A x y Input equation Circuit diagram State diagram State table 9

10 ANALYSIS WITH JK FLIP-FLOPS Example III x A B J A = B K A = Bx J B = x K B = A x FF Input equations Clk Circuit diagram Can you write the FF input equations? 10

11 ANALYSIS WITH JK FLIP-FLOPS Example III Steps: 1. Write the present state and input columns 2. Write the FF inputs columns (using the FF input equations) 3. Write the next state columns (Using the JK FF excitation table) J A = B K A = Bx J B = x K B = A x FF Input equations Q(t) Q(t + 1) J K X X 1 0 X X 0 State table JK FF Excitation table 11

12 ANALYSIS WITH JK FLIP-FLOPS Example III State diagram State table 12

13 ANALYSIS WITH T FLIP-FLOPS Example IV x y T A = Bx T B = x y = AB Circuit diagram Input and output equations Clk Reset Can you write the FF input equations? 13

14 ANALYSIS WITH T FLIP-FLOPS Example IV Q t + 1 A t + 1 = T Q = T A A = Bx A + Bx A = AB + Ax + A Bx T A = Bx, T B = x, y = AB Input and output equations B t + 1 = T B B = x B T FF characteristic equations State table 14

15 ANALYSIS WITH T FLIP-FLOPS Example IV The output depends only on the present state, not on the input, thus, we write it using a slash after the state! State diagram State table 15

16 MEALY AND MOORE FSM 16

17 DESIGN OF SEQUENTIAL CIRCUITS The procedure of designing synchronous sequential circuits can be summarized in the following points: 1. From the word description and specifications of the desired operation, derive a state diagram of the circuit 2. Assign binary values to the states 3. Obtain the binary-coded state table 4. Choose the type of flip-flop to be used 5. Derive the simplified flip-flop input and output equations 6. Sketch the logic diagram 17

18 SYNTHESIS WITH T FLIP-FLOPS Example I Using T flip-flops, it is required to design a 3-bit binary counter that can count from 0 to 7 with a step of 1 Solution: 1. From the word description and the required specifications, we sketch the state diagram. Since each state consists of 3 bits, we need 3 flip-flops 18

19 SYNTHESIS WITH T FLIP-FLOPS Example I 19

20 SYNTHESIS WITH T FLIP-FLOPS Example I 2. Next, we derive the state table. The present and next states are known from the state diagram. While the FF inputs are obtained with the help of the T FF excitation table or characteristic equation 20

21 SYNTHESIS WITH T FLIP-FLOPS Example I 21

22 SYNTHESIS WITH T FLIP-FLOPS Example I 3. The FF input equations are then simplified using K-maps T A2 = A 1 A 0 22

23 SYNTHESIS WITH T FLIP-FLOPS Example I 3. The FF input equations are then simplified using K-maps T A1 = A 0 23

24 SYNTHESIS WITH T FLIP-FLOPS Example I 3. The FF input equations are then simplified using K-maps T A0 = 1 24

25 SYNTHESIS WITH T FLIP-FLOPS Example I 4. Using the simplified Boolean expressions for the inputs and outputs of the FF, we can sketch the logic diagram of this counting circuit T A2 = A 1 A 0 A 2 A 1 A 0 T A1 = A 0 T A0 = 1 Clk 25 1

26 SYNTHESIS WITH D FLIP-FLOPS Example II Design a FSM that detects 3 or more consecutive ones Solution: 1. From the word description and the required specifications, we sketch the state diagram 26

27 SYNTHESIS WITH D FLIP-FLOPS Example II The state diagram is derived by starting with state S 0, the reset state If the input is 0, the circuit stays in S 0, but if the input is 1, it goes to state S 1 to indicate that a 1 is detected If the next input is 1, the change is to state S 2 to indicate the arrival of two consecutive 1s, but if the input is 0, the state goes back to state S 0 If more 1s are detected, the circuit stays in S 3 27

28 SYNTHESIS WITH D FLIP-FLOPS Example II Any 0 input sends the circuit back to S 0 This way, the circuit stays in S 3 as long as there are 3 or more consecutive 1s received Note that the output does not depend on the input. It only depends on the state! (which is why the output is inside the state nodes, not on the arrows) If we reach S 3, this means that the circuit has detected 3 successive 1s 28

29 SYNTHESIS WITH D FLIP-FLOPS Example II 2. Next, we derive the state table The present and next states are known from the logic diagram The FF inputs are obtained with the help of the D FF excitation table or characteristic equation The output attains a value of 1 after three successive 1s are detected 29

30 SYNTHESIS WITH D FLIP-FLOPS Example II The columns for the FF input equations are exactly the ones for the next state, since we are using D flip-flops! Q(t) Q(t + 1) D

31 SYNTHESIS WITH D FLIP-FLOPS Example II 3. The FF input equations are then simplified using K-maps D A = Ax + Bx 31

32 SYNTHESIS WITH D FLIP-FLOPS Example II 3. The FF input equations are then simplified using K-maps D B = Ax + B x 32

33 SYNTHESIS WITH D FLIP-FLOPS Example II 3. The FF input equations are then simplified using K-maps y = AB 33

34 SYNTHESIS WITH D FLIP-FLOPS Example II 4. Using the simplified Boolean expressions for the inputs and outputs of the FF, we can sketch the logic diagram of this sequential circuit D A = Ax + Bx, D B = Ax + B x, y = AB 34

35 D A = Ax + Bx, D B = Ax + B x, y = AB A x B B y 35

36 ASSIGNMENT 2 Deadline of assignment 2 is Thursday the 22 nd of November,

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 7 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter