The World Leader in High Performance Signal Processing Solutions. Section 15. Parallel Peripheral Interface (PPI)

Transcription

1 The World Leader in High Performance Signal Processing Solutions Section 5 Parallel Peripheral Interface (PPI)

2 L Core Timer 64 Performance Core Monitor Processor ADSP-BF533 Block Diagram Instruction Memory LD 32 L Data LD 32 Memory JTAG/ Debug SD32 DMA Mastered Core DA bus Core D bus Core D bus 32 Core DA bus Core I bus 64 bus Core Clock (CCLK) Domain CORE/SYSTEM BUS INTERFACE System Clock (SCLK) Domain 6 DMA Core Bus (DCB) 6 Watchdog And Timers Real Time Clock Event Power Controller Management DMA Controller EBIU 6 Address DMA Ext Bus External Port Bus (DEB) (EPB) Peripheral Access Bus (PAB) DMA Access Bus (DAB) Programmable UART flags IRDA 5-2 SPORTs SPI PPI KB internal Boot ROM Data External Access Bus (EAB) Control

3 PPI - What is it? Parallel Peripheral Interface Programmable bus width (from 8 6 bits in -bit steps) Bidirectional (half-duplex) parallel interface Synchronous Interface Interface is driven by an external clock ( PPI_CLK ) Up to 66MHz rate (SCLK/2) Asynchronous to SCLK Includes three frame syncs to control the interface timing Applications High speed data converters Video CODECs Used Can in conjunction with a DMA channel setup 2D DMA (e.g., for video) Can pack 8-bit bytes into 6-bit words for efficient I/O 5-3

4 PPI in general purpose mode (For video and other high speed devices) Mixed Signal Front End PAB FS3/FIELD/PF3 TX_EN RX_EN FS2/VSYNC/TIMER2 DATAx FS/HSYNC/TIMER DAB AD9975 PPI3- PPI4-7/PF5-PF2 PPI8-5/PF-PF4 RX/TX CLK ADV783 HREF VREF FIELD P[5:] LLC2 PPI CLK NTSC/PAL Standard Video Decoder 5-4

5 General Purpose Input/Output Modes Single Sync (FS only) Useful for Data Converter applications Infinite Capture input sub-mode requires either initial H/W sync to be sent, or Self Trigger through S/W write (no need for H/W FS) 3 Syncs (FS, FS2, FS3) useful for video I/O with H/W signaling Frame Capture mode outputs syncs from processor while data is input into processor 2 Syncs can be used by ignoring 3rd sync where appropriate (pull FS3 to ground) Modes 5-5 are set in PPI_CONTROL register

6 PPI General Purpose Input Mode PPI_CLK PPI_CONTROL PPI_COUNT PAB Data Bus PPI_STATUS 8 8.EF 38 EE PPI_DELAY DMA Controller DAB DMA Request PPI_FRAME FS2 6-bit wide FIFO 6 deep - PACK: 8->6-Bit Packing Unit - GATE: Data Control Unit - SYNC: Data Sync Unit 5-6 FS PACK GATE SYNC FS3

7 Single Sync Input Mode PPI_CLK PPI_FS PPI_DATA PPI_DELAY PPI_CLK, 2 3 N- N PPI_COUNT PPI_FS, PPI_DATA are inputs Programmable delay register (PPI_DELAY) inserts a time delay (in units of PPI_CLK cycles) to start transfer after FS has been asserted Count register (PPI_COUNT) holds the number of samples the PPI will receive PPI_COUNT ignored during Infinite Capture 5-7

8 Three Sync Input Mode PPI_CLK PPI_FS PPI_FS2 PPI_FS3 PPI_DATA PPI_DELAY 2 3 N- N PPI_COUNT PPI_CLK, PPI_FS/2/3, PPI_DATA are inputs Coincident assertion of FS and FS2 with FS3 low indicates the start of a frame FS3 used to indicate odd/even fields. In a 2-FSx configuration, this line is pulled low. PPI_FRAME register is set to the number of lines per frame (lines are delineated by FS assertions) 5-8

9 PPI General Purpose Input Mode Frame Capture PPI_CLK PPI_CONTROL PPI_COUNT PAB Data Bus PPI_STATUS 37 PPI_DELAY DMA Controller DAB DMA Halt FS PPI_FRAME FS2 6-bit wide FIFO UPACK GATE 6 deep PPI_CLK - UPACK: 6->8-Bit Unpacking Unit - GATE: Data Control Unit - TIMER/2: Make use of Timers TIMER TIMER2 5-9 ED 38 EF 8 C7 FF

10 Frame Capture Input Mode PPI_CLK PPI_FS PPI_FS2 PPI_DATA PPI_DELAY 2 3 N- N PPI_COUNT PPI_CLK, PPI_DATA are inputs PPI_FS, PPI_FS2 are outputs TIMER_WIDTH/TIMER_PERIOD used to set up PPI_FS timing TIMER 2 set up to generate PPI_FS2 timing PPI_FRAME register is set to the number of lines per frame (lines are delineated by FS assertions) 5-

11 PPI General Purpose Output Mode PPI_CLK PPI_CONTROL PPI_COUNT PAB Data Bus PPI_STATUS 37 PPI_DELAY DMA Controller DAB DMA Halt FS PPI_FRAME FS2 6-bit wide FIFO UPACK GATE 6 deep PPI_CLK - UPACK: 6->8-Bit Unpacking Unit - GATE: Data Control Unit - TIMER/2: Make use of Timers TIMER TIMER2 5- ED 38 EF 8 C7 FF FS3/PF3

12 Single Sync Output Mode PPI_CLK PPI_FS PPI_DATA PPI_DELAY 2 3 N- N PPI_COUNT PPI_CLK is input PPI_FS and PPI_DATA are outputs Timer used to set up timing for FS There is a -cycle delay between FS assertion and start of PPI_DELAY Count register (PPI_COUNT) holds the number of samples the PPI will output, less one (i.e., set for N-) 5-2

13 Three Sync Output Mode PPI_CLK PPI_FS PPI_FS2 PPI_FS3 PPI_DATA PPI_DELAY 2 3 N- N PPI_COUNT PPI_CLK is input PPI_FS, PPI_FS2, PPI_FS3 and PPI_DATA are outputs Timer used to set up timing for FS Timer 2 used to set up timing for FS2 FS3 toggles coincident with an FS assertion, after an FS2 assertion 5-3

14 Video Basics Interlaced (2 x /6 sec=/3 sec) Screen Sizes QCIF = 76 x 44 pixels CIF = 352 x 288 pixels ¼ VGA = 32 x 24 pixels VGA = 64 x 48 pixels D (NTSC/PAL full screen) = 72 x 48 pixels [72 x 576 includes the unviewable portions above and below the picture] ret r ace Scan Types Interlaced dual-refresh technique on alternating lines at /6 second rate each (e.g. 8i = 8 horizontal lines interlaced) Progressive (Non-Interlaced) single refresh technique on all lines at a /3 second rate (e.g. 48p = 48 horizontal lines progressive scan) El ec tr o pa n g th un 2 Progressive (/3 sec) El ec tro pa n g th un 5-4

15 Video Framing Line Line 2 Line 3 Line 26 Line 262 Line 263 Line Video Blanking Line 2 Line 3 Line 26 Line 262 Line 263 CVBS 8-6 bit BUS Video Blank Video Blank Video Blank Video Blank Video Blank (H)SYNC (V)SYNC (F)IELD t 5-5

16 What constitutes a pixel? Black-and-white Y image (luminance) values only; One 8- or -bit Y value per pixel Color image RGB: Three 8- or -bit values per pixel YUV: Scaled and decorrelated version of RGB Y Cr Cb One Y (luminance) value per pixel (72 per line) One Cr or Cb (chrominance) value per pixel (36 of each per line) 4:2:2 4 Y s for every 2 Cr s and 2 Cb s 5-6 Cb Y Cr Y Cb Y Cr Y Cb Y Cr Y Cb Y Cr Y

17 ITU-6 ITU-6 - specifies methods for digitally coding signals Video coding RGB is an intuitive format, but channels are highly correlated YCrCb (a scaled and offset version of YUV color space) is highly uncorrelated Provides better compression characteristics 8-bit or -bit quantization NTSC and PAL each have 72 pixels per line NTSC (3 frames/sec) has 525 lines (including blanking) PAL (25 frames/sec) has 625 lines (including blanking) PPI 5-7 supports ITU-6 through use of 3-frame-sync modes

18 ITU-656 ITU-656 Defines the physical interfaces and data stream Bit-parallel and bit-serial modes Only bit-parallel supported with PPI 27 MHz nominal clock + 8- data lines (for bit-parallel mode) Embedded hardware signaling (H, V, F) no extra hardware lines required Supports interlaced and progressive formats Some OEMs support pseudo ITU

19 PPI ITU-656 Modes ITU-656 Input (3 Modes) Entire Field (H and V Blanking, Active Video and control codes) Vertical Blanking Interval only (with associated H blanking and control codes) Active video only. Can drop blanking for bandwidth savings ITU-656 User 5-9 Output sets up blanking and encoding info in memory

20 ITU-656 Mode Preamble 8bit Data Bus 8-bit DATA -bit DATA EAV/SAV F F X Y Statu s Word D9 D8 D7 D6 D5 D4 D3 D2 D D F V H P3 P2 P P The preamble (XY) holds the sync indicators VSYNC, HSYNC, Field. It also includes protection bits P-P3. In output mode the user must construct all preamble control codes In general, the 8-bit bus is for consumer markets while -bit bus is for professional markets. 5-2

21 PPI ITU-656 Input Mode PPI_CLK PPI_CONTROL PCHK PPI_COUNT PAB Data Bus PPI_STATUS FF C7 8 EF 38 EE PPI_DELAY DMA Controller PPI_FRAME DMA Request DAB 6-bit wide PACK FIFO - PCHK: Preamble Check Unit - PACK: 8->6-Bit Packing Unit - GATE: Data Control Unit GATE 6 deep 8bit Data Bus Blanking Active Video EAV F F SAV X Y F F 4 EAV X Y C B Y C R Y C B Y 44 C B Y F F

22 PPI ITU-656 Output Mode PPI_CLK PPI_CONTROL PPI_COUNT PAB Data Bus PPI_STATUS 37 PPI_DELAY DMA Controller DAB DMA Halt PPI_FRAME 6-bit wide FIFO 6 deep - UPACK: 6->8-Bit Unpacking Unit - GATE: Data Control Unit 5-22 UPACK GATE ED 38 EF 8 C7 FF

23 PPI Control Register (PPI_Control) FLD_SEL (Active Field Select) PORT_CFG[:] (Port Config.) In ITU-656 input mode: = Field = Fields and 2 In GP input mode: = External frame sync trigger = PPI self-trigger In input mode: = frame sync input = frame capture, FS, FS2 output = 3 frame syncs = infinite mode, frame sync not repeated In output mode: = sync PORT_EN (Enable) = 3 syncs = PPI disable = PPI enable PACK_EN (Packing Mode) = Disable = Enable SKIP_EN (Skip Enable) = Disable = Enable Addr: XFFC Reserved POL[:] (Polarity) = Nothing inverted = PPI_CLK inv., PPI_FS and PPI_FS2 not inv. = PPI_FS and PPI_FS2 inv., PPI_CLK not inverted = PPI_FS, PPI_FS2, and PPI_CLK inv SKIP_EO (Skip Even Odd) = Skip odd number of elem. = Skip even number of elem. DLEN[2:] (Data Length) = 8-bit = -bit.. = 5-bit = 6-bit PORT_DIR (Direction) = PPI receive mode = PPI transmit mode XFR_TYPE[:] (Transfer Type) In input mode: = Active field only = Entire field = Vertical Blanking only = GP Input mode In output mode:,, = ITU-656 Output Mode = GP Output Mode

24 PPI Status Register (PPI_STATUS) ERR_NCOR (Error not corrected) ITU-656 Mode: = Preamble error detected and corrected = Preamble error detected but not corrected FT_ERR (Frame Track Error) = No interrupt = Frame Track error interrupt occurred OVR (PPI FIFO Overflow) = No interrupt = FIFO Overflow Error interrupt occurred Reserved Read to clear Addr: XFFC FLD (Field Indicator) ERR_DET (Error Detected) ITU-656 Mode: = No preamble error detected = Preamble error detected 5-24 = Field = Field 2 UNDR (PPI FIFO Underrun) = No interrupt = FIFO Underrun error interrupt occurred

25 Transfer Count Register (PPI_COUNT) Addr: XFFC PPI_COUNT[5:] In GP input mode: One less than the number of samples to read in to the PPI per line In GP output mode: One less than the number of samples to write out through the PPI per line Delay Count Register (PPI_DELAY) Addr: XFFC C PPI_DELAY[5:] Number of PPI clock cycles to delay after assertation of PPI_FS before latching in data 5-25

26 Lines Per Frame Register (PPI_FRAME) 5 4 Addr: XFFC PPI_FRAME[5:] Holds the number of lines expected per frame of data 5-26