EE141-Fall 2010 Digital Integrated Circuits. Announcements. Homework #8 due next Tuesday. Project Phase 3 plan due this Sat.

Transcription

1 EE141-Fall 2010 Digital Integrated Circuits Lecture 24 Timing 1 1 Announcements Homework #8 due next Tuesday Project Phase 3 plan due this Sat. Hanh-Phuc s extra office hours shifted next week Tues. 3-4pm 2 2

2 Class Material Last lecture Latches and flip-flops Today s lecture Timing Reading Chapter 7, Timing 4 4

3 Synchronous Timing In R 1 R 2 C in C out Out 5 5 Latch Parameters D Q PW m T t setup D t clk-q t hold t d-q Q Delays can be different for rising and falling data transitions 6 6

4 Register Parameters D Q D t hold T t setup Q t clk-q Delays can be different for rising and falling data transitions 7 7 Timing Constraints In R1 R2 t 1 t 2 t cclk-q q t cclk-q,min cd tt su, t setup, hold t hold t logic logic t t logic, cd logic,min Cycle time (max): T > t clk-q + t logic + t setup Race margin (min): t hold < t clk-q,min + t logic,min 8 8

5 Clock Nonidealities Clock skew Spatial variation in temporally equivalent clock edges; deterministic + random, t SK Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) t JS Long term t JL Variation of the pulse width Important for level sensitive clocking 9 9 Clock Uncertainties 4 Power Supply 3 Interconnect 2 Devices Variation 5 Temperature 1 Clock Generation 6 Capacitive Load 7 Coupling to Adjacent Lines Sources of clock uncertainty 10 10

6 Clock Skew and Jitter t SK t JS Both skew and jitter affect the effective cycle time Only skew affects the race margin (usually) Clock Skew # of registers Earliest occurrence of edge Nominal δ/2 Latest occurrence of edge Nominal + δ /2 Insertion delay Max skew delay δ 12 12

7 Positive and Negative Skew In R1 R2 R3 t 1 t 2 t 3 delay (a) Positive skew delay In R1 D Q R2 R3 D Q t 1 t 2 t 3 delay delay (b) Negative skew Positive Skew T + δ 1 1 δ T δ + t h Launching edge arrives before the receiving edge 14 14

8 Negative Skew T - δ 1 1 T δ 4 Receiving edge arrives before the launching edge Timing Constraints In R1 R2 t 1 t 2 t clk-q t c q t t c q, cd clk-q,min t su, t hold t setup, t hold t logic t t logic logic, t cd logic,min Minimum cycle time: T clk - δ = t clk-q + t setup + t logic Worst case is when receiving edge arrives early (positive δ) 16 16

9 Timing Constraints In R1 R2 t 1 t 2 t clk-q c q t clk-q,min c cd t su, t hold t setup, t hold t logic t logic t logic, t cd logic,min Hold time constraint: t (clk-q,min) + t (logic,min) > t hold + δ Worst case is when receiving edge arrives late Race between data and clock Longest Path in Edge-Triggered Systems t clk-q T t logic t setup t JS + δ Latest point of launching Earliest arrival of next cycle 18 18

10 Clock Constraints in Edge-Triggered Systems If launching edge is late and receiving edge is early, the data will not be too late if: t clk-q + t logic + t setup < T t JS,1 t JS,2 - δ Minimum cycle time is determined by the maximum delays through the logic t clk-q + t logic + t setup + δ + 2t JS < T Skew can be either positive or negative Shortest Path Earliest point of launching t clk-q,min t logic,min t hold Nominal clock edge Data must not arrive before this time 20 20

11 Clock Constraints in Edge-Triggered Systems If launching edge is early and receiving edge is late: t clk-q,min + t logic,min t JS,1 > t hold + t JS,2 + δ Minimum logic delay t clk-q,min + t logic,min > t hold + 2t JS + δ (This assumes jitter at launching and receiving clocks are independent which usually is not true) Pipelining a a log Out log Out b b Reference Pipelined 22 22

12 Latch-Based Clocking In F G Out C 1 C 2 C 3 (Domino logic almost always uses latch-based clocking) Compute F compute G Latch vs. Flip-flop In a flip-flop based system: Data launches on one rising edge And must arrive before next rising edge If data arrives late, system fails If it arrives early, wasting time Flip-flops have hard edges In a latch-based system: Data can pass through latch while it is transparent Long cycle of logic can borrow time into next cycle As long as each loop finished in one cycle 24 24

13 Time Borrowing Example Latch vs. Flip-flop Summary Flip-flops generally easier to use Most digital ASICs designed with register-based timing But, latches (both pulsed and level-sensitive) allow more flexibility And hence can potentially achieve higher performance Latches can also be made more tolerant of clock un-certainty More in EE

14 Next Lecture Clock and power distribution 27 27