4-Ch. 250 MHz, 16-bit A/D, 2-Ch. 800 MHz, 16-bit D/A - FMC

Transcription

1 New! Model 3312 Features Four -bit s One digital upconverter Two 800 MHz -bit D/As Sample clock synchronization an external system reference VITA 57 FMC compatible Complete radar or software radio interface solution when combined with the Pentek FMC carriers Ruggedized and conductioncooled versions available 4-Ch., -bit, 2-Ch. 800 MHz, -bit D/A - FMC General Information The Flexor Model 3312 is a multichannel, high-speed data converter FMC module. It is suitable for connection HF or IF ports of a communications or radar system. It includes four, -bit s, programmable clocking, and multiboard synchronization for support of larger high-channel count systems. When combined with a Pentek 3U VPX or a FMC carrier, the 3312 is available as a FlexorSet, a complete turnkey data acquisition solution. For applications that require cusm processing, FlexorSets are ideal for IP development and deployment. Pentek also offers the option -990 reference design with software and IP support when installed on the Xilinx VC707 Evaluation Kit board. Converters The front end accepts four analog HF or IF inputs on front-panel connecrs with transformer-coupling in four Texas Instruments ADS42LB69 dual, -bit converters. Performance of the Model 3312 The true performance of the 3312 can be best unlocked when used with the Pentek FMC carriers as a FlexorSet. With facryinstalled IP, the board-set provides a turnkey data acquisition subsystem eliminating the need create any IP. Installed features include flexible acquisition, programmable linked-list DMA engines, and a metadata packet crear. uisition IP Modules With the 3312 installed on either the 5973 or the 7070 carrier, the board-set features four acquisition modules for easily capturing and moving data. Each module can receive data any of the four s, a test signal generar or the D/A waveform generar IP module in loopback mode. Each IP module can have an associated memory bank on the FMC carrier for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for easily moving data through the FMC carrier s interface. These powerful linked-list DMA engines are capable of a unique acquisition gate- driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample-accurate time stamp and data length information. These actions simplify the host processor s task of identifying and executing on the data. When used with the 5973 or the 7070, Pentek s ReadyFlow BSP provides control of all the 3312 s hardware and IP-based functions. Ready run examples and a fully-sourced C library provide a quickstart and powerful platform create cusm applications. ReadyFlow is compatible with Windows or Linux operating systems. D/A Waveform Generar IP Module With the 5973 or the 7070, the 3312 features a sophisticated D/A waveform generar IP module. A linked-list controller allows users easilyrecord the D/As wave-forms sred in either on-board or off-board host memory. Parameters including length of waveform, delay trigger, waveform repetition, etc. can be programmed for each waveform.

2 Model 3312 FMC Interface The Model 3312 complies with the VITA 57 High-Pin-Count FMC specification. The interface provides all data, clocking, synchronization, control and status signals between the 3312 and the FMC carrier. SPARK Development Systems SPARK systems are fullyintegrated saving engineers and system integrars the time and expense associated with building and testing a development system. SPARK systems ensure the optimum performance of Pentek boards and are available in 3U VPX (Model 8267) and in a PC environment (Model 8266). Ordering Information Channel -bit, 2-Channel 800 MHz -bit D/A FMC module Options: Reference design for 3312 installed on Xilinx VC707 Evaluation Kit 3U FlexorSet Description Channel with Virtex Channel, Virtex-7 with 4 multiband DDCs and interpolar Channel, Kintex UltraScale with 4 multiband DDCs and interpolar FlexorSet Description Channel with Virtex-7 -x Channel, Virtex-7 with 4 DDCs and interpolar -x8 Contact Pentek for availability of rugged and conductioncooled versions and other support options 4-Ch., -bit, 2-Ch. 800 MHz, -bit D/A - FMC Up 64 individual link entries can be chained gether create complex waveforms with minimum programming. Digital Upconverter and D/A Stage A TI DAC5688 DUC (digital upconverter) and D/A accepts a baseband real or complex data stream the and provides that input the upconvert, interpolate and D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals any IF center frequency DC the sampling frequency. It delivers the output the -bit D/A converter. Analog outputs are through front panel connecrs. If translation is disabled, the DAC5688 acts as a dual interpolating -bit D/A with output sampling rates up 800 MHz. In both modes the DAC5688 provides interpolation facrs of 2x, 4x and 8x. Clocking and Synchronization Two internal timing buses provide all timing and synchronization required by the and D/A converters. Each includes a clock, sync and gate or trigger signals. An on-board clock generar receives an external sample clock the front panel coaxial connecr. This clock can be used directly by the or D/A sections or divided by a built-in clock synthesizer circuit provide different and D/A clocks. In an alternate mode, the sample clock can be sourced an on-board programmable VCXO (Voltage-Controlled Crystal Oscillar). In this mode, the front coaxial panel connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel LVTTL Gate/Trigger/ Sync connecr can receive an external timing signal allowing multiple modules be synchronized thereby creating larger multi-board systems. Board Support Packages Pentek s BSPs provide control of the 3312 s hardware and IP-based functions. Ready run examples and a fully-sourced C library provide a powerful, quick-start platform create cusm applications. BSPs are compatible with Windows and Linux operating systems. ReadyFlow BSP is used with OnyxFX Virtex-7 carriers and Navigar BSP is used for all new development going forward including the JadeFX Kintex Ultrascale carriers. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Using Xilinx Vivado ols, developers can integrate their own IP with the Pentek facry-installed functions or use the development kit completely replace the Pentek IP with their own. GateFlow is used with OnyxFX Virtex-7 carriers and Navigar FDK is used for all new development going forward including the JadeFX Kintex UltraScale carriers. Model 3312 Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS42LB69 Sampling Rate: 10 MHz Resolution: bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: max. Output IF: DC 400 MHz max. Output Sampling Rate: 800 MHz max. with interpolation Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel connecr Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: an clock and a D/A clock Clock Synthesizer Clock Source: Selectable onboard programmable VCXO ( MHz) or front panel external clock Synchronization: VCXO can be phaselocked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8, or for the or D/A clocks External Clock Type: Front panel connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference External Trigger Input Type: Front panel connecr, LVTTL Function: Programmable functions include: trigger, gate, sync and PPS Environmental: Level L1 & L2 air cooled, Level L3 conduction-cooled, ruggedized I/O Module Interface: VITA-57.1, High- Pin- Count FMC

3 Model Ch., -bit, 2-Ch. 800 MHz, -bit D/A - FMC Pentek FlexorSet Models Form Type Carrier FMC FlexorSet Facr Development Tools Model Model 3U VPX Virtex Ch & 2 Ch 800 MHz D/A ReadyFlow BSP As above with 4 multiband DDCs & interpolation filters GateFlow FDK Ch -bit Vivado As above with 8 multiband DDCs Ch 3 GHz & 2 Ch 2.8 GHz MHz D/A Ch 500 MHz & 4 Ch 2 GHz D/A Kintex UltraScale Ch & 2 Ch 800 MHz D/A Navigar BSP with 4 multiband DDCs & interpolation filters Navigar FDK Ch -bit Vivado with 8 multiband DDCs Ch 3 GHz & 2 Ch 2.8 GHz MHz D/A Ch 500 MHz & 4 Ch 2 GHz D/A Virtex Ch & 2 Ch 800 MHz D/A ReadyFlow BSP As above with 4 multiband DDCs & interpolation filters GateFlow FDK Ch -bit Vivado As above with 8 multiband DDCs Ch 3 GHz & 2 Ch 2.8 GHz MHz D/A Ch 500 MHz & 4 Ch 2 GHz D/A

4 Model Model Features Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across Four -bit s One digital upconverter Two 800 MHz -bit D/As 4 GB of Sample clock synchronization an external system reference PCI Express (Gen. 1, 2 & 3) interface up x8 User-configurable gigabit serial interface Optional optical Interface for backplane gigabit serial interboard communication Optional connections the Virtex-7 for cusm I/O Compatible with several VITA standards including: VITA-46, VITA-48, VITA-66.4 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available 4-Ch. -bit, 2-Ch. 800 MHz -bit D/A - 3U VPX General Information Model is a member of the Flexor family of high-performance 3U VPX boards based on the Xilinx Virtex-7. As a FlexorSet TM integrated solution, the Model 3312 FMC is facry-installed on the 5973 FMC carrier. The required IP is installed and the board set is delivered ready for immediate use. The delivered FlexorSet is a multichannel, high-speed data converter and is suitable for connection the HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes four, -bit s, one digital upconverter, two 800 MHz, -bit D/As, and four banks of memory. In addition supporting Gen. 3 as a native interface, the Model includes optional copper and optical connections the Virtex-7 for cusm I/O. The Flexor Architecture Based on the proven design of the Pentek Onyx family of Virtex-7 products, the 5973 FMC carrier retains all the key features of that family. As a central foundation of the board architecture, the has access all data and control paths of both the carrier board and the FMC module, enabling facry-installed functions that include data multiplexing, channel selection, data packing, gating, triggering and memory control. Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS Model 3312 FMC Model 5973 FMC Carrier TIMING BUS Clock / Sync / Gate / PPS VCXO CONFIG FLASH VPX-P0 Clock/Sync Bus D/AClock/Sync Bus Control & Status Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 VPX-P1 In -BIT 4X Gigabit Serial I/O When delivered as an assembled board set, the includes facry-installed applications ideally matched the board s analog interfaces. The functions include four acquisition IP modules for simplifying data capture and data transfer. Each of the four acquisition IP modules contains IP modules for memories. The features a sophisticated D/A waveform playback IP module. A linked-list controller allows users easily play back the D/As waveforms sred in either onboard or off-board host memory. Parameters including length of waveform, delay playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. A controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the operate as a turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry- installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. In -BIT GPIO 0 10X VIRTEX-7 VX330T or VX690T pairs VPX-P2 (½) In -BIT FMC CONNECTOR FMC CONNECTOR In -BIT VPX BACKPLANE Out 800 MHz -BIT D/A DIGITAL UPCONVERTER Out 12X Gigabit Serial I/O OPTICAL TRANSCEIVER (Optional) VPX-P2 (½) VITA 66.4

5 Model uisition IP Modules The features four uisition IP Modules for easy capture and data moving. Each IP module can receive data any of the four s, a test signal generar or the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can can aumatically construct metadata packets containing channel ID, a sample accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Playback IP Module The facry-installed functions include a sophisticated D/A Waveform Playback IP module. A linked-list controller allows users easily play back waveforms sred in either on-board or off-board host memory the dual D/As. Parameters including length of waveform, delay playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. 4-Ch. -bit, 2-Ch. 800 MHz -bit D/A - 3U VPX Xilinx Virtex-7 The can be optionally populated with one of two Virtex-7 s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. A 4X connection between the and the VPX P1 connecr supports gigabit serial procols. Option -104 provides pairs of connections between the and the VPX P2 connecr for cusm I/O. Option -110 supports the VITA-66.4 standard that provides 12 optical duplex lanes the backplane. With the installation of a serial procol, the VITA-66.4 interface enables gigabit backplane communications between boards independent of the interface. GateXpress for Configuration The Flexor architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power-up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load FLASH. Bank 1 Ch 1 DETAILS OF VIRTEX-7 IP INSTALLED IN MODEL Module 1 Bank 1 DATA PACKING & FLOW METADATA IP MODULE 1 Module 2 Bank 2 Module 3 Bank 3 Ch 2 Mod 4 & D/A Mod Ch 3 INPUT MULTIPLEXER IP MODULES 2 & 3 This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on many systems. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power-up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first option load is an alternate image FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. INTEACE Ch 4 DATA PACKING & FLOW METADATA IP MODULE 4 D/A loopback TEST SIGNAL 8X Gigabit 4X Serial I/O GPIO D/A DATA UNPACKING & FLOW D/A WAVEFORM PLAYBACK IP MODULE

6 Model PCI Express Interface The Model includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and the board. Resources The architecture supports four independent memory banks. Each bank is deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. SPARK Development Systems The Model 8267 is a fullyintegrated development system for Pentek 3U VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel, 2-Channel 800 MHz -bit D/A with Virtex-7-3U VPX Options: -076 XC7VX690T I/O VPX P2-110 VITA X optical interface Contact Pentek for availability of rugged and conductioncooled versions 8267 VPX Development System See 8267 Datasheet for Options 4-Ch. -bit, 2-Ch. 800 MHz -bit D/A - 3U VPX In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts four analog HF or IF inputs on front-panel connecrs with transformer-coupling in two Texas Instruments ADS42LB69 dual, -bit converters. Digital Upconverter and D/A Stage A TI DAC5688 DUC and D/A accepts a baseband real or complex data stream the and provides that input the upconvert, interpolate and D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals any IF center frequency up 360 MHz. It delivers the output the -bit D/A converter. Analog outputs are through front panel connecrs. If translation is disabled, the DAC5688 acts as a dual interpolating -bit D/A with output sampling rates up 800 MHz. In both modes the DAC5688 provides interpolation facrs of 2x, 4x and 8x. Clocking and Synchronization Two internal timing buses provide all timing and synchronization required by the and D/A converters. Each includes a clock, sync and gate or trigger signals. An on-board clock generar receives an external sample clock the front panel coaxial connecr. This clock can be used directly by the or D/A sections or divided by a built-in clock synthesizer circuit provide different and D/A clocks. In an alternate mode, the sample clock can be sourced an on-board programmable VCXO. In this mode, the front coaxial panel connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel LVTTL Gate/Trigger/Sync connecr can receive an external timing signal synchronize multiple modules. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS42LB69 Sampling Rate: 10 MHz Resolution: bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: max. Output IF: DC 400 MHz max. Output Sampling Rate: 800 MHz max. with interpolation Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel connecr Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: an clock and a D/A clock Clock Synthesizer Clock Source: Selectable onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8 or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference External Trigger Input Type: Front panel connecr Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Option -076: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O 4X gigabit links between the and the VPX P1 connecr support serial procols. Parallel (Option -104): pairs of connections between the and the VPX P2 connecr for cusm I/O Optical (Option -110): VITA-66.4, 12X duplex lanes Type: Size: Four banks, each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Environmental: Level L1 & L2 air-cooled, Level L3 conduction-cooled, ruggedized Size: in. x in. (100 mm x mm)

7 Model Model Features Includes Xilinx Virtex-7 s GateXpress supports dynamic reconfiguration across Four -bit s Four multiband DDCs One digital upconverter Two 800 MHz -bit D/As Extended Interpolation Sample clock synchronization an external system reference PCI Express (Gen. 1, 2 & 3) interface up x8 User-configurable gigabit serial interface Optional optical Interface for backplane gigabit serial interboard communication connections the Virtex-7 for cusm I/O and synchronization Compatible with several VITA standards including: VITA-46, VITA-48, VITA-66.4 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available 4-Ch. -bit with DDCs, 2-Ch. 800 MHz -bit D/A with DUC and Extended Interpolation - 3U VPX General Information Model 5973 is a member of the OnyxFX family of high-performance 3U VPX baseboards with a Xilinx Virtex-7 and an available FMC I/O slot. As an integrated solution, the Model FlexorSet TM combines the Model 5973 and the Model 3312 Flexor FMC as a facry-installed set. The required IP is installed and the board set is delivered ready for immediate use. The delivered FlexorSet is a multichannel, high-speed data converter with programmable DDCs and is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm -processing IP. The Model includes four, -bit s, one digital upconverter, two 800 MHz, -bit D/As, and four banks of memory. In addition supporting Gen. 3 as a native interface, it includes optional copper and optical connections the Virtex-7 for cusm I/O. The Flexor Architecture Based on the proven design of the Pentek Onyx family of Virtex-7 products, the 5973 FMC carrier retains all the key features of that family. As a central foundation of the board architecture, the has access all data and control paths of both the carrier board and the FMC module, enabling facry-installed functions that include data multiplexing, channel selection, data packing, gating, triggering and memory control. Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS Model 3312 FMC Model 5973 FMC Carrier TIMING BUS Clock / Sync / Gate / PPS VCXO CONFIG FLASH VPX-P0 Clock/Sync Bus D/AClock/Sync Bus Control & Status Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 VPX-P1 In -BIT 4X Gigabit Serial I/O When delivered as an assembled board set, the includes facry-installed applications ideally matched the board s analog interfaces. The functions include four acquisition IP modules for simplifying data capture and data transfer. Each of the four acquisition IP modules contains a powerful DDC core. The features a sophisticated D/A waveform generar IP module. A linked-list controller allows users easily record the D/As waveforms sred in either on-board or off-board host memory. Parameters including length of waveform, delay trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. A controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the operate as a turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry-installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. In -BIT GPIO 0 10X VIRTEX-7 VX330T or VX690T pairs VPX-P2 (½) In -BIT FMC CONNECTOR FMC CONNECTOR In -BIT VPX BACKPLANE Out 800 MHz -BIT D/A DIGITAL UPCONVERTER Out 12X Gigabit Serial I/O OPTICAL TRANSCEIVER (Optional) VPX-P2 (½) VITA 66.4

8 Model uisition IP Modules The features four uisition IP Modules for easy capture and data moving. Each IP module can receive data any of the four s, a test signal generar or the D/A Waveform Generar IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Generar IP Module The facryinstalled functions include a sophisticated D/A Waveform Generar IP module. A linkedlist controller allows users easily record waveforms sred in either on-board or off-board host memory the dual D/As. Parameters including length of waveform, delay trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. 4-Ch. -bit with DDCs, 2-Ch. 800 MHz -bit D/A with DUC and Extended Interpolation - 3U VPX DDC IP Cores Within each uisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the Acquisition IP Modules, many different configurations can be achieved including one driving all four DDCs or each of the four s driving its own DDC. Each DDC has an independent -bit tuning frequency setting that ranges DC ƒ s, where ƒ s is the sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as four different output bandwidths for the board. Decimations can be program-med 2 65,536 providing a wide range satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or -bit I + -bit Q samples at a rate of ƒ s /N. Each DDC core contains programmable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up 8K samples. The power meters present Bank 1 DETAILS OF VIRTEX-7 IP INSTALLED IN MODEL Module 1 Bank 1 Module 2 Bank 2 Ch 1 DDC DEC: 2 TO POWER METER & THRESHOLD DETECT DDC CORE DATA PACKING & FLOW METADATA IP MODULE 1 Module 3 Bank 3 Ch 2 INPUT MULTIPLEXER IP MODULES 2 & 3 Mod 4 & D/A Mod Ch 3 Xilinx Virtex-7 The can be optionally populated with one of two Virtex-7 s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. A 4X connection between the and the VPX P1 connecr supports gigabit serial procols. Sixteen pairs of connections between the and the VPX P2 connecr for synchronization and cusm I/O. Option -110 supports the VITA standard that provides 12 optical duplex lanes the backplane. With the installation of a serial procol, the VITA interface enables gigabit backplane communications between boards independent of the interface. INTEACE average power measurements for each DDC core output in easy--read registers. In addition, each DDC core includes a threshold detecr aumatically send an interrupt the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. Ch 4 DDC DEC: 2 TO POWER METER & THRESHOLD DETECT DDC CORE DATA PACKING & FLOW METADATA IP MODULE 4 D/A loopback TEST SIGNAL 8X Gigabit 4X Serial I/O GPIO D/A INTERPOLATOR 2 TO IP CORE DATA UNPACKING & FLOW D/A WAVEFORM PLAYBACK IP MODULE

9 Model Ch. -bit with DDCs, 2-Ch. 800 MHz -bit D/A with DUC and Extended Interpolation - 3U VPX GateXpress for Configuration The Flexor architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power-up, Gate-Xpress immediately presents a target for the host computer discover, effectively giving the time load FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on many systems. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power-up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first option load is an alternate image FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts four analog HF or IF inputs on front-panel connecrs with transformer-coupling in two Texas Instruments ADS42LB69 dual, -bit converters. Digital Upconverter and D/A Stage A TI DAC5688 DUC and D/A accepts a baseband real or complex data stream the and provides that input the upconvert, interpolate and D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals any IF center frequency DC the sampling frequency. It delivers the output the -bit D/A converter. Analog outputs are through front panel connecrs. If translation is disabled, the DAC5688 acts as a dual interpolating -bit D/A with output sampling rates up 800 MHz. In both modes the DAC5688 provides interpolation facrs of 2x, 4x and 8x. In addition, the -based interpolar provides a range of 2x 65536x in two stages of 2x 256x. Including the DAC5688 interpolation, the overall available interpolation range equals 2x 524,288x. Clocking and Synchronization Two internal timing buses provide all timing and synchronization required by the and D/A converters. Each includes a clock, sync and gate or trigger signals. An on-board clock generar receives an external sample clock the front panel coaxial connecr. This clock can be used directly by the or D/A sections or divided by a built-in clock synthesizer circuit provide different and D/A clocks. In an alternate mode, the sample clock can be sourced an on-board programmable VCXO. In this mode, the front-panel coaxial connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel LVTTL Gate/Trigger/ Sync connecr can receive an external timing signal synchronize multiple modules.

10 Model Ch. -bit with DDCs, 2-Ch. 800 MHz -bit D/A with DUC and Extended Interpolation - 3U VPX SPARK Development Systems The Model 8267 is a fullyintegrated development system for Pentek 3U VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel -bit, with DDCs, 2-Channel 800 MHz -bit D/A with DUC, Extended Interpo-lation and Virtex-7-3U VPX Options: -076 XC7VX690T VITA X optical I/O with XC7VX690T, 4X w. XC7VX330T Contact Pentek for availability of rugged and conductioncooled versions 8267 VPX Development System See 8267 Datasheet for Options PCI Express Interface The Model includes an industrystandard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and the board. Resources The architecture supports four independent memory banks. Each bank is deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS42LB69 Sampling Rate: 10 MHz Resolution: bits 4-Channel Digital Downconverter Decimation Range: 2x 65,536x in two stages of 2x 256x LO Tuning Freq. Resolution: bits, 0 ƒs LO SFDR: >120 db Phase Offset Resolution: bits, degrees FIR Filter: 18-bit user-programmable coefficients, 24-bit output Default Filter Set: 80% bandwidth, <0.3 db passband ripple, >100 db spband attenuation Phase Shift Coefficients: I & Q with -bit resolution Gain Coefficients: -bit resolution D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: max. Output IF: DC 400 MHz max. Output Sampling Rate: 800 MHz max. with interpolation Resolution: bits Digital Interpolar Interpolation Range: 2x 65,536x in two stages of 2x 256x Total Interpolation Range D/A and digital combined: 2x 524,288x Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel connecr Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: an clock and a D/A clock Clock Synthesizer Clock Source: Selectable onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8 or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference External Trigger Input Type: Front panel connecr Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Option -076: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O 4X gigabit links between the and the VPX P1 connecr support serial procols. Parallel: pairs of connections between the and the VPX P2 connecr for synchronization and cusm I/O Optical (Option -110): VITA-66.4, 12X duplex lanes Type: Size: Four banks, each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Environmental: Level L1 & L2 air-cooled, Level L3 conduction-cooled, ruggedized Size: in. x in. (100 mm x mm)

11 New! FlexorSet Model Model Features VITA-57.4 HSPC FMC+ site offers access a wide range of possible I/O Supports Xilinx Kintex UltraScale Four -bit s Four multiband DDCs One digital upconverter Two 800 MHz -bit D/As Extended Interpolation Sample clock synchronization an external system reference PCI Express (Gen. 1, 2 & 3) interface up x8 User-configurable gigabit serial interface Optional optical Interface for backplane gigabit serial interboard communication connections the Kintex UltraScale for cusm I/O and synchronization Compatible with several VITA standards including: VITA-46, VITA-48, VITA-66.4 and VITA-65 (OpenVPX TM System Specification) Ruggedized and conductioncooled versions available 4-Ch. -bit with DDCs, 2-Ch. 800 MHz -bit D/A with DUC and Extended Interpolation - 3U VPX General Information Model 5983 is a member of the JadeFX TM family of high-performance 3U VPX base-boards with a Xilinx Kintex UltraScale and an available FMC I/O slot. As an integrated solution, the Model FlexorSet TM combines the Model 5983 and the Model 3313 Flexor FMC as a facry-installed set. The required IP is installed and the board set is delivered ready for immediate use. The delivered FlexorSet is a multichannel, high-speed data converter with programmable DDCs and is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm -processing IP. In addition the Gen. 3 x8 interface, the 5983 architecture includes an optional built-in gigabit serial optical interface. Up 12 high-speed duplex optical lanes are available on a VITA-66.4 connecr. With the installation of a serial procol in the, this interface enables a high-bandwidth connection between 5983s mounted in the same chassis or even over extended distances between them. The Flexor Architecture Based on the proven design of the Pentek Jade family of Kintex products, the 5983 FMC carrier retains all the key features of that family. As a central foundation of the board architecture, the has access all data and control paths of both the carrier board and the FMC module, enabling Model 3313 FMC Sample Clk / Reference Clk In TTL PPS/Gate/Sync Model 5983 FMC Carrier TIMING BUS Clock / Sync / Gate / PPS FREQUENCY SYNTHESIZER Antenna In GPS Clock/Sync Bus D/A Clock/Sync Bus Control & Status CONFIG FLASH In -BIT GTH 8X Gen. 3 x8 facry-installed functions that include data multiplexing, channel selection, data packing, gating, triggering and memory control. When delivered as an assembled board set, the includes facry-installed applications ideally matched the board s analog interfaces. The functions include four acquisition IP modules for simplifying data capture and data transfer. Each of the four acquisition IP modules contains a powerful DDC core. The features a sophisticated D/A waveform generar IP module. A linked-list controller allows users easily record the D/As waveforms sred in either on-board or off-board host memory. Parameters including length of waveform, delay trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. A controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the operate as a turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. The Pentek Navigar Design Kits include the board s entire design as a block diagram that can be edited in Xilinx s Vivado ol suite. In addition, all source code and complete IP core documentation is included. Developers can In -BIT GTH In -BIT FMC CONNECTOR KINTEX ULTRASCALE KU060 or KU115 4X HSPC FMC+ CONNECTOR Gigabit Serial I/O GPIO VPX-P0 VPX-P1 VPX-P2 (½) 0 In -BIT DDR4 5 GB Out 800 MHz 800 MHz -BIT D/A -BIT D/A DIGITAL UPCONVERTER 24X (8X available with KU060, 24X available with KU115) GTH 80 DDR4 4GB VPX BACKPLANE GTH Out 12X Gigabit Serial I/O OPTICAL TRANSCEIVER (Optional) VPX-P2 (½) VITA 66.4

12 Model uisition IP Modules The features four uisition IP Modules for easy capture and data moving. Each IP module can receive data any of the four s, a test signal generar or the D/A Waveform Generar IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Generar IP Module The facryinstalled functions include a sophisticated D/A Waveform Generar IP module. A linkedlist controller allows users easily record waveforms sred in either on-board or off-board host memory the dual D/As. Parameters including length of waveform, delay trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. 4-Ch. -bit with DDCs, 2-Ch. 800 MHz -bit D/A with DUC and Extended Interpolation - 3U VPX DDC IP Cores Within each uisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the Acquisition IP Modules, many different configurations can be achieved including one driving all four DDCs or each of the four s driving its own DDC. Each DDC has an independent -bit tuning frequency setting that ranges DC ƒ s, where ƒ s is the sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as four different output bandwidths for the board. Decimations can be program-med 2 65,536 providing a wide range satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or -bit I + -bit Q samples at a rate of ƒ s /N. Each DDC core contains programmable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up 8K samples. The power Bank 1 DETAILS OF KINTEX ULTRASCALE INSTALLED IN MODEL Modules Bank 1 Ch 1 DDC DEC: 2 TO POWER METER & THRESHOLD DETECT DDC CORE DATAPACKING & FLOW METADATA IP MODULE 1 D/A Module 5 Bank 2 ACQ IP MOD 2 Ch 2 Ch 3 INPUT MULTIPLEXER ACQ IP MOD 3 meters present average power measurements for each DDC core output in easy--read registers. In addition, each DDC core includes a threshold detecr aumatically send an interrupt the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. integrate their own IP along with the Pentek facry-installed functions or use the Navigar kit completely replace the Pentek IP with their own. Xilinx Kintex UltraScale The can be optionally populated with one of two Kintex UltraScale s match the specific requirements of the processing task. Supported s are KU060 or KU115. The KU115 features 5520 DSP48E2 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lowercost KU060 can be installed. Sixteen pairs of connections are optionally provided between the and the VPX P2 connecr for cusm I/O. For applications requiring cusm gigabit links, a 4X connection is supported between the and the VPX P1 connecr support serial procols. Bank 1 INTEACE Ch 4 DDC DEC: 2 TO POWER METER & THRESHOLD DETECT DDC CORE DATAPACKING & FLOW METADATA IP MODULE 4 D/A loopback Bank 2 TEST SIGNAL 8X Gigabit 4X Serial I/O GPIO D/A INTERPOLATOR 2 TO IP CORE DATA UNPACKING & FLOW D/A WAVEFORM IP MODULE

13 Model Ch. -bit with DDCs, 2-Ch. 800 MHz -bit D/A with DUC and Extended Interpolation - 3U VPX The supports the VITA-66.4 standard, that provides up 12 optical duplex lanes the backplane. With the installation of a serial procol, the VITA-66.4 interface enables gigabit backplane communications between boards independent of the interface. GPS An optional GPS receiver provides time and position information the. This information can be used for precise data tagging. Converter Stage The front end accepts four analog HF or IF inputs on front-panel connecrs with transformer-coupling in two Texas Instruments ADS42LB69 dual, -bit converters. Digital Upconverter and D/A Stage A TI DAC5688 DUC and D/A accepts a baseband real or complex data stream the and provides that input the upconvert, interpolate and D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals any IF center frequency DC the sampling frequency. It delivers the output the -bit D/A converter. Analog outputs are through front panel connecrs. If translation is disabled, the DAC5688 acts as a dual interpolating -bit D/A with output sampling rates up 800 MHz. In both modes the DAC5688 provides interpolation facrs of 2x, 4x and 8x. In addition, the -based interpolar provides a range of 2x 65536x in two stages of 2x 256x. Including the DAC5688 interpolation, the overall available interpolation range equals 2x 524,288x. Clocking and Synchronization Two internal timing buses provide all timing and synchronization required by the and D/A converters. Each includes a clock, sync and gate or trigger signals. An on-board clock generar receives an external sample clock the front panel coaxial connecr. This clock can be used directly by the or D/A sections or divided by a builtin clock synthesizer circuit provide different and D/A clocks. In an alternate mode, the sample clock can be sourced an on-board programmable VCXO. In this mode, the front-panel coaxial connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel LVTTL Gate/Trigger/ Sync connecr can receive an external timing signal synchronize multiple modules. PCI Express Interface The Model includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and the board. Resources The architecture supports two independent memory banks. The banks are four and five gigabytes each and are part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS42LB69 Sampling Rate: 10 MHz Resolution: bits 4-Channel Digital Downconverter Decimation Range: 2x 65,536x in two stages of 2x 256x LO Tuning Freq. Resolution: bits, 0 ƒs LO SFDR: >120 db Phase Offset Resolution: bits, degrees FIR Filter: 18-bit user-programmable coefficients, 24-bit output Default Filter Set: 80% bandwidth, <0.3 db passband ripple, >100 db spband attenuation Phase Shift Coefficients: I & Q with -bit resolution Gain Coefficients: -bit resolution

14 Model Ch. -bit with DDCs, 2-Ch. 800 MHz -bit D/A with DUC and Extended Interpolation - 3U VPX SPARK Development Systems The Model 8267 is a fullyintegrated development system for Pentek 3U VPX boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel -bit, with DDCs, 2-Channel 800 MHz -bit D/A with DUC, Extended Interpo-lation and Kintex Ultra- Scale - 3U VPX Options: -087 XCKU VITA X optical interface -180 GPS Support -702 Air cooled, Level L2-763 Conduction-cooled, Level L3 Contact Pentek for availability of rugged and conductioncooled versions Specifications, Continued D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: max. Output IF: DC 400 MHz max. Output Sampling Rate: 800 MHz max. with interpolation Resolution: bits Digital Interpolar Interpolation Range: 2x 65,536x in two stages of 2x 256x Total Interpolation Range D/A and digital combined: 2x 524,288x Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel connecr Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: an clock and a D/A clock Clock Synthesizer Clock Source: Selectable onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8 or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference External Trigger Input Type: Front panel connecr Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Kintex UltraScale XCKU060-2 Optional: Xilinx Kintex UltraScale XCKU115-2 Cusm I/O Serial: 4X gigabit links between the and the VPX P1 connecr support serial procols. Parallel: pairs of connections between the and the VPX P2 connecr for cusm I/O Optical (Option -110): VITA-66.4, 12X duplex lanes Type: DDR4 Size: Two banks, one 4 GB and one 5 GB Speed: 1200 MHz (2400 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Environmental Standard: L0 (air cooled) Operating Temp: 0 50 C Srage Temp: C Relative Humidity: 0 95%, noncondensing Option -702: L2 (air cooled) Operating Temp: C Srage Temp: C Relative Humidity: 0 95%, noncondensing Option -763: L3 (conduction cooled) Operating Temp: C Srage Temp: C Relative Humidity: 0 95%, noncondensing Size: in. x in. (100 mm x mm) OpenVPX Compatibility: The Model is compatibile with the following module profile, as defined by the VITA 65 Open-VPX Specification: SLT3-PAY-2F1F2U1E VPX Development System See 8267 Datasheet for Options

15 Model Ch. -bit, 2-Ch. 800 MHz -bit D/A - x8 Model General Information Model is a member of the Flexor family of high-performance boards based on the Xilinx Virtex-7. As a FlexorSet TM integrated solution, the Model 3312 FMC is facry-installed on the 5973 FMC carrier. The required IP is installed and the board set is delivered ready for immediate use. The delivered FlexorSet is a multichannel, high-speed data converter and is suitable for connection the HF or IF ports of a communications or radar system. Its built-in data capture features offer an ideal turnkey solution as well as a platform for developing and deploying cusm processing IP. It includes four, -bit s, one digital upconverter, two 800 MHz, -bit D/As, and four banks of memory. In addition supporting Gen. 3 as a native interface, the Model includes optional copper and optical connections the Virtex-7 for cusm I/O. The Flexor Architecture Based on the proven design of the Pentek Onyx family of Virtex-7 products, the 7070 FMC carrier retains all the key features of that family. As a central foundation of the board architecture, the has access all data and control paths of both the carrier board and the FMC module, enabling facry-installed functions that include data multiplexing, channel selection, data packing, gating, triggering and memory control. When delivered as an assembled board set, the includes facry-installed applications ideally matched the board s analog interfaces. The functions include four acquisition IP modules for simplifying data capture and data transfer. Each of the four acquisition IP modules contains IP modules for memories. The features a sophisticated D/A waveform playback IP module. A linked-list controller allows users easily play back the D/As waveforms sred in either onboard or off-board host memory. Parameters including length of waveform, delay playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. A controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the operate as a turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry- installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. Features Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across Four -bit s One digital upconverter Two 800 MHz -bit D/As 4 GB of Sample clock synchronization an external system reference PCI Express (Gen. 1, 2 & 3) interface up x8 Optional optical Interface for gigabit serial interboard communication Optional connections the Virtex-7 for cusm I/O Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS Model 3312 FMC Model 7070 FMC Carrier TIMING BUS Clock / Sync / Gate / PPS VCXO CONFIG FLASH Clock/Sync Bus D/AClock/Sync Bus Control & Status Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 Gen. 3 x8 In -BIT In -BIT pairs GPIO Card Edge Connecr FMC CONNECTOR FMC CONNECTOR 0 In -BIT 10X VIRTEX-7 VX330T or VX690T In -BIT Out 800 MHz -BIT D/A DIGITAL UPCONVERTER Out 12X Gigabit Serial I/O OPTICAL TRANSCEIVER (Optional) MTP Connecr

16 Model uisition IP Modules The features four uisition IP Modules for easy capture and data moving. Each IP module can receive data any of the four s, a test signal generar or the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can can aumatically construct metadata packets containing channel ID, a sample accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Playback IP Module The facry-installed functions include a sophisticated D/A Waveform Playback IP module. A linked-list controller allows users easily play back waveforms sred in either on-board or off-board host memory the dual D/As. Parameters including length of waveform, delay playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. 4-Ch. -bit, 2-Ch. 800 MHz -bit D/A - x8 Xilinx Virtex-7 The can be optionally populated with one of two Virtex-7 s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/ decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 provides pairs of connections between the and a card-edge connecr for cusm I/O. Option -110: For applications requiring optical gigabit links, up 12 high-speed, full-duplex lanes driven via an optical transceiver support serial procols. A 12-lane MTPoptical connecr is presented on the slot panel. GateXpress for Configuration The Flexor architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power-up, GateXpress immediately presents a target for the host computer discover, effectively giving the time load FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on many systems. Bank 1 Ch 1 DETAILS OF VIRTEX-7 IP INSTALLED IN MODEL Module 1 Bank 1 DATA PACKING & FLOW METADATA IP MODULE 1 Module 2 Bank 2 Module 3 Bank 3 Ch 2 Mod 4 & D/A Mod Ch 3 INPUT MULTIPLEXER IP MODULES 2 & 3 The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power-up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first option load is an alternate image FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the INTEACE Ch 4 DATA PACKING & FLOW METADATA IP MODULE 4 D/A loopback TEST SIGNAL 8X GPIO D/A DATA UNPACKING & FLOW D/A WAVEFORM PLAYBACK IP MODULE

17 Model Ch. -bit, 2-Ch. 800 MHz -bit D/A - x8 PCI Express Interface The Model includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and the board. Resources The architecture supports four independent memory banks. Each bank is deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. SPARK Development Systems The Model 8266 is a fullyintegrated PC development system for Pentek PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel, 2-Channel 800 MHz -bit D/A with Virtex-7 - x8 Options: -076 XC7VX690T I/O cardedge connecr x gigabit serial optical I/O with XC7VX690T, 4x w. XC7VX330T 8266 PC Development System See 8266 Datasheet for Options loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts four analog HF or IF inputs on front-panel connecrs with transformer-coupling in two Texas Instruments ADS42LB69 dual, -bit converters. Digital Upconverter and D/A Stage A TI DAC5688 DUC and D/A accepts a baseband real or complex data stream the and provides that input the upconvert, interpolate and D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals any IF center frequency up 360 MHz. It delivers the output the -bit D/A converter. Analog outputs are through front panel connecrs. If translation is disabled, the DAC5688 acts as a dual interpolating -bit D/A with output sampling rates up 800 MHz. In both modes the DAC5688 provides interpolation facrs of 2x, 4x and 8x. Clocking and Synchronization Two internal timing buses provide all timing and synchronization required by the and D/A converters. Each includes a clock, sync and gate or trigger signals. An on-board clock generar receives an external sample clock the front panel coaxial connecr. This clock can be used directly by the or D/A sections or divided by a built-in clock synthesizer circuit provide different and D/A clocks. In an alternate mode, the sample clock can be sourced an on-board programmable VCXO. In this mode, the front coaxial panel connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel LVTTL Gate/Trigger/ Sync connecr can receive an external timing signal synchronize multiple modules. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS42LB69 Sampling Rate: 10 MHz Resolution: bits D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: max. Output IF: DC 400 MHz max. Output Sampling Rate: 800 MHz max. with interpolation Resolution: bits Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel connecr Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: an clock and a D/A clock Clock Synthesizer Clock Source: Selectable onboard programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8 or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference External Trigger Input Type: Front panel connecr Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Option -076: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Parallel (Option -104): pairs of connections between the and a card-edge connecr for cusm I/O Optical (Option -110): 12x gigabit serial optical I/O with XC7VX690T, 4x with XC7VX330T Type: Size: Four banks, each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Environmental: Level L1 & L2 air-cooled, Size: in. x in (111.2 mm x mm)

18 Model Ch. -bit with DDCs, 2-Ch. 800 MHz -bit D/A with DUC and Extended Interpolation - x8 Model Features Supports Xilinx Virtex-7 VXT s GateXpress supports dynamic reconfiguration across Four -bit s Four multiband DDCs One digital upconverter Two 800 MHz -bit D/As Extended Interpolation 4 GB of Sample clock synchronization an external system reference PCI Express (Gen. 1, 2 & 3) interface up x8 Optional optical Interface for gigabit serial interboard communication Optional connections the Virtex-7 for cusm I/O General Information Model is a member of the Flexor family of high-performance boards based on the Xilinx Virtex-7. As a FlexorSet TM integrated solution, the Model 3312 FMC is facry-installed on the 7070 FMC carrier. The required IP is installed and the board-set is delivered ready for immediate use. The delivered FlexorSet is a multichannel, high-speed data converter with programmable DDCs and is suitable for connection HF or IF ports of a communications or radar system. Its built-in data capture and playback features offer an ideal turnkey solution as well as a platform for developing and deploying cusm -processing IP. The Model includes four, -bit s, one digital upconverter, two 800 MHz, -bit D/As, and four banks of memory. In addition supporting Gen. 3 as a native interface, it includes optional copper and optical connections the Virtex-7 for cusm I/O. The Flexor Architecture Based on the proven design of the Pentek Onyx family of Virtex-7 products, the 7070 FMC carrier retains all the key features of that family. As a central foundation of the board architecture, the has access all data and control paths of both the carrier board and the FMC module, enabling facry-installed functions that include data multiplexing, channel selection, data packing, gating, triggering and memory control. Sample Clk / Reference Clk In Gate / Trigger / Sync / PPS Model 3312 FMC Model 7070 FMC Carrier TIMING BUS Clock / Sync / Gate / PPS VCXO CONFIG FLASH Clock/Sync Bus D/AClock/Sync Bus Control & Status Config Bus GATEXPRESS CONFIGURATION MANAGER Gen. 3 x8 Gen. 3 x8 Gen. 3 x8 In -BIT When delivered as an assembled board set, the includes facry-installed applications ideally matched the board s analog interfaces. The functions include four acquisition IP modules for simplifying data capture and data transfer. Each of the four acquisition IP modules contains a powerful DDC core. The features a sophisticated D/A waveform playback IP module. A linked-list controller allows users easily play back the D/As waveforms sred in either onboard or off-board host memory. Parameters including length of waveform, delay playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. A controller for all data clocking and synchronization functions, a test signal generar, and a interface complete the facry-installed functions and enable the operate as a turnkey solution without the need develop any IP. Extendable IP Design For applications that require specialized functions, users can install their own cusm IP for data processing. Pentek GateFlow Design Kits include all of the facry- installed modules as documented source code. Developers can integrate their own IP with the Pentek facry-installed functions or use the GateFlow kit completely replace the Pentek IP with their own. In -BIT pairs GPIO Card Edge Connecr FMC CONNECTOR FMC CONNECTOR 0 In -BIT 10X VIRTEX-7 VX330T or VX690T In -BIT Out 800 MHz -BIT D/A DIGITAL UPCONVERTER Out 12X Gigabit Serial I/O OPTICAL TRANSCEIVER (Optional) MTP Connecr

19 Model uisition IP Modules The features four uisition IP Modules for easy capture and data moving. Each IP module can receive data any of the four s, a test signal generar or the D/A Waveform Playback IP Module in loopback mode. Each IP module has an associated memory bank for buffering data in FIFO mode or for sring data in transient capture mode. All memory banks are supported with DMA engines for moving data through the interface. These powerful linked-list DMA engines are capable of a unique Acquisition Gate Driven mode. In this mode, the length of a transfer performed by a link definition need not be known prior data acquisition; rather, it is governed by the length of the acquisition gate. This is extremely useful in applications where an external gate drives acquisition and the exact length of that gate is not known or is likely vary. For each transfer, the DMA engine can aumatically construct metadata packets containing channel ID, a sample accurate time stamp, and data length information. These actions simplify the host processor s job of identifying and executing on the data. D/A Waveform Playback IP Module The facry-installed functions include a sophisticated D/A Waveform Playback IP module. A linked-list controller allows users easily play back waveforms sred in either on-board or off-board host memory the dual D/As. Parameters including length of waveform, delay playback trigger, waveform repetition, etc. can be programmed for each waveform. Up 64 individual link entries can be chained gether create complex waveforms with a minimum of programming. 4-Ch. -bit with DDCs, 2-Ch. 800 MHz -bit D/A with DUC and Extended Interpolation - x8 DDC IP Cores Within each uisition IP Module is a powerful DDC IP core. Because of the flexible input routing of the Acquisition IP Modules, many different configurations can be achieved including one driving all four DDCs or each of the four s driving its own DDC. Each DDC has an independent -bit tuning frequency setting that ranges DC ƒ s, where ƒ s is the sampling frequency. Each DDC can have its own unique decimation setting, supporting as many as four different output bandwidths for the board. Decimations can be programmed 2 65,536 providing a wide range satisfy most applications. The decimating filter for each DDC accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒ s /N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 db. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q or -bit I + -bit Q samples at a rate of ƒ s /N. Each DDC core contains programable I & Q phase and gain adjustments followed by a power meter that continuously measures the individual average power output. The time constant of the averaging interval for each meter is programmable up 8K samples. The power meters present average power Bank 1 DETAILS OF VIRTEX-7 IP INSTALLED IN MODEL Module 1 Bank 1 Module 2 Bank 2 Ch 1 DDC DEC: 2 TO POWER METER & THRESHOLD DETECT DDC CORE DATA PACKING & FLOW METADATA IP MODULE 1 Module 3 Bank 3 Ch 2 INPUT MULTIPLEXER IP MODULES 2 & 3 Mod 4 & D/A Mod Ch 3 INTEACE measurements for each DDC core output in easy--read registers. In addition, each DDC core includes a threshold detecr aumatically send an interrupt the processor if the average power level of any DDC core falls below or exceeds a programmable threshold. Xilinx Virtex-7 The can be optionally populated with one of two Virtex-7 s match the specific requirements of the processing task. Supported s are VX330T or VX690T. The VX690T features 3600 DSP48E1 slices and is ideal for modulation/demodulation, encoding/decoding, encryption/decryption, and channelization of the signals between transmission and reception. For applications not requiring large DSP resources or logic, the lower-cost VX330T can be installed. Option -104 provides pairs of connections between the and a card-edge connecr for cusm I/O. Option -110 supports the VITA-66.4 standard that provides 12 optical duplex lanes the backplane. With the installation of a serial procol, the VITA-66.4 interface enables gigabit backplane communications between boards independent of the interface. Ch 4 DDC DEC: 2 TO POWER METER & THRESHOLD DETECT DDC CORE DATA PACKING & FLOW METADATA IP MODULE 4 D/A loopback TEST SIGNAL 8X GPIO D/A INTERPOLATOR 2 TO IP CORE DATA UNPACKING & FLOW D/A WAVEFORM PLAYBACK IP MODULE

20 Model Ch. -bit with DDCs, 2-Ch. 800 MHz -bit D/A with DUC and Extended Interpolation - x8 GateXpress for Configuration The Flexor architecture includes GateXpress, a sophisticated - configuration manager for loading and reloading the. At power-up, Gate- Xpress immediately presents a target for the host computer discover, effectively giving the time load FLASH. This is especially important for larger s where the loading times can exceed the discovery window, typically 100 msec on many systems. The board s configuration FLASH can hold four images. Images can be facry-installed IP or cusm IP created by the user, and programmed in the FLASH via JTAG using Xilinx impact or through the board s interface. At power-up the user can choose which image will load based on a hardware switch setting. Once booted, GateXpress allows the user three options for dynamically reconfiguring the with a new IP image. The first option load is an alternate image FLASH through software control. The user selects the desired image and issues a reload command. The second option is for applications where the image must be loaded directly through the interface. This is important in security situations where there can be no latent user image left in nonvolatile memory when power is removed. In applications where the IP may need change many times during the course of a mission, images can be sred on the host computer and loaded through as needed. The third option, typically used during development, allows the user directly load the through JTAG using Xilinx impact. In all three loading scenarios, GateXpress handles the hardware negotiation simplifying and streamlining the loading task. In addition, GateXpress preserves the configuration space allowing dynamic reconfiguration without needing reset the host computer rediscover the board. After the reload, the host simply continues see the board with the expected device ID. Converter Stage The front end accepts four analog HF or IF inputs on front-panel connecrs with transformer-coupling in two Texas Instruments ADS42LB69 dual, -bit converters. Digital Upconverter and D/A Stage A TI DAC5688 DUC and D/A accepts a baseband real or complex data stream the and provides that input the upconvert, interpolate and D/A stages. When operating as a DUC, it interpolates and translates real or complex baseband input signals any IF center frequency up 360 MHz. It delivers the output the -bit D/A converter. Analog outputs are through front panel connecrs. If translation is disabled, the DAC5688 acts as a dual interpolating -bit D/A with output sampling rates up 800 MHz. In both modes the DAC5688 provides interpolation facrs of 2x, 4x and 8x. In addition, the -based interpolar provides a range of 2x 65536x in two stages of 2x 256x. Including the DAC5688 interpolation, the overall available interpolation range equals 2x 524,288x. Clocking and Synchronization Two internal timing buses provide all timing and synchronization required by the and D/A converters. Each includes a clock, sync and gate or trigger signals. An on-board clock generar receives an external sample clock the front panel coaxial connecr. This clock can be used directly by the or D/A sections or divided by a built-in clock synthesizer circuit provide different and D/A clocks. In an alternate mode, the sample clock can be sourced an on-board programmable VCXO. In this mode, the front-panel coaxial connecr can be used provide a 10 MHz reference clock for synchronizing the internal oscillar. A front panel LVTTL Gate/Trigger/ Sync connecr can receive an external timing signal synchronize multiple modules.

21 Model Ch. -bit with DDCs, 2-Ch. 800 MHz -bit D/A with DUC and Extended Interpolation - x8 SPARK Development Systems The Model 8266 is a fullyintegrated PC development system for Pentek PCI Express boards. It was created save engineers and system integrars the time and expense associated with building and testing a development system that ensures optimum performance of Pentek boards. Ordering Information Channel -bit, with DDCs, 2-Channel 800 MHz -bit D/A with DUC, Extended Interpo-lation and Virtex-7 -x8 Options: -076 XC7VX690T I/O between the and a cardedge connecr for cusm I/O -110 VITA X optical I/O with XC7VX690T, 4X w. XC7VX330T 8266 PC Development System See 8266 Datasheet for Options PCI Express Interface The Model includes an industry-standard interface fully compliant with PCI Express Gen. 1, 2 and 3 bus specifications. Supporting links up x8, the interface includes multiple DMA controllers for efficient transfers and the board. Resources The architecture supports four independent memory banks. Each bank is deep and is an integral part of the board s DMA capabilities, providing FIFO memory space for creating DMA packets. Specifications Front Panel Analog Signal Inputs Input Type: Transformer-coupled, front panel connecrs Transformer Type: Coil Craft WBC4-6TLB Full Scale Input: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Converters Type: Texas Instruments ADS42LB69 Sampling Rate: 10 MHz Resolution: bits 4-Channel Digital Downconverter Decimation Range: 2x 65,536x in two stages of 2x 256x LO Tuning Freq. Resolution: bits, 0 ƒs LO SFDR: >120 db Phase Offset Resolution: bits, degrees FIR Filter: 18-bit user-programmable coefficients, 24-bit output Default Filter Set: 80% bandwidth, <0.3 db passband ripple, >100 db spband attenuation Phase Shift Coefficients: I & Q with -bit resolution Gain Coefficients: -bit resolution D/A Converters Type: Texas Instruments DAC5688 Input Data Rate: max. Output IF: DC 400 MHz max. Output Sampling Rate: 800 MHz max. with interpolation Resolution: bits Digital Interpolar Interpolation Range: 2x 65,536x in two stages of 2x 256x Total Interpolation Range D/A and digital combined: 2x 524,288x Front Panel Analog Signal Outputs Output Type: Transformer-coupled, front panel connecr Transformer Type: Coil Craft WBC4-6TLB Full Scale Output: +4 dbm in 50 ohms 3 db Passband: 300 khz 700 MHz Sample Clock Sources: On-board clock synthesizer generates two clocks: an clock and a D/A clock Clock Synthesizer Clock Source: Selectable on-board programmable VCXO ( MHz), front panel external clock or LVPECL timing bus Synchronization: VCXO can be locked an external MHz PLL system reference, typically 10 MHz Clock Dividers: External clock or VCXO can be divided by 1, 2, 4, 8 or for the clock External Clock Type: Front panel female SSMC connecr, sine wave, dbm, AC-coupled, 50 ohms, accepts MHz divider input clock or PLL system reference External Trigger Input Type: Front panel connecr Function: Programmable functions include: trigger, gate, sync and PPS Field Programmable Gate Array Standard: Xilinx Virtex-7 XC7VX330T-2 Option -076: Xilinx Virtex-7 XC7VX690T-2 Cusm I/O Parallel (Option -104): pairs of connections between the and a card-edge connecr for cusm I/O Optical (Option -110): 12x gigabit serial optical I/O with XC7VX690T, 4x with XC7VX330T Type: Size: Four banks, each Speed: 800 MHz (00 MHz DDR) PCI-Express Interface PCI Express Bus: Gen. 1, 2 or 3: x4 or x8; Environmental: Level L1 & L2 air-cooled Size: in. x in (111.2 mm x mm)

22 Model Features Supports the Xilinx Virtex-7 Complete development environment with Pentek s reference design Supports the Pentek Model 3312 FMC I/O Module Reference Design for the Xilinx VC707 Evaluation Kit Pentek offers the option -990 reference design with software and IP support for the Pentek Model 3312 when installed on the Xilinx VC707 Evaluation Kit board. The Virtex -7 VC707 Evaluation Kit is a platform using the Virtex-7 XC7VX485T-2FFG1761C. It includes basic components of hardware, design ols, IP, and preverified reference designs. When coupled with Pentek s option -990 reference design for the 3312, the user has a complete development environment for cusm applications. The industry-standard Mezzanine Connecrs (FMC) are directly compatible with the Ordering Information Reference Design for the Xilinx VC707 Evaluation Kit Please purchase the Xilinx VC707 Evaluation Kit your Xilinx authorized distribur: boards-and-kits/ek-v7-vc707-g.html The Xilinx Virtex -7 VC707 Evaluation Kit gives designers an easy starting point for evaluating and leveraging devices that deliver breakthrough performance, capacity, and power efficiency. Out of the box, this platform speeds time market for the full-range of Virtex-7 -based applications including advanced systems for wired and wireless communications, aerospace and defense. The highly flexible kit combines fully integrated hardware, software, and IP with preverified reference designs that maximize productivity and let designers immediately focus on their unique project requirements. The Flexor Model 3312 is a multichannel, high-speed data converter FMC module. It includes four, -bit s, two 800 MHz, -bit D/As, programmable clocking, and multiboard synchronization for support of larger high-channel-count systems.