UNIVERSITY OF TORONTO FACULTY OF APPLIED SCIENCE AND ENGINEERING. Final Examination, December 2017 DURATION: 2 and½ hours

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1 UNVERSTY OF TORONTO FACULTY OF APPLED SCENCE AND ENGNEERNG Final Examination, December 2017 DURATON: 2 and½ hours Third Year- Electrical and Computer Engineering ECE334H 1 F - Digital Electronics Calculator Type: 2 Exam Type: A Examiner - T. Kosteski nstructions: 1. Write your name and student number in the space provided. 2. Do not remove any pages from this examination booklet. 3. Write in pen or pencil. 4. Answer all questions in the space provide in this exam booklet. 5: Non-programmable calculators only. 6. Answer all questions and justify all your work for full marks. 7. The grade for each question is given in the square brackets [ ]. 8. A parameter sheet for transistors, layout design and a formula sheet are given on the last two pages of this booklet. Question Q Q2 Q3 Q4 Q5 Grade Last Name: First Name: Student#: Total (55) Page 1 of 13

2 ', Question 1 [10 marks total] Draw the transistor level_ schematic for the 1!3-yout given in Figure 1 and label the schematic with the same labels A, B, C, D, :Voo and GND. Use the next page for your s~hematic. ' Legend Metal 1 Metal 2 '' Contact. ~, Polysilicon.- l n-diffusion L.._: _... p'-diffusion r :- - 1, n-well GND A B C ' n Figure 1 space on th~ next page for this question Page 2 of 13.

3 Space for Question 1 \ Page 3 of 13

4 Question 2 [10 marks] Draw the CMOS implementation (i.e. using Pull-Up and Pull-Down) for the following function and size the transistors so that the effective rise and fall resistances are equal to a unit sized inverter (i.e. an inverter with all L = Lmin, W n = 211., and W p/w n = 2). Label the inputs and output. Y=AB+CD+E Page 4 of 13

5 Question 3 [10 marks] An RC network is shown in Figure 2. Calculate the Elmore delay from node X to node Y. The component values are: Rl = R2 = R5 = 0.1 n, R3 = 40 n, R4 = 0.2 n, R6 = R7 = 0.4 n, R8 = 400 n, Cl= C3 = C4 = C7 = C8 := 50 ff, C2 = 150 ff, C5 = 200 ff, C6 = 100 ff. Rl R4 R7,R8 Tei Tc4 Tc2 Tc3 - - Tes T C Figure 2 Page 5 of 13

6 Question 4 [15 marks total] PART A [5 marks] A circuit containing flip-flops and logic gates is given in Figure 3a below. The CLK frequency is 100MHz and the flip-flops are triggered on the positive rising edge. Assume that initially all logic values are zero. All signal transitions are assumed to be vertical. x DQ y CLK ~ Figure 3a a) f the flip-flops and logic gates are ideal (i.e. there are no delays), use Figure 3b to draw the timing diagram for the output, Y for the given CLK and input X signal. The spacing between the vertical lines represent 1 ns in time. $ R.,! ; (11-i i-++-t i t ~ -j--ii-t-l-+-;-+-!-t-1-l--;-+--;-;--+--t--i--!---!-l -t-t i.,.,.,. ' 7-,--..,- H : ' :ii,...ll +- --~-; 1 -H--H--i-~--i-!-H--i--i--H-H-HH-i-H,-+-i-H-H,_,_...,,_,--,.-,...,--;... j_ r-- -i- -+-,-- -, _j ""'."' -t--, <-t-<-< _... t-l-+-<..., --!--i-i-t-t-f--!-l t-<-1-,-1--+-i--h l ' '! ' y...,-, L..l... _j ~-~~~' LJ._J_J,.J.., "--l~.~~~~ '-~'~'~--~- --LL... ~ ~-~'~ ' ~'-- LL Figure 3b Page 6 of 13

7 b) [5 marks] f the flip-flops and logic gates are not ideal, use Figure 3c to draw the timing diagram for the output, Y for the given CLK and input X signal. The spacing between the vertical lines represent 1 ns in time. For each flip-flop, tsetup = 0.5 ns, thold = 1 ns, tccq = 0.1 ns, and tpcq = 2 ns. The inverter and the AND gates each have tpct = 1 ns. Figure 3a is redrawn below for convenience. x ,, DQ y Figure 3a.Eigure:jc Page 7 of 13

8 Question 4 Part B [5 marks] A flip-flop circuit with combinational logic is given in Figure 4. The flip-flops are triggered on the positive rising edge. The time characteristics for each flip-flop and combinational logic is given in Table 1 below. f the clock skew is 1 ns for each flip-flop, determine the following: a) [3 marks] The minimum clock period for this circuit. b) [2 marks] Determine if there any hold time violations. X D Q - Combination - D Q - Combination - D Q - Logic #1 Logic # > ~,... > y CLK Flip-Flop #1 Flip-Flop #2 Flip-Flop #3 Figure 4 Table 1: Flip-flop and combinational logic time characteristics. Element t 0 ca (ns) tcca (ns) tsetuo (ns) thold (ns) t 0 ct (ns) Flip-Flop # Flip-Flop # Flip-Flop # Combinational Logic #1 Combinational Logic #2 Additional space on next page Page 8 of 13

9 Additional space for Question 4 Part B Page 9 of 13

10 Question 5 [10 marks total] A SRAM cell is shown in Figure 5 below. Also listed are the parameters for the transistors (note: do not use the parameter sheet at the end ofthis exam for this question).. BL BL WL 1 M3 C=lOfF M6 M2 WL 1 M4 Jc=OfF VDD = 2.5 V all lengths are = 0.25 µm W 1 = 1.0 µm w3 = 0.5 µm W 4 =0.5µm 2 µncox = 120 µan 2 µpccix = 30 µan 2 C 0 x = 6 ff/ µm Figure 5 Vtn=-Vtp=0.4V a) [3 marks] f BL and BL are both precharged to Voo/2, calculate from first principles the peak voltage at VA during a Read operation given that the cell stored a "1" at VB. (Hint: during the Read, M3 will be in active and Ml will be in triode). Page 10 of 13

11 b) [3 marks] Calculate the Word Line capacitance for a single row if this SRAM cell is part of a 256 x 256 array. c) [4 marks] Design a chain of inverters to drive the word line capacitance that was calculated in part (b) and determine the transistor sizes required for each inverter. To size the inverters, start from the word line capacitance and work back towards the smallest inverter; where the smallest inverter has a minimum transistor width of 0.5µm. Use a fanout of 4 where possible> Page 11 of 13

12 Parameter Sheet Physical Constants: F q = 1.6x10 C, 0 = 8.854x--, 0,c = m 180nm (A= 90nm) Process parameters : NMOS PMOS Units Description Yoo V Supply voltage Lmtn (=2.ii.) nm Minimum channel length Vt V Threshold voltage with zero bulk-source voltage lln,'pcox µa/v2 Transistor current gain parameter MOSFETC apac1 nee,arame te rs: Cox 85 ff/µmz Gate capacitance per unit area Cgol 0.3 ff/µm Gate overlap capacitance per.unit width c, 1.0 ff/µm 2 Drain/source bulk junction capacitance per unit area C,sw 0.4 ff/µm Drain/source sidewall junction capacitance per unit perimeter Layout Design Rules Layer Rule Description Rule (in A) Active 2.1 Width Source/drain surround by well Substrate/well contact surround 3 bvwell 2.5 Spacing to active of opposite type 4 Poly 3.1 Width SpacinQ to poly over field oxide 4 3.2a Spacing to poly over active Gate extension beyond active Active extension beyond poly Spacing of poly to active 1 Contact 6.1 Width ( exact) 2x2 6.2b Overlap by colv or active Spacing to contact Spacing to gate 2 6.7b Spacing to active/poly for multiple 3 colv/active contacts Metal 7.3 Overlap of contact 1.. Page 12 of 13

13 Equation Sheet Constants: k = 1.38 x JK- 1, q = x C, Vr = kt/q = 26 m Vat 300 K Eo = x Fm Capacitance: Cox= Eoxltox, Cj = Cjo/(l+VRl~o)Mi, Cg= C 0 xwl, for Lmin: Cgu = CoxLmin, Cg= CguW, Ca= Cs= CauW NMOS: Pn = µncox(w/l), Vtn > 0, Vos> 0, triode: Vos::;; (Vos- Vtn), lo= Pn((Vos - Vtn)Vos - V 2 os/2) active: Vos ~ (V GS - V tn), o = 0.5 Pn(V Gs - Vtn) 2 Vtn = Vtno + y( Vss + ~s - ~) subthreshold: o= oo(vas-ytn)/nvr)(l - e-vosnt) PMOS: PP= µpcox(w/l), Vtp < 0, Vos< 0, triode: Vos~ (Vos - Vtp), o= Pp((Vos- Vtp)Vos- V 2 os/2) active: Vos::;; (Vos- Vtp), o= 0.5pp(Vos - Vtp) 2 CMOS nverter: Vrn = (Voo+ Vtp + Vtnr)/(l+r), r = (µn(w/l)n)/(w/l)p RC Delay est: tar= tar= l.2't, 't = ReqC, Reqn = 2.5/(µnCox(W/L)n(Voo - Vtn)), Reqp = 2.5/(µpCox(W/L)p(Voo + Vtp)), (Wp/Wn)opt = µn/µp Unit Delay est: tat2ltafl = (Cu/CLl)*((W/L)ni/(W/L)n2) Delay: 'tae1ay = 'tinv (CoutlCn), total delay= Nfonv, fj = CoutlCn Elmore Delay: 'ti ;:::: Lk (CkRik), distributed RC 't;:::: RC/2 Power Dissipation: Payn= afcl(voo)2, Pairectpath = ½ anooipeak(tr + tr), peak = 0.5Pn(Vrn - Vtn) 2 MTBF ~ (K1 et/rs)/(fofc1k) Page 13 of 13