FEC Architectural Considerations
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1 FEC Architectural Considerations P802.3bj Interim IEEE Atlanta November 2011 Mark Gustlin Cisco, John D Ambrosia Dell, Sudeep Bhoja - Broadcom
2 Contributors and Supporters Frank Chang Vitesse Roy Cideciyan IBM Chris Cole Finisar Jonathan King Finisar 2
3 Introduction This slide set will explore the architectural impact of FEC in the 802.3ba architecture if a proposal with FEC is selected The presentation should not be seen as an endorsement for any proposals that include FEC 3
4 Today s 100 Gb/s Architecture Below is shown the generic architecture of 802.3ba interfaces, as depicted in Clause 80 FEC (opt) PMA AN 1 Note 1: Conditional on type and solution chosen Note 2: FEC in this case is based on PCS Lanes (KR FEC) 4
5 Today s 100 Gb/s Architecture Many variations of this are possible and are shown in Annex 83C Note that the currently defined FEC is KR (Clause 74) based and operates on individual PCS Lanes, so 20 instances for 100 Gb/s PMA (20:10) CAUI PMA (10:4) AN 1 FEC (KR) PMA (20:10) AN 1 PMA (20:10) CAUI PMA (10:20) FEC (KR) PMA (20:10) AN 1 Note 1: Conditional on type and solution chosen 5
6 KR FEC Processing Below shows the processing for the KR FEC that is part of 802.3ba (everything is done per PCS lane, TX processing is shown): PCS Ln0 PCS Ln1 PCS Ln2 PCS Ln18 PCS Ln19 ooo 64b/65b trnscdng 64b/65b trnscdng 64b/65b trnscdng 64b/65b trnscdng 64b/65b trnscdng FEC Encode FEC Encode FEC Encode FEC Encode FEC Encode PCS Ln0 PCS Ln1 PCS Ln2 PCS Ln18 PCS Ln19 6
7 Low Latency FEC Investigations to Date Many different FEC options have been discussed so far within 802.3bj and the copper study group Most have looked at Reed Solomon codes in order to achieve good single bit and burst error correction capability Most have proposed striping FEC blocks across 4x25G lanes in order to achieve low latency (< 100ns), and re-use Alignment Markers for pre-fec decode alignment of the 4 lanes Would be 4x higher latency if you run FEC per 25G lane Investigated proposals range from 0% over-clocking to 9% A possible sweet spot for backplanes seems to be around 6% (optimum triple tradeoff point) Proposals for 64B/65B and 512B/513B transcoding options so far to reduce the over-clocking Architecturally where does this possible new Low Latency FEC fit? 7
8 Low Latency FEC Architecture Below shows the processing for the FEC options that have been proposed so far (TX side processing): PCS Ln0 PCS Ln1 PCS Ln2 PCS Ln18 PCS Ln19 ooo AM SM AM SM AM SM AM SM AM SM Alignment Function No PCS lanes here! 64b/65b or 512b/513b transcoding FEC encoding Word distribution to 4 lanes FEC lane 0 FEC lane 1 FEC lane 2 FEC lane 3 8
9 Low Latency FEC Architecture Below shows the processing for the FEC options that have been proposed so far (RX side processing): FEC lane 0 FEC lane 1 FEC lane 2 FEC lane 3 Alignment Function FEC decoding/correction 64b/66b transcoding Word distribution to 20 lanes PCS Ln0 PCS Ln1 PCS Ln2 ooo PCS Ln18 PCS Ln19 9
10 Low Latency FEC Architecture The figures below show possible striped (and therefore low latency) FEC architectures FEC (LL) PMA (20:10) PMA (20:10) PMA (20:4) PMA (4:4) CAUI CAUI CAUI-4 PMA (10:20) PMA (10:20) PMA (4:20) AN 1 FEC (LL) FEC (LL) FEC (LL) PMA (4:4) PMA (4:4) PMA (4:4) CAUI-4 CAUI-4 AN 1 PMA (4:4) PMA (4:4) AN 1 AN 1 Note 1: Conditional on type and solution chosen Note: LL = Low Latency CAUI-4 assumed new 25G+ interface, might need multiple rates to support FEC 10
11 Low Latency FEC Architecture The figure below shows an incorrect architecture, once the Low Latency FEC is inserted, the number of lanes cannot change! At least not with the standard 802.3ba PMAs Exploring the possibility of supporting 4, 2 and 1 lane options. But we need to look at burst error behavior. PMA (20:10) CAUI PMA (10:20) FEC (LL) PMA (4:10) CAUI PMA (10:4) 11
12 FEC within the PCS Layer Why not put FEC into the PCS layer and allow the normal PMA muxing that we do for 802.3ba? See gustlin_02_0911, doing this would cause any burst errors to be split up into multiple individual errors and weaken most FEC codes 12
13 LL FEC With MLG The architecture can support MLG payloads 10GE 0 10GE 1 10GE 2 10GE 8 10GE 9 ooo MLG Processing MLG Ln0 MLG Ln1 MLG Ln2 MLG Ln18 MLG Ln19 ooo AM SM AM SM AM SM AM SM AM SM Alignment/Transcoding/FEC encoding Word distribution to 4 lanes FEC lane 0 FEC lane 1 FEC lane 2 FEC lane 3 13
14 Summary The Low Latency FEC codes that have been discussed so far within 802.3bj can fit cleanly into the architecture However, the LL FEC codes are point to point codes across 4 lanes, and after the FEC code is inserted, normal 802.3ba bit manipulation cannot take place The FEC architecture as presented is flexible and can be modified to support various solutions (i.e. transcoding, FEC gain, lane counts or MLG) 14
15 Thanks! 15
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