Data Sheet. AMMP GHz x2 Frequency Multiplier. Features. Description. Applications. Functional Block Diagram.

Transcription

1 AMMP GHz x2 Frequency Multiplier Data Sheet Description The AMMP-61 is an easy-to-use surface mounted packaged integrated frequency multiplier (x2) that operates from to 24 GHz output frequency. It has integrated amplification, matching, harmonic suppression, and bias networks. dbc min. of harmonic rejection is delivered. The input/output are matched to and fully DC blocked. This MMIC is a cost effective alternative to hybrid (discrete-fet) amplifiers that require complex tuning and assembly process. Functional Block Diagram IN 8 Vd1 1 X2 Vg Vd OUT 4 Pin Function 1 Vd1 2 Vg 3 Vd2 4 RF_OUT RF_IN Features x mm surface mount package Wide frequency operation: -24 GHz (Output) Input and Output Match 4 C to +8 C operation Output Power of +21. dbm Typical Fo, 3xFo, 4Fo Rejection: dbc min Applications Microwave Radio Systems VSAT Satellite Up/Down Link Test Equipment Package Diagram GND TOP VIEW Attention: Observe Precautions for handling electrostatic sensitive devices. ESD Machine Model: 4V ESD Human Body Model: V Refer to Avago Application Note A4R: Electrostatic Discharge Damage and Control.

2 ELECTRICAL SPECIFICATIONS Table 1. Absolute Maximum Ratings Parameter Specifications Description Min. Max. Unit Drain Voltage Vd1 V Vd2 6 V Gate Voltage Vg -2. V CW Input Power dbm MSL MSL2 Channel Temperature C Storage Temperature -6 C Comments Table 2. Recommended Operating Range Parameter Specifications Description Pin Min. Typical Max. Unit Comments Drain Voltage Vd V Vd2.. V Gate Voltage Vg V Frequency range Input 12 GHz Output 24 GHz Input Power dbm Quiescent Current I dsq1 ma Vd1 = 3. V I dsq2 1 ma Vd2 = V Thermal Resistance, ch-b 26.4 C/W Case Temperature C ESD Human Body Model V Machine Model 4 V 2

3 Table 3. RF Electrical Characteristics All data measured on a Rogers 43 demo board at Vd1 = 3. V, Vd2 = V, Vg = -1.2 V, T A = C, Pin = dbm and at all ports, unless otherwise specified. Parameter Output Power Fundamental Suppression Freq = GHz Freq = 17 GHz Freq = 24 GHz Freq = GHz Freq = 8. GHz Freq = 12 GHz 3 rd Harmonic Suppression Freq = GHz Freq =. GHz Freq = 36 GHz Performance Min. Typical Max. Unit 22.8 dbm dbc dbc Comments f in =, 8., 12 GHz f in =, 8., 12 GHz 4 th Harmonic Suppression dbc Input Return Loss -12 db Output Return Loss - db Drain Current Id1 1 ma P out = 21 dbm Id2 14 ma Gate Current (Ig) - A Note: 1. Output Power, Fundamental Suppression and 3 rd Harmonic Suppression measurement accuracy is subjected to the tolerance of ±. dbm, ± 1 dbc & ± 1 dbc respectively. Product Consistency Distribution Charts at GHz, 8. GHz and 12 GHz, Vd1 = 3. V, Vd2 = V, Vg = -1.2 V (Sample size of 2,8 pieces) GHz, Mean = 22.8 dbm, = dbm GHz, Mean = 22.1 dbm, = dbm GHz, Mean = 21. dbm, = dbm 3

4 Product Consistency Distribution Charts at GHz, 8. GHz and 12 GHz, Vd1 = 3. V, Vd2 = V, Vg = -1.2 V (Sample size of 2,8 pieces) (Continued) GHz, Mean = 21 dbc, = dbc 8. GHz, Mean =.9 dbc, = dbc 12 GHz, Mean = 29. dbc, = dbc GHz, Mean = 18.3 dbc, = dbc GHz, Mean = 27.2 dbc, = dbc 36 GHz, Mean =.2 dbc, = dbc 4

5 Selected Performance Plots All data measured on a Rogers 43 demo board at Vd1 = 3. V, Vd2 = V, Vg = -1.2 V, T A = C, Pin = dbm and at all ports, unless otherwise specified. Output Power (dbm) H 2H 3H 4H Figure 1. Output Power vs. Output Pin = dbm - - Pin = -6 dbm Pin = -4 dbm Pin = -2 dbm Pin = dbm Pin = +2 dbm Pin = +4 dbm Figure 2. Output Power [2H] vs Output Frequency Over Pin C -4 C 8 C Pin = -6 dbm Figure 3. Output Power vs. Output Pin = -6 dbm over Temperature C -4 C 8 C Pin = dbm Figure 4. Output Power vs. Output Pin = dbm over Temperature C -4 C 8 C Pin = +2 dbm C -4 C 8 C Pin = +4 dbm Figure. Output Power vs. Output Pin = +2 dbm over Temperature Figure 6. Output Power vs. Output Pin = +4 dbm over Temperature

6 I/P & O/P Return Loss (db) Figure 7. Input and Output Return Loss at Pin = dbm S11 S Frequency (GHz) Total Drain Current [Id] (ma) Figure 8. Total Drain Current vs. Pin Vg = -1.4 V, Vd2 = V Vg = -1.2 V, Vd2 = V Pin = -6 dbm Pin = dbm Pin = +4 dbm Figure 9. Fundamental [1H] Suppression vs Output Frequency at Variable Pin Suppression [3H] (dbc) Pin = -6 dbm Pin = dbm Pin = +4 dbm Figure. 3 rd Harmonic [3H] Suppression vs Output Frequency at Variable Pin Suppression [4H] (dbc) 4 Pin = -6 dbm Pin = dbm Pin = +4 dbm Figure th Harmonic [4H] Suppression vs Output Frequency at Variable Pin Figure 12. Output Power [2H] vs Pin at variable Output Frequency GHz [2H] 14 GHz [2H] 18 GHz [2H] 22 GHz [2H] 26 GHz [2H]

7 Fout = GHz Figure 13. Output Power [2H] vs Input Fout = GHz Vg = -1.4 V, Vd2 = V Vg = -1.2 V, Vd2 = V Fout = GHz Vg = -1.4 V, Vd2 = V Vg = -1.2 V, Vd2 = V Figure 14. Fundamental Suppression [1H] vs Input Fout = GHz Fout = 14 GHz Figure. Output Power [2H] vs Input Fout = 14 GHz Vg = -1.4 V, Vd2 = V Vg = -1.2 V, Vd2 = V 4 3 Fout = 14 GHz Vg = -1.4 V, Vd2 = V Vg = -1.2 V, Vd2 = V Figure 16. Fundamental Suppression [1H] vs Input Fout = 14 GHz Fout = 18 GHz Figure 17. Output Power [2H] vs Input Fout = 18 GHz Vg = -1.4 V, Vd2 = V Vg = -1.2 V, Vd2 = V 4 3 Fout = 18 GHz Vg = -1.4 V, Vd2 = V Vg = -1.2 V, Vd2 = V Figure 18. Fundamental Suppression [1H] vs Input Fout = 18 GHz 7

8 Fout = 22 GHz Figure 19. Output Power [2H] vs Input Fout = 22 GHz Vg = -1.4 V, Vd2 = V Vg = -1.2 V, Vd2 = V Fout = 22 GHz Vg = -1.4 V, Vd2 = V Vg = -1.2 V, Vd2 = V Figure. Fundamental Suppression [1H] vs Input Fout = 22 GHz Fout = 26 GHz Vg = -1.4 V, Vd2 = V Vg = -1.2 V, Vd2 = V Fout = 26 GHz Vg = -1.4 V, Vd2 = V Vg = -1.2 V, Vd2 = V Figure 21. Output Power [2H] vs Input Fout = 26 GHz Figure 22. Fundamental Suppression [1H] vs Input Fout = 26 GHz Evaluation Board Description and Application Circuit for AMMP-61 GND GND Vd1 Vg Vd2 4.7 F 4.7 F.1 F Vd1 1.1 F.1 F Vg Vd2 2 3 IN AMMP 61 YWWDNN OUT RFin IN 8 X 2 OUT 4 RFout Table 4. Pin Description Pin # Function Biasing Comment GND GND 1 Vd1 3. V ma (measure current) 2 Vg -1.2 V A (measure current) 3 Vd2. V 1 ma (measure current) GND GND Recommended quiescent DC bias condition for optimum power and linearity performance is Vd1 = 3. V, Vd2 = V and Vg = -1.2 V. The gate voltage, Vg, biases the doubling circuit only; it does not adjust the amplifier bias current. Minor improvements in the AMMP-61 s output power and fundamental suppression can be obtained by adjusting Vg from -1. V to -1. V.

9 Package, Tape & Reel, and Ordering Information Please refer to Avago Technologies Application Note 21, AMxP-xxxx production Assembly Process (Land Pattern B). Part Number Ordering Information Part Number Devices per Container Container AMMP-61-BLKG Antistatic bag AMMP-61-TR1G 7 reel AMMP-61-TR2G 7 reel For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright Avago Technologies. All rights reserved. AV2-38EN - March 23, 16

10 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Avago Technologies: AMMP-61-TR1G AMMP-61-BLKG AMMP-61-TR2G