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1 I E E E Circuits and Systems Volume 10, Number 1, March/April 1999 ISSN AN OBJECT-ORIENTED APPROACH TO A VISUAL DATABASE MORPHOSYS: A RECONFIGURABLE COMPUTING CHIP PAGE 6. S O C I E T Y N E W S L E T T E R by Taehyung Wang and Phillip C.-Y. Sheu Introduction Visualization can be applied to almost all computer-based applications such as medical education, scientific data, virtual reality, simulation, and so forth. Research in visual databases addresses the problem of retrieving, updating, and displaying a 3-D static or dynamic world which consists of a large number of objects stored in a centralized or distributed database. In addition, it is desirable that a visual database can allow the user to access a large, dynamic visual world interactively with intelligent queries over the Internet. In traditional computer graphics, the major concern is to display a scene accurately without the consideration of secondary storage; and the existing spatial database systems have not considered the visual and dynamic aspects of graphical objects. Because of the rising demands for visualizing a large number of objects, a visual database needs to consider the following requirements: (1) a world consists of a large number of objects, and thus objects have to be stored in one or several databases; (2) both the camera and the objects are allowed to move; and (3) rapid search based on visual properties, such as shape, of an object is necessary to effectively locate the object. Object-Oriented Algorithms for Computer Graphics While conventional approaches in computer graphics, such as the binary space partition (BSP) tree algorithm [1 2] and its extensions [3 6], deal with each polygon of an object, an object-oriented ap-... continued on Page 4 Places es P DECEMBER Pla ty Places Places s SEPTEMBER ociety Plac y Places Places Peo y Places JUNE Places Artic rticles Places Societ Places S MARCH ople Places Article P cles Places Places THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, INC. Places Societ

2 IEEE Circuits and Systems Newsletter Newsletter Homepage Editor Michael K. Sain Electrical Engineering Department University of Notre Dame Notre Dame, IN, USA Phone: (219) Fax: (219) IEEE Publishing Services Robert Smrek Production Manager IEEE Service Center 445 Hoes Lane P.O. Box 1331 Piscataway, NJ , USA Phone: (732) Months of Publication March June September December Newsletter Deadlines for the CAS Newsletter issues must be received by the Editor by the following dates: Issue Due Date March February 1 June May 1 September August 1 December November IEEE. Information contained in this newsletter may be copied without permission provided that the copies are not made or distributed for direct commercial advantage, and the title of the publication and its date appear. IEEE Circuits and Systems Newsletter is published quarterly by the Circuits and Systems of the Institute of Electrical and Electronics Engineers, Inc., Three Park Avenue, New York, NY Four dollars per member per year (included in fee) for each member of the Circuits and Systems. Printed in U.S.A. Periodicals Postage Paid at New York, NY, and at additional mailing offices. Postmaster: Send address changes to IEEE Circuits and Systems Newsletter, Attn: Change of Address, IEEE, 445 Hoes Lane, Piscataway, NJ Elsewhere in the Issue Nominate Someone Special for a CAS 50th Anniversary Award, page 21 Get Involved with a CAS Technical Committee, page 21 Farewell Salute to Carl F. Kurth, page 26 Avoid a CAS Y2K Problem Nomination Time for Next Officers, page 31 Wang/Sheu: Object-Oriented Databases... 1 Garth/Huang/Werner: Crosstalk Mitigation... 3 Lee, et al.: Reconfigurable Chip... 6 Newsletter to Magazine Update VLSI Transactions Special Section CFP Board of Governors Report CAS Awards Announced Constitution and Bylaws More 1998 CAS Best Paper Awards th Anniversary Awards Nominations CAS TCs Participation Invitation Region 8 News CAS Officer Nominations Due The Adventures of the Umble Ohm CAS 1998 IEEE Fellow Profiles Carl F. Kurth Obituary Places Calls for Papers ISCAS VCIP Coming Conferences CAS-COM Workshop MWSCAS ICECS ICCAD ECCTD SCS rd Mixed Mode Workshop MSICD ISLPED NDES

3 CROSSTALK MITIGATION FOR XDSL CHANNELS by Lee M. Garth, Gang Huang, and Jean-Jacques Werner High-speed bandwidthefficient transceivers have been designed for the existing copper telephone loop plant. Unlike conventional voice-band modems, these transceivers use the full available bandwidth of the copper cables. These digital subscriber line (xdsl) systems have been designed to mitigate bridged-tap-caused spectral nulls, impulse noise, and other impairments [1]. The channel impairment that remains one of the biggest obstacles to achieving even higher bandwidth efficiency and data transmission rates is crosstalk. The telephone loop plant typically consists of twisted pairs of copper wires bundled together in large cables. Figures 1 and 2 show cross sections of common cables in the United States and Europe. Because the different electrical signals, corresponding to different users and services (voice, ISDN, etc.), are transmitted V S (t) X N (t) NEXT Pair i Cable Pair j FEXT Figure 3. Two types of wireline crosstalk. down long copper wires in parallel, both capacitive and inductive couplings are induced between the pairs of wires, detrimentally affecting the coexisting signals. 1 The superposition of these couplings, known as crosstalk, comes in two forms as shown in Fig. 3. Near-end crosstalk (NEXT) is defined to be the induced interference at a receiver due to other transmitters located at the same end of the cable as the receiver. Far-end crosstalk (FEXT) is defined to be the induced interference at a receiver due to transmitters other than the correct transmitter located at the opposite end of the cable from the receiver. Spectral allocations of the signals propagating in both directions govern whether NEXT or FEXT is the limiting impairment. For example, for HDSL, which uses the same frequency band for both directions, self-next is the major impairment, whereas for VDSL, which uses different frequency bands for each direction, self- FEXT is the major impairment. 2 Figures 4 and 5, pages 8 9, show measurements made in our laboratory of pair-wise self- NEXT and self-fext losses for a BKMA cable (Fig. 1) [2]. Smooth curves corresponding to various empirically-derived models are shown as well. In deriving operating characteristics of new wireline transceivers, assuming a large number of interferers, the total crosstalk interference has been typically modeled as additive X F (t) Figure 1. Cross section of typical North American cable. Figure 2. Cross section of typical European cable. 1 To reduce the strength of these couplings, modern cables contain pairs of wires twisted in a highly controlled manner to ensure that adjacent pairs see opposite polarity signals. Unfortunately, the twistings of these pairs are not perfect and are disturbed by bends or stretches in the cable, leaving residual couplings. 2 The terms self -NEXT and self -FEXT refer to the scenario when all the twisted pairs in a particular cable are providing the same type of service (e.g., all the wires are transmitting VDSL).... continued on Page 8 3

4 4 Figure 1. Top view of a scene and the corresponding BSP tree. Figure 2. Top view of a scene and the corresponding object-oriented BSP tree. les Artic les Articl es Article icles Arti A An Object-Oriented Approach to a Visual Database* continued from front cover proach deals with objects themselves. In the object-oriented BSP tree algorithm [7], the internal nodes of a tree are partitioning planes used to partition a space and to decide the relative location of each object. Objects are attached to the tree as leaves. When an object is split by a partitioning plane, two new objects are produced: one object lies in the front and the other lies in the back of the plane. Intuitively, compared with the original BSP tree algorithm, the size of a BSP tree can be reduced with the object-oriented approach. As a simple example, suppose there are three cubes as shown in Fig. 1. According to the original BSP tree algorithm, there are 18 nodes in the BSP tree inasmuch as each polygon must be a node of the tree. With the object-oriented BSP algorithm, any polygon can be selected as the partitioning plane so that the objects in the scene can be divided into two sets: those in the front of the plane and those in the back of the plane. * Some work reported in this article is supported in part by National Institutes of Health (NIH) under grant number AG the cost of managing a tree A A A In this example, if p1 is first selected as the partitioning plane whose direction is shown in Fig. 2, then object o1 is in the front of p1 and objects o2 and o3 are in the back of p1. We can separate object o2 and o3 using another partitioning plane p2. Consequently, only 5 nodes are required for the object-oriented BSP tree as shown in Fig. 2. When a scene is displayed, two procedures are generally needed. One is to build a tree and the other is to draw a tree. The object-oriented BSP tree algorithm not only can save the time for building a tree and drawing a tree, but also can simplify the cost of managing a tree in case any object moves. Figure 3 shows a performance comparison between the objectoriented BSP (OOBSP) algorithm and the original BSP tree algorithm. A cube is employed as an object. The polygons of an object based on a serial order are selected as the partitioning planes in the BSP tree algorithms. As shown in Fig. 3 the performance of the OOBSP algorithm is better than that of the original BSP algorithm because of two factors: object-orientation and minimum splitting. Hierarchical Structures With the original BSP algorithm, management of a BSP tree could be inefficient for dynamic scenes because any modification may result in a total reconstruction of the tree, which is cost ex- Figure 3. Performance of two algorithms for displaying a scene. pensive. To reduce the cost, we can divide the object space into a set of regions so that in each region all viewpoints have the same object ordering. Therefore, if we store each region together with its associated ordering, the objects can be displayed easily for a given viewpoint. Such regions are found based on a structure called region tree, which is a binary tree whose nodes correspond to a direction of a partition plane and whose leaves correspond to the resulting subspaces. Based on each region and its corresponding OOBSP tree all the objects are stored into an R + -tree [8]. When we display a scene we traverse an R + -tree and retrieve the objects from the farthest to the closest from a given viewpoint. Using the

5 query language is transparent les Artic ticles Art les Article icles Arti A les Articl A A les Article ticles Art packing algorithm [9] we can build an R + - tree with minimum coverage. After building the tree, the OOBSP tree corresponding to each node can be generated. Note that the OOBSP tree of a leaf node handles real objects. On the other hand, the OOBSP tree of an internal node handles rectangles. Given the position of the camera, its view volume can be determined, and the view volume can be considered as a search window. The ordering of search in a node can be obtained using the corresponding OOBSP tree at the given viewpoint. Figures 4 and 5 show one example. Given the viewpoint, the OOBSP tree of each entry gives the object ordering. For example, given the viewpoint, the ordering of entries at the root node is 5, 4, 3, 2, and 1. Assume that entries 3 and 1 overlap with the view volume. The child nodes of entry 3 and entry 1 which are overlapped with the view volume are 18, 19, and 6 respectively as shown in Fig. 4. Suppose that the order between entry 18 and entry 19 at the viewpoint is 19 and 18. In the same manner the objects belonging to entry 19 can be ordered by the corresponding OOBSP tree, for instance, o70, o69, o68, o67, and o66. The object ordering of entry 18 and entry 6 is o65, o64, o63, o62, o61 and o5, o4, o3, o2, o1 respectively. The final object ordering for Figure 4. The scene which is decomposed into 5 regions. the view volume is as follows: o70, o69, o68, o67, o66, o65, o64, o63, o62, o61, o5, o4, o3, o2, and o1. In the display stage, clipping is needed after the objects are projected from 3-D to 2-D. Object Relational Database Due to the many problems associated with relational databases [10], an objectrelational database can be used to support the various graphic operations associated with the new methodology. Queries in the database are composed visually so that the query language is transparent to the user and even novice users can access the database easily. Once a query is composed, it is executed and the results are browsed in the Visual I/O Area. The user can visually specify a particular part of the result as the context of search for the next query; the initial context of search is, of course, the entire database. To cope with situations involving the creation of an object (i.e., an object that is not pre-stored in the database) so that it can be referenced in a query during a search (called Constructive Search), the database allows a new object to be created. Possible features applicable to the object (e.g., color, texture, size, and shape) are then displayed for selection. Once a feature is selected, a set of tools provided by the system is displayed. With an appropriate tool, we can adjust various features and/or create various building blocks. Features or building blocks are then put together in an object construction process. Summary We have discussed use of the object-oriented concept to solve various problems in... continued on Page 10 o1 o2 o3 o4 o o61 o62 o63 o64 o65 o66 o67 o68 o69 o Figure 5. The R + -tree for the scene. 5

6 MORPHOSYS A RECONFIGURABLE COMPUTING CHIP 6 Figure 1. MorphoSys system architecture by Ming-hau Lee, Guangming Lu, Hartej Singh, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M.C. Filho, and Vladimir Castro Alves In this research effort, we propose MorphoSys, as an implementation of a novel model for reconfigurable computing systems. This design model involves having a reconfigurable SIMD component on the same die with a powerful generalpurpose RISC processor, and a high bandwidth memory interface. Figure 1 shows the MorphoSys architecture. It is composed of an array of reconfigurable cells (RC array) with its configuration data memory (Context Memory), a control processor (Tiny RISC), a data buffer (Frame Buffer) and a DMA controller. The main component of MorphoSys is the 8 x 8 RC (Reconfigurable Cell) array, shown in Fig. 2. Each RC as illustrated in Fig. 3 has an ALU-multiplier and a register file and is configured through a 32-bit context word. The context words for the RC array are stored in the Context Memory. The RC architecture is defined to make the system versatile enough for the class of applications (DSP, video compression, and image processing) we are investigating while keeping the best speed/ area tradeoff. The RC array follows the SIMD model of computation. All the RCs in the same row/column share the same configuration word; however, each RC operates on different data. The configuration word specifies an instruction opcode for the RC and provides control signals for the multiplexers and output bus. The Context Memory can store up to 32 planes of configuration. Users have the option of broadcasting contexts across rows or columns. MorphoSys supports

7 Figure 4. MorphoSys M1 chip layout. dynamic reconfiguration. New context words may be loaded into the non-active parts of the Context Memory without interfering with RC array operation. MorphoSys has two sets of Frame Buffer, which is analogous to a data cache. It makes the memory accesses transparent to the RC array by alternately using the two sets so that the computation and the data load and store can be overlapped. The TinyRISC is the control processor of MorphoSys. Several new instructions are introduced to control the MorphoSys operation. They establish the communication between the general RISC processor, DMAC, Frame Buffer, Context Memory and RC array. The DMAC controller controls the data load and store of the Frame Buffer and the context load of the Context Memory through the instructions of TinyRISC. Both custom design and standard cell design are employed for the MorphoSys implementation. The long critical path of Figure 2. 8 x 8 Reconfigurable cell (RC) array. the RC and the dense interconnection network of the RC array make it almost impossible for the design automation tools to synthesize properly the design. That leaves us no choice but to custom design the whole RC array and its interconnection network even though they constitute almost 90% of the MorphoSys M1 chip. The Reconfigurable Cell supports the MAC (multiply/accumulate) and shift in one clock cycle (10ns), which is the critical path of the design. The multiplier can be disabled if the operation doesn t involve multiplication. This feature can reduce the power consumption of MorphoSys tremendously for most of the applications. SPICE simulation is carried out for the performance study of the RC. The maximum possible load of the RC is computed and replaced by an equivalent capacitance in the SPICE netlist for the purpose of more accurate timing analysis. The critical path operation time of the RC is 9.5 ns, and each RC consumes 200 mw at 25 o C, 100MHz in the worst case. Figure 4 shows the layout picture of the MorphoSys M1 chip. We developed a VHDL model for MorphoSys and mapped several applications to it successfully. The simulation results have validated this architectural model through impressive performance for several of... continued on Page 20 Figure 3. Reconfigurable cell architecture. Ming-hau Lee Guangming Lu Hartej Singh Nader Bagherzadeh Fadi J. Kurdahi Eliseu M. C. Filho Vladimir Castro Alves 7

8 Lee M. Garth Gang Huang Jean-Jacques Werner distorted by different transfer functions Ar les Artic les Articl es Article Crosstalk Mitigation... continued from Page 3 icles Arti A A A Gaussian noise with a power spectral density similar to the smooth curves in Figs. 4 and 5 [3]. Such a model, however, ignores the known structure of the interference. For the self-next and self-fext cases, the interference is the superposition of multiple signals of the same type distorted by different transfer functions depending on the corresponding twisted pairs within the particular cable. Figure 6 illustrates this superposition for two NEXT interferers. In [4, 5], researchers have pointed out the cyclostationary nature of crosstalk interferers. Many crosstalk equalization techniques have been proposed which make implicit use of the cyclostationarity [6 13]. Unfortunately, these techniques require that the various signals have 100% excess bandwidth per crosstalk interferer. In [14], alternate adaptive equalizers have been proposed which make explicit use of the cyclostationarity of the interfering signals, yielding performance gains in certain scenarios. For the special case when the input data sequences of the various transmitters are known at the central office, NEXT cancellers have been proposed [12, 15], similar to data-driven echo cancellers. An alternative approach to crosstalk mitigation is to design the various signals entering the cable to minimize the effects of crosstalk while maximizing the channel capacity [16 18]. Finally, for many years, researchers and system designers working on multiple access and multipath interference in wireless systems have adopted a more accurate multiuser channel model. They have modeled the received signal as the superposition of similar signals, designing receivers to take advantage of this structure and leading to remarkable system performance gains [19]. Systems have been proposed using training sequences to start up the receiver, as well as blind techniques taking advantage of, for example, a CDMA signal structure [20, 21]. In wireline applications such as xdsl, only preliminary work has been done in applying multiuser detection techniques [22, 23]. The future application of these techniques holds great promise. References [1] T. Starr, J. M. Cioffi, and P. J. Silverman, Understanding Digital Subscriber Line Technology. Upper Saddle River, NJ: Prentice-Hall, [2] G. Huang and J.-J. Werner, Cable Characteristics, ANSI Standards Contribution T1E1.4/ , May 12 16, See < > for further information. [3] K. J. Kerpez, Near-End Crosstalk Is Almost Gaussian, IEEE Transactions on Communications, vol. 41, pp , January [4] J. C. Campbell, A. J. Gibbs, and B. M. Smith, The Cyclostationary Nature of Crosstalk Interference from Digital Signals in Multipair Cable Part I: Fundamentals, IEEE Transactions on Communications, vol. 31, pp. 629 Figure 4. Measured pair-to-pair NEXT losses of BKMA cable. NEXT Loss (db) Frequency (MHz) 8

9 depending on corresponding twisted pairs les Artic les Articl es Article icles Arti A A A es Article ticles Ar ticles 637, May [5] J. C. Campbell, A. J. Gibbs, and B. M. Smith, The Cyclostationary Nature of Crosstalk Interference from Digital Signals in Multipair Cable Part II: Applications and Further Results, IEEE Transactions on Communications, vol. 31, pp , May [6] E. Biglieri, M. Elia, and L. Lopresti, The Optimal Linear Receiving Filter for Digital Transmission over Nonlinear Channels, IEEE Transactions on Information Theory, vol. 35, pp , May [7] B. R. Petersen and D. D. Falconer, Minimum Mean Square Equalization in Cyclostationary and Stationary Interference Analysis and Subscriber Line Calculations, IEEE Journal on Selected Areas in Communications,vol.9, pp , August [8] M. Abdulrahman and D. D. Falconer, Cyclostationary Crosstalk Suppression by Decision Feedback Equalization on Digital Subscriber Loops, IEEE Journal on Selected Areas in Communications, vol. 10, pp , April [9] A. Duel-Hallen, Equalizers for Multiple Input/Multiple Output Channels and PAM Systems with Cyclo-Stationary Input Sequences, IEEE Journal on Selected Areas in Communications, vol. 10, pp , April [10] M. L. Honig, P. Crespo, and K. Steiglitz, Suppression of Near- and Far-End Crosstalk by Linear Pre- and Post-Filtering, IEEE Journal on Selected Areas in Communications, vol. 10, pp , April [11] G.-H. Im, D. D. Harman, G. Huang, A. V. Mandzik, M.-H. Nguyen, and J.-J. Werner, Mb/s 16-CAP ATM LAN Standard, IEEE Journal on Selected Areas in Communications, vol. 13, pp , May [12] G.-H. Im and J.-J. Werner, Bandwidth- Efficient Digital Transmission over Unshielded Twisted-Pair Wiring, IEEE Journal on Selected Areas in Communications, vol. 13, pp , December [13] D. Schmucking, M. Schenk, and A. Worner, Crosstalk Cancellation for Hybrid Fiber Twisted-Pair Systems, Proceedings IEEE Global Telecommunications Conference, (London), November 18 22, NEXT #2 CABLE NEXT #1 RECEIVER TRANSMITTER TRANSMITTER Figure 6. System level NEXT representation. [14] W. A. Gardner, Ed., Cyclostationarity in Communications and Signal Processing. New York: IEEE Press, [15] G.-H. Im and N. R. Shanbhag, A Pipelined Adaptive NEXT Canceller, IEEE Transactions on Signal Processing, vol. 46, pp , August [16] G. D. Golden, J. E. Mazo, and J. Salz, Transmitter Design for Data Transmission in the Presence of a Data-Like Interferer, IEEE Transactions on Communications, vol. 43, pp , February/March/April [17] P. Mandarini, R. Cusani, E. Baccarelli, and S. Galli, Combined Optimization of Transmitting and Receiving Filters for Crosstalk Suppression on Twisted-Pair Wirings, Proceed-... references and biographies continued on back cover SAMPLER DATA EQUALIZER DECISION SNR FSLE OR DFE i SNR 0 DEVICE SAME TRANSCEIVER EL-FEXT Loss (db) Frequency (MHz) Figure 5. Measured pair-to-pair equal-level FEXT losses of 600 BKMA cable. 9

10 10 les Artic Phillip C.-Y. Sheu Taehyung Wang les Articl es Article s Article A A An Object-Oriented Database continued from Page 5 moving in a virtual world Arcomputer graphics. Instead of using a polygon as the basic unit, an object which consists of a set of polygons is employed as a basic unit so that we can reduce the cost of building, traversing, and managing a BSP tree. In addition, an object-oriented approach is more suitable to dynamic scenes. We have also discussed how to store OOBSP trees in a database. An R + - tree, which is a variant of an R-tree, is employed to store OOBSP trees. Moving an object in a virtual world requires the modification of an R + -tree and an OOBSP tree. Basically, as the size of a tree becomes larger the cost of modification is higher. To minimize the cost we have described a hierarchical structure to store objects. In other words, instead of reconstructing a tree, each node of an R + -tree includes the corresponding OOBSP tree so that only the related OOBSP trees are modified. Finally, we have discussed how to use an object relational database to facilitate the above operations and to support declarative retrieval of visual objects. References [1] H. Fuchs, Z. M. Kedem, and B. F. Naylor, On Visible Surface Generation by a Priori Tree Structure, Proceedings SIGGRAPH 80, Computer Graphics, vol. 14, no. 3, pp , July [2] H. Fuchs, G. D. Abram, and E. D. Grant, Near Real-Time Shaded Display of Rigid Objects, Proceedings SIGGRAPH 83, Computer Graphics, vol. 17, no. 3, pp , July [3] N. Chin and S. Feiner, Near Real-Time Shadow Generation Using BSP Trees, Proceedings SIGGRAPH 89, Computer Graphics, vol. 23, no. 3, pp , July [4] Y. Chrysanthou and M. Slater, Computing Dynamic Changes to BSP Trees, Eurographics 92, A. Kilgour and L. Kjelldahl (Eds.), Blackwell Publishers, vol. 11, no. 3, pp. C311 C332, [5] W. Thibault and B. Naylor, Set Operations on Polyhedra Using Binary Space Partitioning Trees, Proceedings SIGGRAPH 87, Computer Graphics, vol. 21, no. 4, pp , July [6] E. Torres, Optimization of the Binary Space Partition Algorithm (BSP) for the Visualization of Dynamic Scenes, Eurographics 90, C. E. Vandoni and D. A. Duce (Eds.), Elsevier icles Arti es Arcles Artic s Ar Science Publishers B.V. North-Holland, pp , [7] T. Wang, An Object Relational Approach to Visual Databases, Ph.D. Dissertation, University of California, [8] T. Sellis, N. Roussopoulos, and C. Faloutsos, The R + -Tree: A Dynamic Index for Multi- Dimensional Objects, Proceedings VLDB, pp , [9] N. Roussopoulos and D. Leifker, Direct Spatial Search on Pictorial Databases Using Packed R-Trees, Proceedings ACM SIGMOD, pp , May [10] M. Stonebraker and P. Brown, Object-Relational DBMSs, Tracking the Next Great Wave, Second Edition. San Francisco: Morgan Kaufmann, Dr. Phillip C.-Y. Sheu is currently professor of electrical and computer engineering at the University of California, Irvine. He received his Ph.D. degree from the University of California at Berkeley in electrical engineering and computer science in Prior to that, he worked as a computer scientist at Systems Control Technology, Inc., Palo Alto, California, where he designed and implemented aircraft expert control systems; and he worked as a product planning engineer at Advanced Micro Devices Inc., Sunnyvale, California, where he designed and integrated CAD systems. From 1986 to 1988, he was an assistant professor of electrical engineering at Purdue University. From 1989 to 1993, he was an associate professor of electrical and computer engineering at Rutgers University. He has authored/co-authored two books: Intelligent Robotic Planning Systems (World Scientific, 1993) and Software Engineering - An Object- Oriented Perspective (Plenum Publishing, 1996). He has authored more than 100 papers and technical reports in object-oriented databases, computer graphics, simulation, and other related areas. His paper, entitled Logic-Oriented Object Bases, was selected for the Best Paper Award by the IEEE Computer in Dr. Taehyung Wang received the B.S. degree in control and instrumental engineering from Seoul National University, Seoul, Korea, in 1985; the M.S. degree in computer science from Western Illinois University in 1994; and the Ph.D. degree from the University of California, Irvine in He is currently a postdoctoral researcher in the Department of Electrical and Computer Engineering at UC Irvine. He worked as a research engineer for LG Information and Telecommunication, Korea, from January 1985 to June 1991 where he was involved in the development of control and signal processing boards for an electronic switching system. His research interests include computer graphics, visual databases, software testing, object-relational databases, and web applications.

11 PUBLICATIONS NEWS S y iety Socie S S So ty Soci ety S METAMORPHOSIS NEWSLETTER TO MAGAZINE Starting in January of 1998, the CAS Newsletter became a technical newsletter by including short articles and worskhop descriptions on emerging technologies. The content and form of the Newsletter in 1998 has been well received, and the CAS Newsletter office has been considered to be among the most proactive of all the newsletter and magazine offices, according to the feedback received by Mike Sain. On the above basis, and also on the basis of the demand by a membership poll for a magazine, preliminary arrangements were made in 1998 to enable the CAS Newsletter to evolve from a newsletter to a magazine. In March of 1999, ExCom approved the principle of transitioning the Newsletter into a CAS magazine. Specifically, the new magazine will cater to all the six areas pertaining to our six Transactions. Accordingly, the magazine will be run by the following editorial structure: EIC Features Editor Editorial Board A proposal will be presented to the BOG, including analysis of financial implications and other details, at the November 7, 1999 meeting of the BOG. Mike Sain and his team are in charge of preparing this proposal in close cooperation with the IEEE team headed by Laura Pohl. The proposal is expected to pass the various IEEE levels in the first half of So the magazine is expected to begin regular publishing in Laura Pohl, who attended the May BOG meeting, in Orlando, fielded questions from the audience. Rui J. P. de Figueiredo on behalf of Nanni De Micheli THE ADVENTURES OF THE 'UMBLE OHM A mistake. Shlomo Karni ΩΩΠΣ...! * * CALL FOR PAPERS * * IEEE TRANSACTIONS ON VLSI SYSTEMS Special Section on System-Level Synthesis and Design Guest Editors Prof. Allen C.-H. Wu Computer Science Department Tsing Hua University Hsin-Chu, Taiwan Phone: Fax: Prof. Nikil Dutt Center for Embedded Computer Systems 444 Computer Science University of California Irvine, CA , USA Phone: Fax: Submission deadline: August 15, 1999 Acceptance notice: October 15, 1999 Final manuscript deadline: November 15, 1999 Target Publication date: September, 2000 For complete details, visit the TVLSI web site: 11

12 GOVERNORS CLIPBOARD MINUTES of the CAS BOARD OF GOVERNORS MEETING Sunday, November 8, 1998 Doubletree Hotel San Jose, California, USA I. Call to Order. President Rui de Figueiredo called the meeting to order at 1:45 p.m. II. Approval of Previous Minutes. Al Dunlop indicated that the motion in item #9e (Publications Division - Allocation of Funds to Archive all CAD Publications) of the May 31, 1998 Minutes be corrected to read: (1) A motion was made, seconded and voted to allocate $383K from DAC funds to electronically archive all CAD publications; and (2) CAS look into CDROM-archiving of all CAS transactions, except T CAD, to commemorate the s 50th Anniversary. The approval of the amended Minutes passed unanimously. III.Approval of Agenda. De Figueiredo requested to withdraw the item on Continued Consideration of the s Infrastructure Needs because he is not ready to discuss it at this time and would like to pass the matter on to President-Elect George Moschytz to address during A motion to adopt the amended Agenda was made, seconded and passed unanimously. IV. Report from the President. a. De Figueiredo presented a brief overview of the state of the. b.de Figueiredo announced the IEEE Millennium Project and that Michael Soderstrand has agreed to oversee it on behalf of the. At this time, the floor was turned over to Soderstrand who gave a detailed presentation on the project and submitted a Proposal to the Board for approval. After a lengthy discussion, R. Marks put forth the following motion: Move that proposal and budget be accepted and the indirect cost applied to salaries. J. Choma moved to amend the motion to approve the $10K being requested by Soderstrand in order for him to proceed with the job that has been described in the proposal. The amended motion was seconded and passed with 7 abstentions. Mohammed Ismail suggested that the outcome of the Millenium project/study be submitted to the CAS Newsletter for publication. c.barbara Wehner gave a brief report on the administration. d.bell Shenoi, Chair of the President s Advisory Council (PAC), announced that the proposed long-range recommendations by PAC were mailed to all ExCom and BOG members. He also distributed the preliminary report on the Membership Satisfaction Survey which is part of PAC s recommendations. In addition, Shenoi, as chair of the CAS Distinguished Lecturers Program, distributed the list of visits by the CAS Distinguished Lecturers from 1997 through September 25, e. De Figueiredo announced that, after discussion with the Solid-State Circuits representatives and Cliff Lau, CAS Constitution and Bylaws Committee Chair, it has been recommended that a revised amendment be proposed regarding the CAS/SSCS dual representation. The following motion was put forth: The IEEE Circuits and Systems (CAS) will appoint a representative to the IEEE Solid-State Circuits (SSCS) for a period of two years. This representative will be a voting member of the Administrative Committee (AdCom) of SSCS. Also, CAS will accept a representative of SSCS to serve as a voting member of the CAS Board of Governors (BOG). The motion was seconded and approved unanimously. f. De Figueiredo presented an update on the s 50th Anniversary situation. i. CDROM-archiving of CAS Transactions, to be presented later by Y.-F. Huang. 12

13 GOVERNORS CLIPBOARD ii. Article in the CAS Newsletter written by someone with insight, experience and understanding of the s history. CAS is looking for someone to take responsibility. iii. A commemorative brochure publication will be produced. Huang presented Signal Processing s booklet as an example. iv. A celebration is planned to take place in Orlando during ISCAS 99. Several ideas have already been discussed. Barbara Wehner and the Conference Division will work with the ISCAS organizing committee. The will need to consider budget implications of any extra events. v. ACE Short Courses in Thailand. Due to the economic situation in the Far East, seven courses out of the twenty-two originally proposed ran. It was suggested by G. Moschytz that the event be considered a launching of the s 50th Anniversary in the Far East. vi. Wayne Wolf mentioned that the CANDE Technical Committee would also like to contribute to the Anniversary events. He will get in touch with either R. de Figueiredo or B. Wehner. g.the following statement was read by De Figueiredo regarding the s infrastructure. Because this is my last official meeting as the President, and given the complexity of the issues pertaining to the infrastructure, I have decided to table discussion of this item now, in the hope that George Moschytz and/or his successor(s) will devote to it the attention that it deserves. However, for your information, I would like to share my thoughts with you on this subject. As soon as I assumed the position of president and fully attended the February 1998 Board of Directors series of meetings in Los Angeles, I sensed the urgent need of our putting in place a minimal organizational structure that would enable it to advance effectively the s mission at the IEEE Board level as well as at inter- and intra-societal level, not only with respect to form but also the content of its mission. I felt the urgency in view of the increasingly stiff competition for members from the IEEE membership pool. Since the presidency of Wai-Kai Chen in 1994, attempts have been made to address this issue; but it was only four years later, this year, that a first step was made in this direction by our securing the services of Ms. Barbara Wehner as administrator. When other societies, some much smaller than ours, had already established a successful road map, I felt it was not necessary for us to proceed in an ad-hoc, piecemeal, fashion, but rather to establish a minimal organization by adding one additional position, namely that of an executive director, to complement the function of our administrator. I presented a slide at the last meeting of the ExCom (September 6, 1998) providing a job description of an executive director. If the position were approved, then we would have to proceed with an internal search for a set of best qualified candidates for the position. However, our president-elect George Moschytz, with whom I discussed this issue at length, felt that this was not of the highest priority during his term. I also believe that the same view is shared by some other members of our leadership. In my opinion, the entire infrastructure issue needs to be studied carefully by an appropriate committee before it is brought for consideration by our Board. But this is a decision I will leave to George Moschytz because today is the day of my last meeting as president. h.a Committee for REStructuring of Tcas I & II (CREST) will be formed and future discussions circulated. V. Report from the President-Elect Regional Activities a. Anthony Davies, Jose Silva-Martinez and Graham Hellestrand, vice presidents for Regions 8, 9 and 10, respectively, summarized the activities in their regions. b.president-elect, George Moschytz, suggested the creation of a position of vice president for Regions 1 7. He expressed his concern that the CAS membership in these regions has been decreasing for several years, and there is a strong indication that it might be due to the lack of not having an officer specifically overseeing the activities in these regions. Moschytz strongly encouraged the creation of the position that would complement the current set-up of the VPs for Regions 8, 9 and 10. Also, he feels that an officer responsible directly for these regions would be able to devote the necessary time to stimulate chapter activities, thereby promoting the CAS and improving membership. Discussion followed, and the following motion... continued on Page 16 13

14 AWARDS 1999 GUILLEMIN-CAUER AWARD Low-IF Topologies for High-Performance Analog Front Ends of Fully Integrated Receivers Jan Crols and Michiel S. J. Steayer Abstract When it comes to integratability, the zero-intermediate frequency (IF) receiver is an alternative for the heterodyne or IF receiver. In recent years, the zero-if receiver has been introduced in several applications, but its performance cannot be compared to that of the IF receiver yet. This lower performance is closely related to its baseband operation, resulting in filter saturation and distortion, both caused by DC-offsets and self-mixing at the inputs of the mixers. The low-if receiver has a topology which is closely related to the zero-if receiver, but it does not operate in the baseband, only near the baseband. The consequences are that, as for the zero-if receiver, the implementation of a low-if receiver can be done with a high degree of integration, however, its performance can be better. In this paper, the fundamental principles of the low-if receiver topology are introduced. Different low-if receiver topologies are synthesized and fully analyzed in this paper. This is done by applying the complex signal technique a technique used in digital applications to the study of analog receiver front ends. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, March 1998, pp IEEE CAS SOCIETY 1999 AWARDS One of the features each year at ISCAS is the presentation of the Circuits and Systems Awards. True to form, this year in Orlando, Florida, the 1999 awards were announced at the 32nd IEEE International Symposium on Circuits and Systems. Despite being at the home of Disney World, this was no Mickey Mouse affair; and we are pleased to present here the winners of these prestigious awards. /Achievement Awards The Circuits and Systems Mac Van Valkenburg Award was pre DARLINGTON AWARD BiCMOS Circuits for Analog Viterbi Decoders Mohammad Hossein Shakiba, David A. Johns, and Kenneth W. Martin Abstract Analog Viterbi decoders are finding widespread use in class-iv partial-response disk-drive applications. These analog realizations are often used because they are smaller and consume less power than their digital counterparts. However, class-iv signaling allows simplifications during Viterbi detection and thus existing analog decoders have limited applications. The purpose of this paper is to develop efficient analog circuits that can be used for general Viterbi detection. To demonstrate the feasibility of the proposed approach, the analog portions of two analog Viterbi decoders were fabricated in a 0.8-µm BiCMOS process. With an off-chip digital path memory, operation up to 50 Mb/s is demonstrated. However, simulations indicate that with on-chip digital path memory, speeds on the order of 300 Mb/s can be achieved. The power consumption of the proposed approach is estimated to be 15 mw/state drawn from a single 5-V power supply. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, December 1998, pp OUTSTANDING YOUNG AUTHOR AWARD A Four Quadrant S 2 I Switched-Current Multiplier Gabriele Manganaro (co-author J. Pineda de Gyves) Abstract The analysis, design, and implementation of a two-step current-sampling switched-current (S 2 I) multiplier is presented. The S 2 I technique has been employed to compensate analog errors due to charge injection as well as those arising from the finite output impedance. A thorough circuit analysis investigating the offset sources of the S 2 I cell and of the multiplier s nonlinearities sets up the platform to effectively design the multiplier and to avoid the use of feedback, or cascode techniques, to deal with channel modulation effects. The multiplier has been implemented using a 2-µm n-well MOSIS CMOS technology. Experimental results are in agreement with the theoretical findings. The following are brief highlights of the measurement results: 1) millions of multiplications per second; 2) 1.7% total harmonic distortion for a sinusoid of 35-µA (50 Hz); 3) 206 khz bandwidth; 4) 40dB SNR; and 5) 0.3-mW zero input power consumption for a ±3-V power supply. A complete set of detailed experimental results is provided in the paper. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, July 1998, pp sented to Sanjit K. Mitra for fundamental contributions to the theory and teaching of active and digital filter theory, and for dedicated and creative service to the IEEE Circuits and Systems. The winner of the CAS Technical Achievement Award was Alfred E. Dunlop for seminal contributions to computer-aided design methodology for performance-driven physical design of VLSI circuits and systems. The CAS Education Award was bestowed upon John Choma, Jr. for

15 AWARDS inspirational teaching and for casting state-of-the-art research in circuits into textbook contributions. Franco Maloberti received the CAS Meritorious Service Award for his outstanding contributions to the broadening of the presence of the CAS, and the expansion of CAS activities in Region 8. The CAS Industrial Pioneer Award is the s newest award. The first honoree of this award is Quentin C. Cassen for leadership in the development of high-speed, low VLSI BEST PAPER AWARD Mesh Routing Topologies for Multi-FPGA Systems Scott Hauck, Gaetano Borriello, and Carl Ebeling Abstract There is currently great interest in using fixed arrays of FPGA s for logic emulators, custom computing devices, and software accelerators. An important part of designing such a system is determining the proper routing topology to use to interconnect the FPGA s. This topology can have a great effect on the area and delay of the resulting systsem. Crossbar, Hierarchical Crossbar, and Mesh interconnection schemes have all been proposed for use in FPGA-based systems. In this paper, we examine Mesh interconnection schemes, and propose several constructs for more efficient topologies. These reduce interchip delays by more than 60% over the basic four-way Mesh. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, September 1998, p CSVT BEST PAPER AWARD Very Low Bit-Rate Video Coding Based on Matching Pursuits Ralph Neff and Avideh Zakhor Abstract We present a video compression algorithm which performs well on generic sequences at very low bit rates. This algorithm was the basis for submission to the November 1995MPEG-4 subjective tests. The main novelty of the algorithm is a matching-pursuit based motion residual coder. The method uses an inner-prodcut search to decompose motion residual signals on an overcomplete dictionary of separable Gabor functions. This coding strategy allows residual bits to be concentrated in the areas where they are needed most, providing detailed reconstructions without block artifacts. Coding results from the MPET-4 Class A compression sequences are presented and compared to H.263. We demonstrate that the matching pursuit system outperforms the H.263 standard in both peak signal-to-noise ratio (PSNR) and visual quality. IEEE Transactions on Circuits and Systems for Video Technology, February 1997, pp power integrated circuits for electronic warfare, military communications, and guidance, navigation, and control for DoD, space, and secure applications; for pioneering the extremely versatile and high-performance circuits at the forefront of the OEM and consumer datatransmission electronics industry; and for leadership in telecommunications wireless standards organizations in both North America and Europe. The CAS Chapter-of-the-Year Award was presented to the Argentina Chapter (Chair: Juan E. Cousseau) for the creative start-up of a new Circuits and Systems chapter with a very successful impact on activities and membership in Argentina and beyond in Region 9. More on Page CAD BEST PAPER AWARD PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm Altan Odabasioglu, Mustafa Celik, and Lawrence T. Pileggi Abstract This paper describes an algorithm for generating provably passive reduced-order N-port models for RLC interconnect circuits. It is demonstrated that, in addition to macromodel stability, macromodel passivity is needed to guarantee the overall circuit stability once the active and passive driver/load models are connected. The approach proposed here, PRIMA, is a general method for obtaining passive reduced-order macromodels for linear RLC systems. In this paper, PRIMA is demonstrated in terms of a simple implementation which extends the block Arnoldi technique to include guaranteed passivity while providing superior accuracy. While the same passivity extension is not possible for MPVL, comparable accuracy in the frequency domain for all examples is observed. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, August 1998, pp

16 BOG Minutes... continued from Page 13 GOVERNORS CLIPBOARD was put forth: The IEEE Circuits and Systems needs to create the position of a Vice President for Regions 1 7 on the Executive Committee. BOG member, R. Marks, requested to amend the motion and have the Constitution and Bylaws (CBL) Committee prepare a draft of an amendment and, in addition, have the VP- Administration show the budgetary impact of the position s creation. The amended motion was seconded and passed with one opposed and two abstaining. VI.Report from the Past President. Past president John Choma, also the 1998 CAS Awards chair, presented the list of the awardees for Choma expressed his concern that the awards procedures are somewhat flawed and suggested that a more efficient process be adopted. De Figueiredo announced that he will be the 1999 Awards chair and emphasized that it is extremely important for the members of the Board to recommend candidates. The Call for Nominations appears in the September issues of the CAS Newsletter and on the CAS web site. Note: After the BOG meeting, the 1998 TVLSI Best Paper Award and the 1998 TCAD Best Paper Award were announced at ICCAD. See page 19 for details of the awards. VII.Report from the V. P. for Technical Activities. Magdy Bayoumi presented a progress report from the Technical Activities Division. a.a Technical Activities participation survey form has been prepared for publication in the CAS Newsletter, see page 21 of this issue, and distribution to the membership. The form is a way for members to become aware of the various technical committees which exist within CAS and to encourage them to become involved. All inquiries will be forwarded to the appropriate Technical Committee chairs for follow-up. b.technical Activities is now more involved in the ISCAS program. c.three new Technical Committees have been formed: Sensors & Micromachining; Circuits & Systems for Communications; and Cellular Neural Networks & Array Computing. All committees will be holding meetings in the near future. d.the CANDE benchmark project is proceeding well, and Bayoumi is being informed of its progress. e. A decision whether or not to proceed with a second round of the ACE Short Courses will be made after a report is received following the Thailand program scheduled to take place at the end of November. f. The CANDE Technical Committee has submitted a proposal for funding of a Verilog Standards project. A request for $75K was made and approved at the ExCom meeting. VIII.Report from the V. P. for Publications. Yih- Fang Huang put forth the following action items. a.motion: The 1998 page budget for TCAS II increase by 100 pages. This is a one-time increase to reduce some of the backlog of papers. The motion was seconded and passed with one abstention. b.motion: The Darlington Special Issue, to appear in TCAS I, January 1999, be distributed to all CAS members. The estimated cost to CAS will be approximately $16,000. At this time, Ernie Kuh gave a presentation on the content of the issue and gave credit to Bing Sheu for coming up with the idea to put together such an issue. Afterwards, Huang brought the motion back onto the floor; it was seconded and passed unanimously. c. At the May 1998 meeting, a motion was made and passed to have the look into CDROM-archiving its publications to commemorate the 50th Anniversary. Huang announced that he solicited various vendors and received proposals from three. All vendors have extensive background in these types of productions Parity Computing, Kathy Preas, and Institute of Information Science (Academia Sinica, Taipei, Taiwan). After some discussion on the needs of such a project, the following motion was presented: The Board of Governors would charge the Publications Division to make the decision on 16

17 GOVERNORS CLIPBOARD the bidder to CDROM-archive the s publications before the end of November at a fee equal to or less than the maximum of the three bids that we have at present. The motion was seconded and passed unanimously. d.a decision needs to be made regarding the annual CDROM subscription (as of 1997) and whether or not to include conference proceedings. The CD is produced twice a year and contains the content of TCAS I, TCAS II, TCAD, and TCSVT. IEEE has been running behind on the production, and members have been complaining that they have not received their CDs. A reason given by IEEE for the latest delay is that CAS includes conference proceedings which are not available on time. Motion: Proceed with the CDROM production and exclude the conference proceedings. The motion was seconded and passed unanimously. e. Motion: Continue support of the Circuits & Devices Magazine. Seconded and approved with one opposed and three abstentions. IX. Report from the V. P. for Conferences. a.bing Sheu acknowledged the help he has received from B. Wehner in processing various conference-related requests and general administrative support. b.sheu reported that ISCAS 2002 is scheduled to be held in the US. He has received one formal proposal from Phoenix, Arizona. In addition M. Bayoumi and M. Ismail have expressed interest in submitting proposals to host the conference in New Orleans and Detroit, respectively. Sheu encouraged all to submit detailed proposals for consideration by the Conference Division. A decision on the 2002 site will be made before the end of the year. c.iscas 2003 is scheduled to be held in Region 10. A solicitation for proposals will be circulated in the near future. d.a meeting to discuss the ICECS and ECCTD situation took place in Lisbon, Portugal. The CAS has announced that ICECS will be its Region 8 flagship conference. e.future ISCAS schedule:1999 Orlando, Florida; 2000 Geneva, Switzerland; 2001 Sydney, Australia; 2002 Region 1-7; 2003 Region 10; 2004 USA/Canada; 2005 Region 8; 2006 USA/Canada. f. Sherif Michael, chair of ISCAS 98, mentioned a billing problem he is trying to resolve with IEEE. Michael indicated that the charge is incorrect and he is contesting it. De Figueiredo requested that Michael describe the matter to him in writing and he will bring it to the attention of the appropriate individuals at IEEE Headquarters. X. Report from the V. P. for Administration. K. Thulasiraman presented the financial status of the. XI. Amendments to the Constitution and Bylaws. A proposal for two amendments to the Constitution and Bylaws (CBL) was presented by Graham Hellestrand on behalf of Cliff Lau, chair of the CBL Committee to help facilitate continuity in the Executive Offices of the CAS. A motion to approve the changes was put forth, seconded, and passed with one abstention. See page 18 in the Newsletter for the amendments. XII. New Business. Al Dunlop put forth the following motion regarding conduct of BOG business by electronic means. Motion: The BOG may vote by confirmed transmission between BOG meetings. The voting is over a two-week period from the time that the transmission is sent. The count of the votes will be percent of approval as compared to the total count of BOG members not respondents. A straw vote, taken to have the motion acted on by the Constitution and Bylaws Committee and presented at the next BOG meeting, was seconded and passed unanimously. XIII.Appreciation to Outgoing Officers and BOG Members. De Figueiredo expressed his gratitude to all of the outgoing officers and BOG members for their valuable contributions to the. In addition, De Figueiredo welcomed the newcomers who have recently been elected. G. Moschytz took this opportunity to thank Rui de Figueiredo for his drive, intensity, energy,... continued on Page 18 17

18 GOVERNORS CLIPBOARD BOG Minutes... continued from Page 17 and most of all commitment to the CAS during his presidency. A round of applause followed. XIV. Next Meeting. The next meeting of the BOG will be held on Sunday, May 30, 1999 in Orlando, Florida, in conjunction with ISCAS. XV. Adjournment. The meeting adjourned at 6:50 p.m. BOG HiLites CAS Constitution and Bylaws Changes To provide continuity in the Executive Offices of the CAS the following two amendments were approved by the Board of Governors at their meeting on November 8, These changes take effect 30 days after publication (i.e. the mailing of this issue) unless two percent or more of the members object. 1. Change Article IV, Section 3 in the Constitution to: The President shall serve as an officer for three years: the year following his/her election as president-elect, the year as president, and the following year as past president. The past president may again be elected to the presidency following a lapse of three years after serving as president. The other officers are elected for two year terms. They may each serve a maximum of two consecutive full terms for a total of four years. Eligibility for office is restored after a lapse of two years from office. Filling an unexpired term for more than six months shall count as a full term. 2. Insert in the Bylaws, Article III, Section 11: The following officer positions shall be elected in odd years (e.g. 1999) to begin serving the two-year term the following year: Vice President - Technical Activities, Vice President - Conferences, Vice President - Region 8, and Vice President - Region 9. The following officer positions shall be elected in even years (e.g. 2000) to begin serving the two-year term the following year: Administrative Vice President, Vice President - Publications, and Vice President - Region 10. Also, at the Spring BOG meeting in Orlando, Florida, the following amendments were approved to create the position of Vice President of Regions 1 7. With the amendments is a note to include the V.P. of Regions 1 7 in all references to the Regional Vice Presidents throughout the Bylaws. 1. Change in the Bylaws, Article II, Section 6: There shall be four additional Vice Presidents - one residing in Regions 1 7, one in Region 8, one in Region 9, and one in Region Change in the Bylaws, Article III, Section 11: The following officer positions shall be elected in even years (e.g. 2000) to begin serving the two-year term the following year: Administrative Vice President, Vice President - Publications, Vice President Regions 1 7, and Vice President - Region

19 MORE AWARDS The honorees of two 1998 Best Paper Awards, the CAD Transactions Best Paper Award and the VLSI Transactions Best Paper Award, were not selected in time to be announced at ISCAS 98. They were, therefore, announced in November at ICCAD 98 in San José, California. The details of those awards are provided below. Congratulations to the winners! 1998 TCAD BEST PAPER AWARD Logic Decomposition during Technology Mapping E. Lehman, Y. Watanabe, J. Grodstein, and H.L. Harkness Abstract A problem in technology mapping is that the quality of the final implementation depends significantly on the initially provided circuit structure. This problem is critical, especially for mapping with tight and complicated constraints. In this paper, we propose a procedure which takes into account a large number of circuit structures during technology mapping. A set of circuit structures is compactly encoded in a single graph, and the procedure dynamically modifies the set during technology mapping by applying simple local transformations to the graph. State-ofthe-art technology mapping algorithms are naturally extended, so that the procedure finds an optimal tree implementation over all of the circuit structures examined. We show that the procedure effectively explores the entire solution space obtained by applying algebraic decomposition exhaustively. However, the run time is proportional to the size of the graph, which is typically logarithmic in the number of circuit structures encoded. The procedure has been implemented and used for commercial design projects. We present experimental results on benchmark examples to demonstrate its effectiveness. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, August 1997, pp TVLSI BEST PAPER AWARD Programmable Active Memories: Reconfigurable Systems Come of Age J.E. Vuillemin, P. Bertin, D. Roncin, M. Shand, H.H. Touati, and P. Boucard Abstract Programmable active memories (PAM) are a novel form of universal reconfigurable hardware coprocessor. Based on field -programmable gate array (FPGA) technology, a PAM is a virtual machine, controlled by a standard microprocessor, which can be dynamically and indefinitely reconfigured into a large number of application-specific circuits. PAMs offer a new mixture of hardware performance and software versatility. We review the important architectural features of PAMs, through the example of DECPeRLe-1, an experimental device built in PAM programming is presented, in contrast to classical gate-array and full custom circuit design. Our emphasis is on large, code-generated synchronous systems descriptions; no compromise is made with regard to the performance of the target circuits. We exhibit a dozen applications where PAM technology proves superior, both in performance and cost, to every other existing technology, including supercomputers, massively parallel machines, and conventional custom hardware. The fields covered include computer arithmetic, cryptography, error correction, image analysis, stereo vision, video compression, sound synthesis, neural networks, high-energy physics, thermodynamics, biology and astronomy. At comparable cost, the computing power virtually available in a PAM exceeds that of conventional processors by a factor 10 to 1000, depending on the specific application, in A technology shrink increases the performance gap between conventional processors and PAMs. By Noyce s law, we predict by how much the performance gap will widen with time. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, March 1996, pp

20 20 MorphoSys continued from Page 7 the target applications. We have implemented the MorphoSys M1 chip using CMOS 0.35 µm 3.3 V technology. We visualize that MorphoSys may be the precursor of a generation of general-purpose processors that have a specialized reconfigurable component designed for multimedia applications. Ming-hau Lee received the Bachelor of Science degree from the Department of Electrical Engineering at the National Taiwan University, Taipei, Taiwan in In 1997, he received the M.S. degree in electrical and computer engineering from the University of California, Irvine (UCI) where he is currently working toward the Ph.D. degree. He is currently a research assistant at the UCI Reconfigurable Computing Laboratory. His research interests are in computer architecture, reconfigurable computing, and VLSI design. Hartej Singh received the Bachelor of Technology degree in electrical engineering from the Thapar Institute of Engineering and Technology, Patiala, India in He received the M.S. degree from the Department of Electrical and Computer Engineering at the University of California, Irvine (UCI) in He is currently a doctoral candidate at the University of California, Irvine, and is associated with the MorphoSys project at the UCI Reconfigurable Computing Laboratory. His areas of interest are architectural mapping of multi-media applications, reconfigurable computing, and VLSI systems design. Guangming Lu received the Bachelor of Engineering degree in electronic engineering from the Tsinghua University, Beijing, China, in From 1994 to 1996, he was a graduate student in the Department of Computer Science at the Peking University, Beijing, China. He received the M.S. degree from the Department of Electrical and Computer Engineering at the University of California, Irvine (UCI) in 1997, where he is currently working toward the Ph.D. degree. Since 1997, he has been a research assistant at the UCI Reconfigurable Computing Laboratory. His areas of interest are VLSI systems design, CAD tools, design automation, communication and computer architecture. Nader Bagherzadeh received the Ph.D. degree in computer engineering from the University of Texas at Austin in From 1980 to 1984, he was with AT&T Bell Laboratories in Holmdel, New Jersey. Since 1988, he has been with the University of California, Irvine where he is currently a professor in the Electrical and Computer Engineering Department. His research interests are in parallel processing, reconfigurable computing, computer architecture, and VLSI design. Fadi J. Kurdahi received the Bachelor of Engineering degree in electrical engineering from the American University of Beirut, Lebanon, in He received the M.S. degree in electrical engineering and the Ph.D. degree in computer engineering from the University of Southern California in 1982 and 1987, respectively. Since 1987, he has been with the University of California, Irvine where he is currently a professor in the Electrical and Computer Engineering Department and holds a courtesy appointment with the Information and Computer Science Department. His areas of interest are highlevel synthesis of digital circuits, VLSI systems design and layout, and design automation. Eliseu M. C. Filho received the Electronic Engineer degree from the University of Brasilia in 1983, the M. Sc. degree in informatics from the Catholic University of Rio de Janeiro, Brazil, in 1987, and the D. Sc. degree in systems and computer engineering from the Federal University of Rio de Janeiro (UFRJ), Brazil, in Currently, he is associate professor in the Department of Systems and Computer Engineering at UFRJ. His areas of interest include computer architecture, in particular instruction-level parallelism and reconfigurable systems, VLSI systems, and computer networks. Vladimir Castro Alves received the Electronic Engineer degree from the Federal University of Rio de Janeiro, Brazil, in 1985 and the DEA and Ph.D. degrees from the National Polytechnic Institute of Grenoble, France, in 1989 and 1992, respectively. He held the Eurochip Lecture position at the University of Aveiro, Portugal, during the academic year , where he was also responsible for the VLSI Design Laboratory. He is currently associate professor at the Federal University of Rio de Janeiro where he lectures on VLSI design and testing. His interests are in VLSI design, computer architecture, and digital and mixed-signal circuit testing.

21 50 TH ANNIVERSARY AWARDS S y DEADLINE July 31, 1999 In commemorating the 50th anniversary of the IEEE Circuits and Systems and the centennial celebration of the IEEE, both the Circuits and Systems and the IEEE will issue Commemorative Medals to deserving individuals. The CAS Awards Committee, appointed by CAS president George Moschytz and chaired by Prof. Rui J. P. de Figueiredo, with the approval of the CAS Board of Governors, will select the recipients for the CAS Medals and nominate candidates for the IEEE Medals. Nominees are solicited who meet at least one of the following criteria: 1.Outstanding Technical Achievement; 2.Outstanding Achievement in Education; 3. Outstanding Leadership in Technology Development; 4. Outstanding Leadership in Education; or 5. Outstanding Service to the CAS. The Awards Committee has decided that all living members of our who have received the M. E. Van Valkenburg, Technical Achievement, Education, or Meritorious Service Awards, or IEEE-wide medals or field awards, will be automatically considered for these medals, and no additional nominations are required. Please use the Nomination Form that appeared in CAS Newsletter (Vol. 9, No. 3, September, 1998, found on the CAS Newsletter web site, ~stjoseph/newscas) and send your nomination or submit the following, preferably in , to Professor. Rui J. P. de Figueiredo, Department of Electrical and Computer Engineering, University of California, Irvine, CA , Tel: , Fax: , 1. Name/address of nominee, present employment position(s), highest degree attained, telephone (day); 2. Name, address, telephone (day), fax, and of nominator; 3. Basis for nomination: a statement not exceeding 750 words on why the candidate is being nominated for the award. This statement should then be followed by the record of accomplishments of the candidate as an educator, as a researcher and/or as an administrator, as appropriate. 4. No curriculum vitae is needed. iety Socie S S 5. Publications: list all books, book chapters, and patents published. Select no more than 10 of the most important publications stating their significance very briefly and lucidly. 6. References: no more than three brief supporting letters from colleagues should be included with each award nomination. List the names of the references on the nomination form or letter. The reference letters can either be collected by the nominator or forwarded unopened to Professor de Figueiredo; or the referees can be instructed to forward their recommendations directly to Prof. de Figueiredo. All reference letters must be received by the due date of the nominations. Soci IEEE Circuits & Systems You are invited to participate in the Technical Committees The Technical Committees (TCs) are the heart and soul of the Circuits and Systems. They serve the s membership and give them a forum to participate in various activities: conferences, workshops, publications, and education. Through these TCs you have an opportunity to interact with leading researchers, developers, and educators from academia, industry, and research laboratories. You will have a chance to influence, impact, and shape the direction of the in the most effective way. If you are interested in participating in these activities, simply check out the committee(s) relevant to you, and please fax, mail, or the requested information below, to: Barbara R. Wehner, 15 W. Marne Avenue, P.O. Box 265, Beverly Shores, IN ; Tel: (219) ; Fax: (219) ; Analog Signal Processing, Cellular Neural Networks & Array Computing, Circuits & Systems for Communication, Computer-Aided Network Design, Digital Signal Processing, Multimedia Systems & Applications, Neural Systems & Applications, Nonlinear Circuits & Systems and Chaos, Power Electronic Circuits & Power Systems, Sensors & Micromachining, Visual Signal Processing, VLSI Systems & Applications Name: Member #: Address: Tel: Fax: For more information: Magdy A. Bayoumi, CAS Vice President for Technical Activities, The Center for Advanced Computer Studies, University of Southwestern Louisiana, P.O. Box 44330, Lafayette, LA 70504; 21

22 Peop Pe Kenneth Alan Loparo ople Peop eople P eople Pe ople Pe Kenneth Alan Loparo For contributions to stochastic stability and control theory with applications to engineering systems. eople Pe eople Pe P e IEEE CAS FELLOW PROFILES 1999 Kenneth A. Loparo received the Ph.D. degree in systems and control engineering from Case Western Reserve University, Cleveland, Ohio, in He was assistant professor in the Mechanical Engineering Department at Cleveland State University from 1977 to 1979 and has been on the faculty of The Case School of Engineering, Case Western Reserve University, since He is professor of electrical engineering and computer science and holds academic appointments in mechanical and aerospace engineering and mathematics. He has received numerous awards including the Sigma Xi Research Award for contributions to stochastic control, the John S. Diekoff Award for Distinguished Graduate Teaching, the Tau Beta Pi Outstanding Engineering and Science Professor Award, the Undergraduate Teaching Excellence Award and the Carl F. Wittke Award for Distinguished Undergraduate Teaching. He was associate dean of engineering from and chair of the Department of Systems Engineering from His research interests include stability and control of nonlinear and stochastic systems with applications to large-scale electric power systems; nonlinear filtering with applications to monitoring, fault detection, diagnosis and reconfigurable control; information theory aspects of stochastic and quantized systems with applications to adaptive and dual control and the design of digital control systems. Dr. Loparo has held numerous positions in the IEEE Control Systems including chair of the Conference Audit and Finance Committees, member of the Conference Editorial Board and Technical Activities Board, and associate editor for the IEEE Transactions on Automatic Control and the IEEE Control Systems Magazine. Yu Hen Hu For contributions to parallel VLSI algorithms and architectures. Yu Hen Hu Yu Hen Hu received the BSEE degree from National Taiwan University, Taipei, Taiwan, ROC. He received the MSEE and Ph.D. degrees in electrical engineering from the University of Southern California, Los Angeles. He has been assistant professor in the Electrical Engineering Department at Southern Methodist University, Dallas, Texas. He is currently on the faculty in the Department of Electrical and Computer Engineering, University of Wisconsin, Madison. His research interests include VLSI signal processing, artificial neural networks, fast algorithms and multimedia micro-architecture, and computer aided design tools for VLSI. He has published more than 170 journal and conference papers in these areas. Professor Hu was associate editor from 1988 to 1990 of the IEEE Transactions on Acoustics, Speech, and Signal Processing in the areas of system identification and fast algorithms. He served as IEEE Signal Processing secretary from 1996 to 1998, and as chairperson of the Neural Network for Signal Processing technical committee from 1993 to He was technical program co-chair for the 1995 International Symposium on Artificial Neural Networks in Taiwan, and technical program co-chair of the 1996 Great Lakes Symposium on VLSI in Ames, Iowa. He is also the general chair of the 1999 IEEE Workshop on Neural Networks for Signal Processing. 22

23 Peopl le Peop ple Peo ople Peo P CIRCUITS AND SYSTEMS SOCIETY MEMBERS P eople Pe Christopher Patrick Silva For contributions in the application of nonlinear circuits and systems theory to communications signal processing. Pe Pe ople Peo ople Christopher P. Silva received the B.S., with highest honors, M.S., and Ph.D. degrees, all in electrical engineering, in 1982, 1985, and 1993, respectively, from the University of California at Berkeley, with an emphasis on nonlinear circuit and system theory. He joined The Aerospace Corporation in 1989, where he is currently engineering specialist in the Electronic Systems Division. He has been the principal investigator on several internal research and development projects addressing nonlinear microwave CAD, chaosbased communications, and the modeling and compensation of nonlinear satellite communications channels, the last of which has evolved into a long-term military program support team effort for advanced wideband technology development. Dr. Silva is perhaps best known for his many contributions to the dissemination of nonlinear techniques, the knowledge of which mainly develops/resides in academic circles, to the practicing engineering community. This needed transfer has been accomplished both through his application of these techniques to real-world problems in the support and development of Air Force satellite communications programs, and by his numerous invited conference, society meeting, corporate, and academic institution talks on the subject. These presentations have been accompanied by corresponding publications. Several major accomplishments have resulted from his individual and team efforts, including the invention of a robust high-frequency chaotic oscillator design, and the development of novel measurement techniques and nonlinear high-power amplifier models. This work has received much corporate, customer, and community-wide attention, resulting in several inventor awards, patents, and other corporate honors. Dr. Silva is also a member of The American Association for the Advancement of Science, The American Institute for Aeronautics and Astronautics, the American Mathematical, and the for Industrial and Applied Mathematics. Christopher P. Silva Irith Pomeranz For contributions to the area of test generation for digital logic circuits. Irith Pomeranz received the B.Sc. degree, summa cum laude, in computer engineering and the D.Sc. degree from the Department of Electrical Engineering at the Technion-Israel Institute of Technology in 1985 and 1989, respectively. From 1989 to 1990 she was lecturer in the Department of Computer Science at the Technion. In 1990 she joined the Department of Electrical and Computer Engineering at the University of Iowa, where she is currently professor. Her present research interests include testing, design for testability, and synthesis and verification of computer systems. Dr. Pomeranz was a recipient of the NSF Young Investigator Award in 1993, and of the University of Iowa Faculty Scholar Award in She won best paper awards at EURO-DAC in 1992 and She serves as associate editor of the ACM Transactions on Design Automation. She served as guest editor of the IEEE Transactions on Computers January 1998 special issue on dependability of computing systems. She is a program co-chair of the 29th IEEE Fault-Tolerant Computing Symposium, Irith Pomeranz 23

24 Peop Pe John Vincent McCanny ople Peop eople Pe ople Pe ople Pe John Vincent McCanny For contributions to signal processing with Very-Large-Scale Integrated Circuits. John V. McCanny obtained a B.Sc. in physics from the University of Manchester in 1973 and a Ph.D. in solid-state physics from the University of Ulster in In 1979 he joined the Royal Signals and Radar Establishment (now DERA), Malvern, England where he became principal scientific officer. He joined Queen s University Belfast in 1984, becoming professor of microelectronics engineering in His contributions include pioneering research on bit level systolic array architectures, methods for significantly enhancing the sampling rates of recursive DSP functions, signal processing arithmetic architectures and methodologies for the rapid design of complex DSP silicon IP cores. He has published over 180 scientific papers in major journals and international conferences, holds 10 patents and has edited 4 research books. He was recently eople Pe eople Pe P e IEEE CAS FELLOW PROFILES 1999 awarded a D.Sc. degree (higher Doctorate), by Queen s University in recognition of his research contributions. He has also successfully co-founded two high technology companies, APT Ltd. (digital audio compression) and ISS Ltd. (advanced DSP silicon IP cores) where he is also currently CTO. Professor McCanny is a fellow of the Royal Academy of Engineering, the Institution of Electrical Engineers and the Institute of Physics. He currently chairs the IEEE Technical Committee on the Design and Implementation of Signal Processing Systems, having been involved, for many years, in the organization of major conferences in this field (including general and technical chair). In 1996 he was awarded a Royal Academy of Engineering Silver Medal for outstanding contributions to British Engineering leading to commercial development. Bang-Sup Song For contributions to integrated filters and analog-digital converters. Bang-Sup Song Bang-Sup Song received the B.S. degree from the Seoul National University in 1973, the M.S. degree from the Korea Advanced Institute of Science in 1975, and the Ph.D. degree from the University of California, Berkeley in From 1983 to 1986 he was a member of the technical staff at AT&T Bell Laboratories, Murray Hill, and was also an adjunct faculty member in the Department of Electrical Engineering, Rutgers University. Since 1986, he has been with the Department of Electrical and Computer Engineering and the Coordinated Science Laboratory, University of Illinois at Urbana, where he is professor. His interest is in analog ICs for highspeed precision data converters, high-frequency filters, radio transceivers, phaselocked loops, CD/DVD read channels, and complex vector processing. Prof. Song received the Distinguished Technical Staff Award from AT&T Bell Laboratories in 1986, the Career Development Professor Award from Analog Devices in 1987, and the Xerox Senior Faculty Research Award in His IEEE activities have been in the capacities of associate editor, guest editor, and program committee member for the IEEE Transactions on Circuits and Systems, IEEE Journal of Solid-State Circuits, IEEE International Solid-State Circuits Conference, and IEEE Symposium on Circuits and Systems. 24

25 Organizing Committee General Chair Martin Hasler Swiss Fed. Inst. of Techn., Lausanne Vice Chair George S. Moschytz Swiss Fed. Inst. of Techn., Zürich Technical Program Chair Joos Vandewalle Katholieke Univ. Leuven, Belgium Techn. Program Vice Chair Georges Gielen Katholieke Univ. Leuven, Belgium Special Sessions Chair Maciej Ogorzalek Univ. of Mining & Metallurgy, Krakow Special Sessions Vice Chair Eric Vittoz CSEM, Neuchâtel Tutorial Chair Josef A. Nossek University of Techn., Munich, Germany Tutorial Vice Chair Hans Peter Graf AT&T Labs Research, Red Bank NJ Publications Chair Hervé Dedieu Swiss Fed. Inst. of Techn., Lausanne Publicity Chair Martin Hänggi Swiss Fed. Inst. of Techn., Zürich Exhibit Chair Christian Enz CSEM, Neuchâtel, Switzerland Local Arrangements Chair André Stauffer Swiss Fed. Inst. of Techn., Lausanne Registration Chair Christiane Good Swiss Fed. Inst. of Techn., Lausanne Finance Chair Jean-Louis Pfaeffli Energie Ouest Suisse, Lausanne Database Chair Bertrand Dutoit Swiss Fed. Inst. of Techn., Lausanne ISCAS Steering Committee Chair Hari Reddy California State Univ., Long Beach International Coordinators Michael Peter Kennedy University College Dublin, Ireland Shin ichi Oishi School of Science & Eng., Tokyo, Japan Angel Rodríguez-Vázquez Universidad de Sevilla, Spain ISCAS 2000 THE 2000 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS SUNDAY,MAY 28 WEDNESDAY,MAY 31, 2000 INTERNATIONAL CONFERENCE CENTER OF GENEVA (CICG) GENEVA,SWITZERLAND CALL FOR PAPERS Emerging Technologies for the 21 st Century The 2000 IEEE International Symposium on Circuits and Systems will be held in Geneva, Switzerland. The symposium is sponsored by the IEEE Circuits and Systems. The symposium will include regular sessions on the topics listed below; special sessions on emerging circuits and systems topics; plenary sessions on selected advanced aspects of the theory, design and applications of circuits and systems; and short courses given by experts in specific state-of-the-art subject areas. The symposium will be organized into parallel lecture sessions and poster sessions. Papers suitable for poster presentation are those that require interactive discussion; otherwise, poster and lecture presentations carry equal weight. Prospective authors are invited to submit their papers reporting original work as well as tutorial overviews in all areas of circuits and systems. Exciting new areas and problems for research in circuits and systems will be presented in special sessions. Short courses will provide up-to-date knowledge on important topics. Topics for regular sessions include, but are not limited to, the following: 1. Analog Circuits and Signal Processing 1.1 Analog circuits and filters 1.2 Switched capacitor/current techniques 1.3 Analog and mixed signal processing 1.4 Data conversion and Σ- modulation 2. General and Nonlinear Circuits and Systems 2.1 Linear and nonlinear circuits and systems 2.2 Linear and nonlinear circuit theory 2.3 Chaos, bifurcation and applications 2.4 Distributed circuits and systems 3. Digital Signal Processing 3.1 Digital filters and filter banks 3.2 Wavelets and multirate signal processing 3.3 Adaptive signal processing 3.4 Multidimensional systems 3.5 Fast computations for signal processing 4. Multimedia and Communications 4.1 Speech processing and coding 4.2 Image processing and coding 4.3 Video and multimedia technology 4.4 Signal processing for communications 4.5 Computer communications 5. VLSI Circuits and Systems 5.1 Analog and digital ICs 5.2 Low power design 5.3 VLSI physical design 5.4 Testing: analog, digital and mixed 5.5 High level synthesis & hardware/software codesign 5.6 Logic synthesis and formal verification 5.7 Fault tolerant systems 5.8 Sensors and micromachining 6. Computer Aided Design 6.1 Numerical and symbolic methods 6.2 Linear and nonlinear optimization 6.3 Graph theory, combinatorial optimization 6.4 Modeling and simulation techniques 6.5 CAD tools 7. Neural Networks and Systems 7.1 Neural networks 7.2 Cellular neural networks 7.3 Fuzzy logic and circuits 7.4 Learning and intelligent systems 8. Power Systems and Industrial Applications 8.1 Sensors 8.2 Robotics 8.3 Banking and security systems 8.4 Micromechatronics 8.5 Power electronics and systems Authors are invited to fill out the electronic form that enables the electronic paper submission at the address: WWW address for submission: The full four-page paper in double column format, including paper title, authors names and aliation, and short abstract is requested. Only electronic submissions (postscript format) are accepted. Those submitters who are unable to send in their contribution electronically are asked to contact the program chairs. Fax +32/16/ ). Once accepted, authors will be asked to prepare a final four-page camera-ready paper for the proceedings. AUTHOR S SCHEDULE Deadline for Submission of Papers October 1, 1999 Notification of Acceptance December 23, 1999 Deadline for Submission of Camera-Ready Paper January 31, 2000 Proposals for Special Sessions, Plenary Sessions, and half or full-day Short Courses may be submitted to the respective chair by September 15, Please contact them directly for further information. Check the symposium web site for up to date information: Specific questions to the Organizing Committee members may be directed, as appropriate, to one of the listed addresses. 25

26 May 11, 1928 April 15, It is with great sadness that I report the death of a close friend, an outstanding engineer and scholar, and a fine and compassionate gentleman, Carl Ferdinand Kurth; he passed away unexpectedly, shortly before his 71 st birthday, at his home in Port St. Lucie West, Florida on the morning of April 15, Carl is survived by his wife of 48 years, Ursula L. Kurth and his children, Matthias C. Kurth and Cornelia L. Kurth-Bowen, and five grandchildren. Carl was born on May 11, 1928 in Zwickau, Saxony, Germany. He grew up in a family in which his father had a radio repair shop during the 1930s, 1940s and 1950s. In 1944 until the end of the war at the age of fifteen, he and his entire high-school class were drafted into the army to operate antiaircraft radar systems outside Berlin. As he told it, he and his comrades considered this an exercise in survival, which he fortunately passed successfully. After the war he studied electrical engineering at the Polytechnikum Mittweida, graduated, and married Ursula in Until 1960 he held various positions in R&D communication systems in East Germany, before escaping with his wife and two children (Matthias 4 1/2, Cornelia 3 1/2 years old) in the subway from East to West Berlin, just before the closing of the Berlin Wall. He prepared for this flight to the West by stuffing his attaché case with belongings of value and, in his daily commute by subway from East to West Berlin, where he worked, depositing them in his West- Berlin office. To Ursula s consternation, she found out later that the belongings of value were not silver dishes and the like, but his books from College and University, which he knew he would need to start a new life in emigration. As Carl told me many years later, it was in fact those valuable books that enabled him to pick up immediately as an electrical engineer when starting his new life, with his family, in the United States. This new life first began in Stuttgart, West Germany, where Carl worked at Standard Electric Lorenz until 1964, when he and his family emigrated to the United States. His first position was that of an instructor at Lehigh University, Bethlehem, PA, after which, in 1965, he joined the Merrimack-Valley Bell Laboratories in North Andover, Massachusetts. For the next 24 years Carl worked there successfully in forward-looking projects entailing research and development in circuit design, as well as network and transmission system development. As supervisor and engineer he was highly respected and appreciated by all who knew him. Numerous members of his group were promoted to management, and his own personal achievements were recognized and rewarded by a large number of patents, professional publications and awards both inside

27 CARL FERDINAND KURTH and outside Bell Labs. Among his many publications is a textbook, coedited with Sanjit K. Mitra, on Miniaturized and Integrated Filters (John Wiley, 1989). It was in those years (in the 60s and early seventies) that I had the pleasure of working with Carl on the development of the first Bell System thin-film hybrid active RC filters for transmission systems, and later, in the late 70s, again in the analysis and design of switched-capacitor filters. Those years and, later, months of work together with Carl belong to the richest and most memorable of my engineering career. Soon after coming to the United States Carl Kurth joined the IEEE, and most importantly for us, the Circuits and Systems. As everywhere else, Carl was soon to make an impact here as well. In 1977 he was presented with the IEEE-CAS Darlington Prize Paper Award; in 1979 he was nominated an IEEE Fellow; in 1980 he was president of the CAS ; and in 1984 he was awarded an IEEE Centennial Medal. His Fellow Award was for contributions to the practical use of active filters and leadership in the applications of digital signal processing to telecommunications systems. This citation is in itself somewhat unusual and reflects the extraordinarily wide spectrum of knowledge that made Carl a remarkable and outstanding engineer. It draws attention to the fact that Carl was equally at home in the intricacies of classical network and filter theory and analog active RC filter design, as he was in those of digital signal processing, digital circuit design and telecommunication systems and networks. It was this vast knowledge and expertise that made Carl stand out clearly as a rare and exceptional engineer, and made any discussion with him on the widest range of science and technology a rewarding experience. In this sense he was a Circuits-and-Systems engineer par excellence. But Carl was by no means a narrowminded technocrat. He loved travelling, with Ursula who usually accompanied him; he was interested in other cultures, was an amateur photographer, and generally appreciated the good life in America, and his fortune in having left Europe behind. He had become a proud American with valuable and colorful European overtones, and was looking forward to living in his self-designed and selfbuilt retirement home in Florida with Ursula, and to visits by his successful two children of whom he was so very proud together with the five grand children. This May, just after his 71 st birthday, was to provide a particularly memorable and enjoyable opportunity to which he and Ursula were keenly looking forward; it was the reunion with old CAS friends at the ISCAS in Orlando, just an hour s drive away from his home. Sadly, it was not to be. We shall think of him; and those of us who knew him will remember him and miss him very much. George S. Moschytz 27

28 ces laces Plac Places REGION 8 and OTHER WORKSHOP NEWS ces Place Places ces Places Places P SUMMER IN EUROPE? es Places Places Pla s Places ces Place Below you will find a list of possible reasons for spending some of your summer in various nice places in Europe. Please pass the details on to your colleagues if you cannot attend yourself. Prof. Tony Davies VP for Region 8 1. VIPromCom 99 in Croatia International Workshop on Video Processing and Multimedia Communications, June 23 25, 1999, Zadar, Croatia. Workshop Chair: Branka Zovko-Cihlar. This is the 41st ELMAR International Symposium; organization is by the University of Zagreb, co-sponsored by the IEEE Croatia Section. Zadar is an island and the event will be held at a hotel in a pine-wood and beach location with an associated Sailing Regatta. 2. SCS 99 in Romania SCS 99 (International Symposium on Signals, Circuits and Systems), July 6 7, 1999, Iasi, Romania. Symposium Chair: Liviu Goras. This is now an established regular event in Romania, and international attendance will be very welcome. Co-sponsors are the IEEE Romania CAS Chapter and the CAS. Iasi is accessible by plane or by Intercity train from Bucharest. 3. NDES 99 in Denmark The seventh annual workshop on Nonlinear Dynamics of Electronic Systems (NDES 99) will be hosted by the Department of Information Technology, Technical University of Denmark, July 15-17, 1999, at Ronne, Denmark. Workshop Chair: Erik Lindberg. Co-sponsorshop is by the IEEE CAS. NDES 99 will be held on the island of Bornholm, at the Hotel Griffin in Ronne. Access to Bornholm is by air, ship or bus/ferry from Copenhagen (or Ystad in Sweden); and ferries also run from North Germany (Sassnitz) and North Poland (Swinoujscie) to Ronne. For local information about NDES 99, look at: 4. IWSSIP 99 in Slovakia IWSSIP 99 (6th International Workshop on Systems, Signals and Image Processing), June 2 4, 1999, Bratislava, Slovakia. This workshop is co-sponsored by IEE, IEEE, and EURASIP. The General Chairs are Kalman Fazekas (Budapest) and Branka Zovko-Cihlar (Zagreb). 5. ECCTD 99 in Italy ECCTD 99 (European Conference on Circuit Theory and Design), August 29 September2, 1999, Stresa, Italy. Conference Chair: Pier Paulo Civalleri. ECCTD is a regular event of the European Circuits, and ECCTD 99 is organized in cooperation with the CAS. 6. ICECS 99 in Cyprus ICECS 99 (6th International Conference on Electronics, Circuits and Systems), September 5-8, 1999, Pafos, Cyprus. ICECS has become established as a successful venture in the Mediterranean area, and ICECS 99 is co-sponsored by the IEEE CAS. Places Places Pla Places laces Plac Call for Participation Places Places IEEE CAS-COM WORKSHOP 99 Second IEEE CAS Workshop on Emerging Technologies in Circuits and Systems: IEEE CAS-COM Workshop on High-Speed Data over Local Loops and Cable Princeton University, Princeton, New Jersey July 26 28, 1999 Keynote Speaker: Robert W. Lucky Corporate Vice President, Applied Research Telcordia, Inc. The IEEE Circuits and Systems (CAS) and the IEEE Communications (COMSOC) announce the co-sponsorship of a Workshop on High-Speed Data over Local Loops and Cable, to be held at Princeton University, Princeton, New Jersey, on July 26 28, This is the second in a series of IEEE CAS Workshops on Emerging Technologies in Circuits and Systems. The three-day workshop addresses critical equipment implementation issues for high-speed access to the Internet and other data services. This workshop focuses on the last mile of networks delivering modern digital services to the home, i.e., the bottleneck that exists from curbside to the home where the fiber optics medium may be too costly. The program will combine presentations by experts in the field from academia and industry, with panel and informal discussions. Individuals interested in further information should consult the workshop website at or send to Co-Chairs: Ruey-wen Liu Department of Electrical Engineering University of Notre Dame Notre Dame, IN Ph: (219) W. Kenneth Jenkins Director, Coordinated Science Laboratory 1308 W. Main Street University of Illinois Urbana, Illinois Ph: (217) Fax: (217)

29 Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Third International Workshop on Design of Mixed- Mode Integrated Circuits and Applications 42nd Midwest Symposium on Circuits and Systems August 8 11, 1999 New Mexico State University Marriott CasaMagna Hotel Puerto Vallarta, Mexico July 26 28, 1999 The Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications will be held in Puerto Vallarta, Mexico, July 26-28, The conference will be devoted to presentations and discussions on the state of the art of solid-state circuits, and are intended for engineers, researchers and graduate students interested in looking into forthcoming developments of IC design and practical implementations. A major purpose of the Workshop is to continue extending the knowledge of CAS disciplines. Chairmen: Program Chairmen: Arturo Sarmiento Reyes José Silva-Martinez Franco Maloberti Edgar Sánchez-Sinencio For further information: José Silva-Martinez, Technical Program Chair P.O. Box 51 and 216, Puebla, Pue. Mexico. Phone: +52 (22) Fax: +52 (22) / +52 (22) www-elec.inaoep.mx/wsh-cas/main.html Las Cruces, New Mexico The symposium will include all aspects of theory, design, implementation, testing, and application of analog, digital, and microwave circuits and systems. In addition to the technical program, the 42nd Midwest Symposium on Circuits and Systems will feature recreational tours to Carlsbad Caverns, White Sands Missile Range, and Ciudad Juarez, Mexico. On Tuesday, August 10, 1999, an evening banquet will take place at the New Mexico Farm and Ranch Museum, featuring grand entertainment of singing mariachis and authentic food from the Southwest. Jaime Ramírez-Angulo, General Chair New Mexico State University (505) Please see the MWSCAS homepage for complete and up-to-date information. SCS 99 International Symposium on Signals, Circuits & Systems July 6 7, 1999 Iasi, Romania The fourth biannual International Symposium on Signals, Circuits and Systems will be hosted by the Faculty of Electronics and Telecommunications, Technical University Gh. Asachi. Iasi, the Romanian city of seven hills, is one of the oldest cities in Romania and its oldest academic center. It is located in the northeast part of the country and can be reached from Bucharest in 5 hours by train or in one hour by plane.a post-symposium one-day trip in a neighboring region well known for its wonderful monasteries as well as a wine tasting will be organized. Conference Chairman: Dimitrie Alexa Paul M. Furth, Technical Program Chair Midwest Symposium on Circuits and Systems The Klipsch School of Electrical and Computer Engineering Thomas and Brown Hall, Rm 106, MSC 3 0 New Mexico State University Las Cruces, NM USA New Mexico ECCTD 99 European Conference on Circuit Theory and Design August 29 September 2, 1999 Stresa, Italy Conference Chairman: Pier Paolo Civalleri Dipartimento di Elettronica - Politecnico di Torino Corso Duca degli Abruzzi, 24 I Torino, Italy Phone: Fax: Technical Program Chairman: Claudio Beccari Dipartimento di Elettronica - Politecnico di Torino Corso Duca degli Abruzzi, 24 I Torino, Italy Phone: Fax: Mexico ECCTD 99 Organizing Secretariat CCI - Centro Congressi Internazionale srl Corso F. Ferrucci 6 I Torino, Italy Phone: Fax: For further information, visit our web site: Places Places Places Places Places Places Places Places Places Places Places Places Places Places Italy Further information: ~mrs8n/scs.html Address for correspondence: Adriana Sirbu SCS 99 International Symposium Faculty of Electronics and Telecommunications Bd. Copou 11 Iasi 6600, Romania Phone: Romania CALL FOR PAPERS Visual Communications and Image Processing 2000 June 20 23, 2000 University of Western Australia Perth, Australia In cooperation with: IEEE CAS, IE Australia Conference Chairs: King N. Ngan, Univ. of Western Australia Thomas Sikora, Heinrich-Hertz Institute Ming-Ting Sun, Univ. of Washington Visual communication has become an important engineering area that attracts interdisciplinary research interest and has led to significant developments in technology and science. This conference is designed as a forum for presenting important research results. Authors Schedule: Abstract Due: November 9, 1999 Notification of Acceptance: February 29, 2000 Manuscript Due: March 28, 2000 Early notification of acceptance will be placed on the SPIE Web site the week of February 15, 2000 at: Instructions for submitting abstracts can be found at URL: forms/vc00_submission_form.html For further information: Australia Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places 29

30 Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN November 7 11, 1999 San José, California The rapid progress in process technology development, combined with the expanding diversity of information processing applications, is placing enormous demands on CAD tool development. ICCAD-99 offers a place for CAD developers and VLSI designers to meet and exchange ideas about problems and solutions in the era of system-on-a-chip. Founded in 1982, ICCAD is an annual show focusing on information technology for computeraided design professionals and engineers. The conference includes programs, workshops, tutorials, and panels highlighting the latest developments in computer-aided design. Products and technologies in the area of computer-aided design are presented during the conference. The four-day show targets electronic engineers, computer-aided design professionals, buyers and end-users. CONFERENCE CHAIR Jacob White Massachusetts Institute of Technology PROGRAM CHAIR Ellen M. Sentovich Cadence Berkeley Labs PROGRAM VICE CHAIR Rolf Ernst Technical University of Braunschweig Please direct all correspondence to: ICCAD-99 Publications Department MP Associates, Inc Spine Rd., Suite A Boulder, CO Telephone: (303) Fax: (303) ICCAD s Home Page: NDES 99 San José ISLPED 99 International Symposium on Low Power Electronics and Design San Diego, California August 16 17, Sponsored by: ACM SIGDA and IEEE/CAS with technical support by the Electron Devices The International Symposium on Low Power Electronics and Design (ISLPED) is the premier forum for presentation of recent advances in all aspects of low power designs and technologies, ranging from process and circuit technologies, to simulation and synthesis tools, and to system-level design and optimization. General Chair: Farid N. Najm Univ. of Illinois at Urbana-Champaign David Blaauw, ISLPED 99 Program Co-Chair Motorola, Inc East Courtyard Drive Bridgepint Plaza 1, MD: F30B Austin, TX, Tel: ICECS 6TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS September 5 8, 1999 Coral Beach Hotel & Resort Pafos, CYPRUS The IEEE International Conference on Electronics, Circuits and Systems will include regular sessions; special sessions on emerging electronics, circuits and systems topics; plenary sessions on selected advanced aspects of the theory, design, and applications of electronics, circuits and systems; and short courses given by experts in the specific state-of-the-art subject areas. General Chair Dr. Odysseas Koufopavlou University of Patras Tech. Program Chair Dr. Thanos Stouraitis University of Patras Send inquiries to: ICECS 99 Secretariat Electrical & Computer Engineering Dept. University of Patras, Patras 26500, Greece Tel: , Fax: For up-to-date information: Cyprus NONLINEAR DYNAMICS OF ELECTRONIC SYSTEMS 1999 An International Specialist Workshop The seventh annual workshop on Nonlinear Dynamics of Electronic Systems (NDES 99) will take place at Hotel Griffen in Roenne on the Danish Island of Bornholm in Denmark on July 15 17, 1999 The workshop shall bring together specialists in mathematical, natural and engineering sciences in order to provide an opportunity to meet in a low-cost informal setting to address new theoretical and practical results, novel analysis and design methods in nonlinear dynamic systems and circuits and to discuss open problems in nonlinear science. General Chairman: Erik Lindberg Department of Information Technology Electronics and Signal Processing 344 Technical University of Denmark DK 2800 Lyngby, Denmark Technical Chairman: Wolfgang Schwarz Technical University of Dresden Faculty of Electrical Engineering / IEE Mommsenstr. 13 D Dresden, Germany For further information: Denmark Jason Cong, ISLPED 99 Program Co-Chair Computer Science Department Univ. of California, Los Angeles 4711 Boelter Hall Los Angeles, CA Tel: Call for Participation San Diego IEEE Circuits and Systems Workshop on Mixed-Signal Integrated Circuit Design in Cooperation with the Solid-State Circuits December 1 3, 1999 Hyatt Regency Long Beach Long Beach, California The IEEE Circuits and Systems is sponsoring the above-mentioned workshop to promote research activity as well as dissemination of technical information in the field of mixed-signal integrated circuit design. The workshop will combine presentations by invited experts in the field from academia and industry, with panel and informal discussions. Prof. Hari C. Reddy, General Chair Dr. Geert De Veirman, General Co-Chair Prof. Phil Allen, General Co-Chair For details and registration, please check the web site or contact one of the following: Professor Hari C. Reddy Department of Electrical Engineering California State University, Long Beach 1250 Bellflower Blvd Long Beach, CA Phone: (562) Fax: (562) Dr. Geert De Veirman Senior Principal Engineer Silicon Systems, Inc. Texas Instruments Storage Products Group Myford Road, MS C-100 Tustin, CA Phone: (714) Fax: (714) Because the number of participants in the workshop is limited, early registration is highly encouraged. Long Beach Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places Places

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