Spartan-6 FPGA Configurable Logic Block

Transcription

1 Spartan- FPGA Configurable Logic Block Spartan- User GuideFPGA CLB [optional] [optional]

2 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "ocumentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the ocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the ocumentation. Xilinx reserves the right, at its sole discretion, to change the ocumentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the ocumentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. THE OCUMENTATION IS ISCLOSE TO YOU AS-IS WITH NO WARRANTY OF ANY KIN. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIE, OR STATUTORY, REGARING THE OCUMENTATION, INCLUING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIR-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEUENTIAL, INIRECT, EXEMPLARY, SPECIAL, OR INCIENTAL AMAGES, INCLUING ANY LOSS OF ATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE OCUMENTATION Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Revision History The following table shows the revision history for this document. ate Version Revision 0/24/ Initial Xilinx release. Spartan- FPGA CLB User Guide

3 Table of Contents Revision History Preface: About This Guide Additional ocumentation Additional Support Resources Spartan- FPGA CLB CLB Overview Slice escription CLB / Slice Timing Models Slice ( and Storage Element) Timing Models Slice istributed RAM Timing Model (SLIM only) Slice L Timing Model (SLIM only) Slice Carry-Chain Timing Model (SLIM and SLIL only) CLB Primitives istributed RAM Primitives Shift Registers (Ls) Primitive Other Shift Register Applications Multiplexer Primitives Carry Chain Primitive Spartan- FPGA CLB User Guide 3

4 4 Spartan- FPGA CLB User Guide

5 Preface About This Guide Additional ocumentation This guide serves as a technical reference describing the Spartan - FPGA configurable logic blocks (CLBs). Usually, the logic synthesis software assigns the CLB resources without system designer intervention. It can be advantageous for the designer to understand certain CLB details, including the varying capabilities of the look-up tables (s), the physical direction of the carry propagation, the number and distribution of the available flip-flops, and the availability of the very efficient shift registers. This guide describes these and other features of the CLB in detail. The following documents are also available for download at Spartan- Family Overview This overview outlines the features and product selection of the Spartan- family. Spartan- FPGA ata Sheet: C and Switching Characteristics This data sheet contains the C and switching characteristic specifications for the Spartan- family. Spartan- FPGA Packaging and Pinout Specifications This specification includes the tables for device/package combinations and maximum I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications. Spartan- FPGA Configuration User Guide This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques. Spartan- FPGA SelectIO Resources User Guide This guide describes the SelectIO resources available in all Spartan- devices. Spartan- FPGA Clocking Resources User Guide This guide describes the clocking resources available in all Spartan- devices, including the CMs and PLLs. Spartan- FPGA Block RAM Resources User Guide This guide describes the Spartan- device block RAM capabilities. Spartan- FPGA GTP Transceivers User Guide This guide describes the GTP transceivers available in the Spartan- LXT FPGAs. Spartan- FPGA CLB User Guide

6 Preface: About This Guide Spartan- FPGA SP48A1 Slice User Guide This guide describes the architecture of the SP48A1 slice in Spartan- FPGAs and provides configuration examples. Spartan- FPGA Memory Controller User Guide This guide describes the Spartan- FPGA memory controller block, a dedicated embedded multi-port memory controller that greatly simplifies interfacing Spartan- FPGAs to the most popular memory standards. Spartan- FPGA PCB esigner s Guide This guide provides information on PCB design for Spartan- devices, with a focus on strategies for making design decisions at the PCB and interface level. Additional Support Resources To search the database of silicon and software questions and answers or to create a technical support case in WebCase, see the Xilinx website at: Spartan- FPGA CLB User Guide

7 Spartan- FPGA CLB CLB Overview The Configurable Logic Blocks (CLBs) are the main logic resources for implementing sequential as well as combinatorial circuits. Each CLB element is connected to a switch matrix for access to the general routing matrix (shown in Figure 1). A CLB element contains a pair of slices. These two slices do not have direct connections to each other, and each slice is organized as a column. For each CLB, the slice in the bottom of the CLB is labeled as SLI(0), and the slice in the top of the CLB is labeled as SLI(1). X-Ref Target - Figure 1 COUT CLB Slice(1) Switch Matrix Slice(0) CIN ug384_01_ Figure 1: Arrangement of Slices within the CLB The Xilinx tools designate slices with the following definitions. An X followed by a number identifies the position of each slice in a pair as well as the column position of the slice. The X number counts slices starting from the bottom in sequence 0, 1 (the first CLB column); 2, 3 (the second CLB column); etc. A Y followed by a number identifies a row of slices. The number remains the same within a CLB, but counts up in sequence from one CLB row to the next CLB row, starting from the bottom. Figure 2 shows four CLBs located in the bottom-left corner of the die. Spartan- FPGA CLB User Guide 7

8 X-Ref Target - Figure 2 COUT COUT CLB SLIX X1Y1 CLB SLIX X3Y1 Slice X0Y1 Slice X2Y1 CIN CIN CLB COUT SLIX X1Y0 CLB COUT SLIX X3Y0 Slice X0Y0 Slice X2Y0 ug384_02_ Figure 2: Row and Column Relationship between CLBs and Slices Slice escription Every slice contains four logic-function generators (or look-up tables, s) and eight storage elements. These basic elements are used by all slices to provide logic and ROM functions. Some slices, called SLILs, also contain an arithmetic carry structure that can be concatenated vertically up through the slice column, and wide-function multiplexers. The SLIMs contain the carry structure, multiplexers, and s for use as 4-bit distributed RAM and as variable-length shift registers (maximum 32-bit). Each column of CLBs contain two slice columns. One column is a SLIX column, the other column alternates between SLIL and SLIMs. Thus, approximately 0% of the available slices are of type SLIX, while 2% each are SLIL and SLIMs. The XCSLX4 does not have SLILs (Table 2). SLIM (shown in Figure 3) represents a superset of elements and connections found in all slices. SLIL is shown in Figure 4. SLIX is shown in Figure. All eight,, and inputs are driven by common control inputs. 8 Spartan- FPGA CLB User Guide

9 X-Ref Target - Figure 3 COUT I :1 X I2 A:A1 WA:WA1 RAM ROM I1 PRAM4 PRAM32 SPRAM4 SPRAM32 L1 L32 WA8 WA7 MC31 CARRY4 INIT0 INIT1 MC31 CY XOR MC31 CY XOR X FF LATCH AN2L OR2L INIT0 INIT1 MUX CI C:C1 CX I2 A:A1 WA:WA1 RAM ROM I1 PRAM4 PRAM32 SPRAM4 SPRAM32 L1 L32 WA8 WA7 MC31 INIT0 INIT1 C F7 CY XOR F7 CY XOR CX FF LATCH AN2L OR2L INIT0 INIT1 C CMUX C BI B:B1 BX I2 A:A1 WA:WA1 RAM ROM I1 PRAM4 PRAM32 SPRAM4 SPRAM32 L1 WA8 L32 WA7 MC31 INIT0 INIT1 B F8 CY XOR F8 CY XOR BX FF LATCH AN2L OR2L INIT0 INIT1 B BMUX B AI A:A1 I2 A:A1 WA:WA1 RAM ROM I1 PRAM4 PRAM32 SPRAM4 SPRAM32 L1 L32 WA8 WA7 MC31 INIT0 INIT1 A F7 CY XOR F7 CY XOR AX FF LATCH AN2L OR2L INIT0 INIT1 A AMUX A AX 1 CIN ug384_03_ Figure 3: iagram of SLIM Spartan- FPGA CLB User Guide 9

10 X-Ref Target - Figure 4 COUT :1 X A:A1 CARRY4 INIT0 INIT1 CY XOR CY XOR X FF LATCH AN2L OR2L INIT0 INIT1 MUX C:C1 A:A1 INIT0 INIT1 C F7 CY XOR C CMUX CX F7 CY XOR CX FF LATCH AN2L OR2L INIT0 INIT1 C B:B1 A:A1 INIT0 INIT1 B F8 CY XOR B BMUX BX F8 CY XOR BX FF LATCH AN2L OR2L INIT0 INIT1 B A:A1 A:A1 INIT0 INIT1 A F7 CY XOR A AMUX F7 CY XOR AX FF LATCH AN2L OR2L INIT0 INIT1 A 1 AX CIN ug384_04_ Figure 4: iagram of SLIL 10 Spartan- FPGA CLB User Guide

11 X-Ref Target - Figure :1 X A:A1 INIT0 INIT1 X FF LATCH AN2L OR2L INIT0 INIT1 MUX C:C1 A:A1 INIT0 INIT1 C C CMUX CX CX FF LATCH AN2L OR2L INIT0 INIT1 C B:B1 A:A1 INIT0 INIT1 B B BMUX BX BX FF LATCH AN2L OR2L INIT0 INIT1 B A:A1 A:A1 INIT0 INIT1 A A AMUX AX FF LATCH AN2L OR2L INIT0 INIT1 A AX ug384_0_ Figure : iagram of SLIX Spartan- FPGA CLB User Guide 11

12 CLB/Slice Configurations Table 1 summarizes the logic resources in one CLB. Each CLB or slice can be implemented in one of the configurations listed. Table 1: Logic Resources in One CLB Slices s Flip-Flops Arithmetic and Carry Chains (2) istributed RAM (1) Shift Registers (1) bits 128 bits Notes: 1. SLIM only, SLIL and SLIX do not have distributed RAM or shift registers. 2. SLIM and SLIL only. Table 2 shows the available CLB resources for the Spartan- FPGAs. The ratio between the number of -input s and logic cells is 1.. This reflects the increased capability of the new -input architecture compared to traditional 4-input s. Table 2: Spartan- FPGA Logic Resources evice Logic Cells Total Slices SLIMs SLILs SLIXs Number of -Input s Maximum istributed RAM (Kb) Shift Registers (Kb) Number of Flip-Flops XCSLX4 3, , ,800 XCSLX9 9,12 1, , ,440 XCSLX1 14,79 2, ,139 9, ,224 XCSLX2 24,01 3, ,879 1, ,04 XCSLX4 43,1,822 1,02 1,809 3,411 27, ,7 XCSLX7 74,37 11,2 2,78 3,03,831 4, ,29 XCSLX ,21 1,822 3,904 4,007 7,911 3, ,7 XCSLX10 147,443 23,038,420,099 11,19 92,12 1, ,304 XCSLX2T 24,01 3, ,879 1, ,04 XCSLX4T 43,1,822 1,02 1,809 3,411 27, ,7 XCSLX7T 74,37 11,2 2,78 3,03,831 4, ,29 XCSLX100T 101,21 1,822 3,904 4,007 7,911 3, ,7 XCSLX10T 147,443 23,038,420,099 11,19 92,12 1, ,304 Look-Up Table () The function generators in Spartan- FPGAs are implemented as six-input look-up tables (s). There are six independent inputs (A inputs - A1 to A) and two independent outputs ( and ) for each of the four function generators in a slice (A, B, C, and ). The function generators can implement any arbitrarily defined six-input Boolean function. Each function generator can also implement two arbitrarily defined five-input Boolean functions, as long as these two functions share common inputs. Only the output of the function generator is used when a six-input function is implemented. Both and are used for each of the five-input function generators implemented. In this case, A is driven High by the software. The propagation delay through a is independent of the function 12 Spartan- FPGA CLB User Guide

13 implemented, or whether one six-input or two five-input generators are implemented. Signals from the function generators can exit the slice (through A, B, C, output for or AMUX, BMUX, CMUX, MUX output for ), enter the XOR dedicated gate from an output (see Fast Lookahead Carry Logic), enter the carry-logic chain from an output (see Fast Lookahead Carry Logic), enter the select line of the carry-logic multiplexer from an output (see Fast Lookahead Carry Logic), feed the input of the storage element, or go to F7AMUX/F7BMUX from an output. In addition to the basic s, SLIL and SLIM contain three multiplexers (F7AMUX, F7BMUX, and F8MUX). These multiplexers are used to combine up to four function generators to provide any function of seven or eight inputs in a slice. F7AMUX and F7BMUX are used to generate seven input functions from slice A and B, or C and, while F8MUX is used to combine all slices to generate eight input functions. Functions with more than eight inputs can be implemented using multiple slices. There are no direct connections between slices to form function generators greater than eight inputs within a CLB or between slices. Storage Elements Each slice has eight storage elements. There are four storage elements in a slice that can be configured as either edge-triggered -type flip-flops or level-sensitive latches. The input can be driven directly by a output via AFFMUX, BFFMUX, CFFMUX or FFMUX, or by the BYPASS slice inputs bypassing the function generators via AX, BX, CX, or X input. When configured as a latch, the latch is transparent when the is Low. In Spartan- devices, there are four additional storage elements that can only be configured as edge-triggered -type flip-flops. The input can be driven by the output of the. When the original 4 storage elements are configured as latches, these 4 additional storage elements can not be used. The control signals clock (), clock enable (), and set/reset () are common to all storage elements in one slice. When one flip-flop in a slice has or enabled, the other flip-flops used in the slice will also have or enabled by the common signal. Only the signal has independent polarity but applies it to all eight storage elements. Any inverter placed on the clock signal is automatically absorbed. The and signals are active High. All flip-flop and latch primitives have and non- versions. The signal forces the storage element into the state specified by the attribute INIT1 or INIT0. INIT1 forces a logic High at the storage element output when is asserted, while INIT0 forces a logic Low at the storage element output (see Table 3). Table 3: Truth Table when using INIT INIT Function 0 INIT0 (default) No Logic Change 1 INIT0 (default) 0 0 INIT1 No Logic Change 1 INIT1 1 Spartan- FPGA CLB User Guide 13

14 Figure shows both the register only and the register/latch configuration in a slice, both are available. X-Ref Target - Figure Registers Only Registers or Latches FF FF/LATCH INIT1 INIT0 X FF LATCH INIT1 INIT0 CFF C CFF/LATCH C INIT1 INIT0 C CX FF LATCH INIT1 INIT0 C Reset Type Reset Type Sync Sync BFF Async B BFF/LATCH Async B INIT1 INIT0 B BX FF LATCH INIT1 INIT0 B AFF A AFF/LATCH A INIT1 INIT0 A AX FF LATCH INIT1 INIT0 A ug384_0_ Figure : Configuration in a Slice: 4 Registers Only and 4 Register/Latch INIT0 and INIT1 can be set individually for each storage element in a slice. The choice of synchronous (SYNC) or asynchronous (ASYNC) set/reset (TYPE) cannot be set individually for each storage element in a slice. The initial state after configuration or global initial state is defined by the same INIT attribute. The configuration options for the set and reset functionality of a register or the four storage elements capable of functioning as a latch are as follows: No set or reset Synchronous set Synchronous reset Asynchronous set (preset) Asynchronous reset (clear) 14 Spartan- FPGA CLB User Guide

15 istributed RAM and Memory (SLIM only) Multiple s in a SLIM can be combined in various ways to store more data. The function generators in SLIMs can be implemented as a distributed RAM element. RAM elements are configurable within a SLIM to implement the distributed RAM shown in Table 4. istributed RAM modules are synchronous (write) and asynchronous (read) resources. However, a synchronous read resource can be implemented with a storage element or a flip-flop in the same slice. By placing this flip-flop, the distributed RAM performance is improved by decreasing the delay into the clock-to-out value of the flip-flop. However, an additional clock latency is added. The distributed elements share the same clock input. For a write operation, the Write Enable () input, driven by either the or pin of a SLIM, must be set High. Table 4 shows the number of s (four per slice) occupied by each distributed RAM configuration. Table 4: istributed RAM Configuration RAM Number of s escription 32 x 2 (2) 4 uad-port 32 x 2-bit RAM 32 x SP (2) 4 Simple ual-port 32 x -bit RAM 4 x 1S 1 Single-Port 4 x 1-bit RAM 4 x 1 2 ual-port 4 x 1-bit RAM 4 x 1 (3) 4 uad-port 4 x 1-bit RAM 4 x 3SP (3) 4 Simple ual-port 4 x 3-bit RAM 128 x 1S 2 Single-Port 128 x 1-bit RAM 128 x 1 4 ual-port 128 x 1-bit RAM 2 x 1S 4 Single-Port 2 x 1-bit RAM Notes: 1. S = single-port configuration; = dual-port configuration; = quad-port configuration; SP = simple dual-port configuration. 2. RAM32M is the associated primitive for this configuration. 3. RAM4M is the associated primitive for this configuration. For single-port configurations, distributed RAM has a common address port for synchronous writes and asynchronous reads. For dual-port configurations, distributed RAM has one port for synchronous writes and asynchronous reads, and another port for asynchronous reads. In simple dual-port configuration, there is no data out (read port) from the write port. For quad-port configurations, distributed RAM has one port for synchronous writes and asynchronous reads, and three additional ports for asynchronous reads. In single-port mode, read and write addresses share the same address bus. In dual-port mode, one function generator is connected with the shared read and write port address. The second function generator has the A inputs connected to a second read-only port address and the WA inputs shared with the first read/write port address. Spartan- FPGA CLB User Guide 1

16 Figure 7 through Figure 1 illustrate various example distributed RAM configurations occupying one SLIM. When using x2 configuration (RAM32X2), A and WA are driven High by the software to keep and independent. X-Ref Target - Figure 7 RAM 32X2 I[1] I[0] AR[4:0] W (X) (AI/BI/CI/I) [:1] () () PRAM32 I1 I2 A[:1] WA[:1] O[0] O[1] PRAM32 ARC[4:0] C[:1] I1 I2 A[:1] WA[:1] OC[0] OC[1] ARB[4:0] B[:1] PRAM32 I1 I2 A[:1] WA[:1] OB[0] OB[1] ARA[4:0] A[:1] PRAM32 I1 I2 A[:1] WA[:1] OA[0] OA[1] ug384_07_ Figure 7: istributed RAM (RAM32X2) 1 Spartan- FPGA CLB User Guide

17 X-Ref Target - Figure 8 RAM 32XSP unused unused WAR[:1] WAR[] = 1 W [:1] () () I1 I2 A[:1] WA[:1] PRAM32 ATA[1] ATA[2] RAR[:1] RAR[] = 1 C[:1] PRAM32 I1 I2 A[:1] WA[:1] O[1] O[2] ATA[3] ATA[4] B[:1] PRAM32 I1 I2 A[:1] WA[:1] O[3] O[4] ATA[] ATA[] A[:1] PRAM32 I1 I2 A[:1] WA[:1] O[] O[] ug384_08_ Figure 8: istributed RAM (RAM32XSP) Spartan- FPGA CLB User Guide 17

18 X-Ref Target - Figure 9 RAM4X1S (X) I1 SPRAM4 O A[:0] W ([:1]) () (/) A[:1] WA[:1] Registered ug384_09_ Figure 9: istributed RAM (RAM4X1S) If four single-port 4 x 1-bit modules are built, the four RAM4X1S primitives can occupy a SLIM, as long as they share the same clock, write enable, and shared read and write port address inputs. This configuration equates to 4 x 4-bit single-port distributed RAM. X-Ref Target - Figure 10 RAM4X1 (X) I1 PRAM4 SPO A[:0] W ([:1]) () (/) A[:1] WA[:1] Registered I1 PRAM4 PO PRA[:0] (C[:1]) A[:1] WA[:1] Registered ug384_10_ Figure 10: istributed RAM (RAM4X1) If two dual-port 4 x 1-bit modules are built, the two RAM4X1 primitives can occupy a SLIM, as long as they share the same clock, write enable, and shared read and write port address inputs. This configuration equates to 4 x 2-bit dual-port distributed RAM Spartan- FPGA CLB User Guide

19 X-Ref Target - Figure 11 RAM4X1 I (X) I1 PRAM4 O AR W ([:1]) () () A[:1] WA[:1] Registered I1 PRAM4 OC ARC (C[:1]) A[:1] WA[:1] Registered I1 PRAM4 OB ARB (B[:1]) A[:1] WA[:1] Registered I1 PRAM4 OA ARA (A[:1]) A[:1] WA[:1] Registered ug384_11_ Figure 11: istributed RAM (RAM4X1) Spartan- FPGA CLB User Guide 19

20 X-Ref Target - Figure 12 RAM 4X3SP unused unused WAR[:1] W [:1] () () I1 I2 A[:1] WA[:1] PRAM32 ATA[1] RAR[:1] C[:1] PRAM32 I1 I2 A[:1] WA[:1] O[1] ATA[2] B[:1] PRAM32 I1 I2 A[:1] WA[:1] O[2] ATA[3] A[:1] PRAM32 I1 I2 A[:1] WA[:1] O[3] ug384_12_ Figure 12: istributed RAM (RAM4X3SP) Implementation of distributed RAM configurations with depth greater than 4 requires the usage of wide-function multiplexers (F7AMUX, F7BMUX, and F8MUX) Spartan- FPGA CLB User Guide

21 X-Ref Target - Figure 13 A (CX) RAM128X1S (X) I1 SPRAM4 A[:0] W [:0] 7 () (/) A[:1] WA[7:1] 0 [:0] 7 SPRAM4 I1 A[:1] WA[7:1] F7BMUX Registered ug384_13_ Figure 13: istributed RAM (RAM128X1S) If two single-port 128 x 1-bit modules are built, the two RAM128X1S primitives can occupy a SLIM, as long as they share the same clock, write enable, and shared read and write port address inputs. This configuration equates to 128 x 2-bit single-port distributed RAM. Spartan- FPGA CLB User Guide 21

22 X-Ref Target - Figure 14 RAM128X1 A (CX) X I1 PRAM4 A[:0] W 7 () () A[:1] WA[7:1] SPO 7 PRAM4 I1 A[:1] WA[7:1] F7BMUX Registered I1 PRAM4 PRA[:0] 7 A[:1] WA[7:1] PO AX 7 PRAM4 I1 A[:1] WA[7:1] F7AMUX Registered ug384_14_ Figure 14: istributed RAM (RAM128X1) 22 Spartan- FPGA CLB User Guide

23 X-Ref Target - Figure 1 RAM2X1S I1 SPRAM4 A[7:0] W 8 () (/) A[:1] WA[8:1] A (CX) I1 SPRAM4 F7BMUX 8 A[:1] WA[8:1] A7 (BX) O I1 SPRAM4 F8MUX Registered 8 A[:1] WA[8:1] A (AX) I1 SPRAM4 F7AMUX 8 A[:1] WA[8:1] ug384_1_ Figure 1: istributed RAM (RAM2X1S) istributed RAM configurations larger than the examples provided in Figure 7 through Figure 1 require more than one SLIM. There are no direct connections between slices to form larger distributed RAM configurations within a CLB or between slices. istributed RAM ata Flow Synchronous Write Operation The synchronous write operation is a single clock-edge operation with an active-high write-enable () feature. When is High, the input () is loaded into the memory location at address A. Asynchronous Read Operation Spartan- FPGA CLB User Guide 23

24 The output is determined by the address A (for single-port mode output/spo output of dual-port mode), or address PRA (PO output of dual-port mode). Each time a new address is applied to the address pins, the data value in the memory location of that address is available on the output after the time delay to access the. This operation is asynchronous and independent of the clock signal. istributed RAM Summary Single-port and dual-port modes are available in SLIMs. A write operation requires one clock edge. Read operations are asynchronous ( output). The data input has a setup-to-clock timing specification. Read Only Memory (ROM) Each function generator can implement a 4 x 1-bit ROM. Three configurations are available: ROM4x1, ROM128x1, and ROM2x1. ROM contents are loaded at each device configuration. Table shows the number of s occupied by each ROM configuration. Table : ROM Configuration ROM Number of s 4 x x x 1 4 Shift Registers (SLIM only) A SLIM function generator can also be configured as a 32-bit shift register without using the flip-flops available in a slice. Used in this way, each can delay serial data anywhere from one to 32 clock cycles. The shiftin (I1 pin) and shiftout 31 (MC31 pin) lines cascade s to form larger shift registers. The four s in a SLIM are thus cascaded to produce delays up to 128 clock cycles. It is also possible to combine shift registers across more than one SLIM. Note that there are no direct connections between slices to form longer shift registers, nor is the MC31 output at B/C/ available. The resulting programmable delays can be used to balance the timing of data pipelines. Applications requiring delay or latency compensation use these shift registers to develop efficient designs. Shift registers are also useful in synchronous FIFO and content addressable memory (CAM) designs. The write operation is synchronous with a clock input () and an optional clock enable (). A dynamic read access is performed through the -bit address bus, A[4:0]. The LSB of the is unused and the software automatically ties it to a logic High. The configurable shift registers cannot be set or reset. The read is asynchronous; however, a storage element or flip-flop is available to implement a synchronous read. In this case, the clock-to-out of the flip-flop determines the overall delay and improves performance. However, one additional cycle of clock latency is added. Any of the 32 bits can be read out asynchronously (at the outputs) by varying the -bit address. This capability is useful in creating smaller shift registers (less than 32 bits). For example, when building a 13-bit shift register, simply set the address to the 13 th bit. Figure 1 is a logic block diagram of a 32-bit shift register Spartan- FPGA CLB User Guide

25 X-Ref Target - Figure 1 SHIFTIN (MC31 of Previous ) LC32E SHIFTIN () A[4:0] (AX) (A[:2]) L32 I1 MC31 A[:2] SHIFTOUT (31) () (/) () (A) Registered ug384_1_ Figure 1: 32-bit Shift Register Configuration Figure 17 illustrates an example shift register configuration occupying one function generator. X-Ref Target - Figure 17 SHIFTIN () 32-bit Shift Register SHIFTOUT(31) Address (A[4:0]) MUX ug384_17_ Figure 17: Representation of a Shift Register Figure 18 shows two 1-bit shift registers. The example shown can be implemented in a single. Spartan- FPGA CLB User Guide 2

26 X-Ref Target - Figure 18 L1 SHIFTIN1 (AX) I1 A[3:0] 4 A[:2] L1 SHIFTIN2 (AI) I2 4 A[:2] MC31 ug384_18_ Figure 18: ual 1-bit Shift Register Configuration As mentioned earlier, an additional output (MC31) and a dedicated connection between shift registers allows connecting the last bit of one shift register to the first bit of the next, without using the output. Longer shift registers can be built with dynamic access to any bit in the chain. The shift register chaining and the F7AMUX, F7BMUX, and F8MUX multiplexers allow up to a 128-bit shift register with addressable access to be implemented in one SLIM. Figure 19 through Figure 21 illustrate various example shift register configurations that can occupy one SLIM. X-Ref Target - Figure 19 L32 SHIFTIN () I1 A[:0] () (/) A[:2] MC31 A (AX) () I1 L32 F7AMUX (A) Registered A[:2] MC31 (MC31) SHIFTOUT (3) ug384_19_ Figure 19: 4-bit Shift Register Configuration 2 Spartan- FPGA CLB User Guide

27 X-Ref Target - Figure 20 CX (A) L32 SHIFTIN () I1 A[:0] () (/) A[:2] MC31 F7BMUX BX (A) (BMUX) () F8MUX (B) Registered L32 I1 A[:2] MC31 AX (A) I1 A[:2] L32 Not Used F7AMUX UG384_20_ Figure 20: 9-bit Shift Register Configuration Spartan- FPGA CLB User Guide 27

28 X-Ref Target - Figure 21 L32 SHIFTIN () I1 A[:0] () (/) A[:2] MC31 CX (A) I1 L32 F7BMUX A[:2] I1 MC31 L32 BX (A) F8MUX (BMUX) (B) () Registered A[:2] MC31 AX (A) I1 L32 F7AMUX A[:2] MC31 (MC31) SHIFTOUT (127) ug384_21_ Figure 21: 128-bit Shift Register Configuration It is possible to create shift registers longer than 128 bits across more than one SLIM. However, there are no direct connections between slices to form these shift registers. Shift Register ata Flow Shift Operation The shift operation is a single clock-edge operation, with an active-high clock enable feature. When enable is High, the input () is loaded into the first bit of the shift register. Each bit is also shifted to the next highest bit position. In a cascadable shift register configuration, the last bit is shifted out on the M31 output. The bit selected by the -bit address port (A[4:0]) appears on the output. ynamic Read Operation The output is determined by the -bit address. Each time a new address is applied to the -input address pins, the new bit position value is available on the output after the time 28 Spartan- FPGA CLB User Guide

29 delay to access the. This operation is asynchronous and independent of the clock and clock-enable signals. Static Read Operation If the -bit address is fixed, the output always uses the same bit position. This mode implements any shift-register length from 1 to 1 bits in one. The shift register length is (N+1), where N is the input address (0 31). The output changes synchronously with each shift operation. The previous bit is shifted to the next position and appears on the output. Shift Register Summary A shift operation requires one clock edge. ynamic-length read operations are asynchronous ( output). Static-length read operations are synchronous ( output). The data input has a setup-to-clock timing specification. In a cascadable configuration, the 31 output always contains the last bit value. The 31 output changes synchronously after each shift operation. Multiplexers Function generators and associated multiplexers in SLIL or SLIM can implement the following: 4:1 multiplexers using one 8:1 multiplexers using two s 1:1 multiplexers using four s These wide input multiplexers are implemented in one level or logic (or ) using the dedicated F7AMUX, F7BMUX, and F8MUX multiplexers. These multiplexers allow combinations of up to four s in a slice. esigning Large Multiplexers 4:1 Multiplexer Each can be configured into a 4:1 MUX. The 4:1 MUX can be implemented with a flipflop in the same slice. Up to four 4:1 MUXes can be implemented in a slice, as shown in Figure 22. Spartan- FPGA CLB User Guide 29

30 X-Ref Target - Figure 22 SLI () 4:1 MUX SEL [1:0], ATA [3:0] Input ([:1]) A[:1] () Registered (C) 4:1 MUX SEL C [1:0], ATA C [3:0] Input (C[:1]) A[:1] (C) Registered (B) 4:1 MUX SEL B [1:0], ATA B [3:0] Input (B[:1]) A[:1] (B) Registered (A) 4:1 MUX SEL A [1:0], ATA A [3:0] Input (A[:1]) A[:1] (A) Registered () ug384_22_ :1 Multiplexer Figure 22: Four 4:1 Multiplexers in a Slice Each SLIL or SLIM has an F7AMUX and an F7BMUX. These two muxes combine the output of two s to form a combinatorial function up to 13 inputs (or an 8:1 MUX). Up to two 8:1 MUXes can be implemented in a slice, as shown in Figure Spartan- FPGA CLB User Guide

31 X-Ref Target - Figure 23 SLI SEL [1:0], ATA [3:0] Input (1) ([:1]) A[:1] F7BMUX (CMUX) 8:1 MUX (1) SEL C [1:0], ATA C [3:0] Input (1) (C[:1]) A[:1] (C) Registered SELF7(1) (CX) () SEL B [1:0], ATA B [3:0] Input (2) (B[:1]) A[:1] F7AMUX (AMUX) 8:1 MUX (2) SEL A [1:0], ATA A [3:0] Input (2) (A[:1]) A[:1] (A) Registered SELF7(2) (AX) ug384_23_ Figure 23: Two 8:1 Multiplexers in a Slice 1:1 Multiplexer Each SLIL or SLIM has an F8MUX. F8MUX combines the outputs of F7AMUX and F7BMUX to form a combinatorial function up to 27 inputs (or a 1:1 MUX). Only one 1:1 MUX can be implemented in a slice, as shown in Figure 24. Spartan- FPGA CLB User Guide 31

32 X-Ref Target - Figure 24 SLI SEL [1:0], ATA [3:0] Input ([:1]) A[:1] F7BMUX SEL C [1:0], ATA C [3:0] Input (C[:1]) A[:1] F8MUX SELF7 (CX) (BMUX) (B) 1:1 MUX Registered SEL B [1:0], ATA B [3:0] Input (B[:1]) A[:1] F7AMUX SEL A [1:0], ATA A [3:0] Input (A[:1]) A[:1] SELF7 SELF8 (AX) (BX) () ug384_24_ Figure 24: 1:1 Multiplexer in a Slice It is possible to create multiplexers wider than 1:1 across more than one SLIM. However, there are no direct connections between slices to form these wide multiplexers. Fast Lookahead Carry Logic In addition to function generators, SLIM and SLIL (but not SLIX) contain dedicated carry logic to perform fast arithmetic addition and subtraction in a slice. A CLB has one carry chain, as shown in Figure 1. The carry chains are cascadable to form wider add/subtract logic, as shown in Figure 2. The carry chain in the Spartan- device is running upward and has a height of four bits per slice. For each bit, there is a carry multiplexer (MUXCY) and a dedicated XOR gate for adding/subtracting the operands with a selected carry bits. The dedicated carry path and carry multiplexer (MUXCY) can also be used to cascade function generators for implementing wide logic functions. Figure 2 illustrates the carry chain with associated logic elements in a slice Spartan- FPGA CLB User Guide

33 X-Ref Target - Figure 2 COUT (To Next Slice) Carry Chain Block (CARRY4) From S3 MUXCY CO3 MUX/* From X I3 O3 MUX From C S2 MUXCY CO2 CMUX/C* From C CX I2 O2 CMUX C From B S1 MUXCY CO1 BMUX/B* From B BX I1 O1 BMUX B From A S0 MUXCY CO0 AMUX/A* From A AX I0 O0 AMUX A CYINIT CIN 0 1 CIN (From Previous Slice) *Can be used if unregistered/registered outputs are free. ug384_2_ Figure 2: Fast Carry Logic Path and Associated Elements The carry chains carry lookahead logic along with the function generators. There are ten independent inputs (S inputs S0 to S3, I inputs I1 to I4, CYINIT and CIN) and eight independent outputs (O outputs O0 to O3, and CO outputs CO0 to CO3). The S inputs are used for the propagate signals of the carry lookahead logic. The propagate signals are sourced from the output of a function generator. The I inputs are used for the generate signals of the carry lookahead logic. The generate signals are sourced from either the output of a function generator or the BYPASS input (AX, BX, CX, or X) of a slice. The former input is used to create a multiplier, while the latter is used to create an adder/accumulator. CYINIT is the CIN of the first bit in a carry chain. The CYINIT value can be 0 (for add), 1 (for subtract), or AX input (for the dynamic first carry bit). The CIN input is used to cascade slices to form a longer carry chain. The O outputs contain the sum of the addition/subtraction. The CO outputs compute the carry out for Spartan- FPGA CLB User Guide 33

34 CLB / Slice Timing Models each bit. CO3 is connected to COUT output of a slice to form a longer carry chain by cascading multiple slices. The propagation delay for an adder increases linearly with the number of bits in the operand, as more carry chains are cascaded. The carry chain can be implemented with a storage element or a flip-flop in the same slice. ue to the large size and complexity of Spartan- FPGAs, understanding the timing associated with the various paths and functional elements is a difficult and important task. Although it is not necessary to understand the various timing parameters to implement most designs using Xilinx software, a thorough timing model can assist advanced users in analyzing critical paths or planning speed-sensitive designs. Three timing model sections are described: Functional element diagram basic architectural schematic illustrating pins and connections Timing parameters definitions of Spartan- FPGA ata Sheet timing parameters Timing iagram - illustrates functional element timing parameters relative to each other Use the models in this chapter in conjunction with both the Xilinx Timing Analyzer software (TR) and the section on switching characteristics in the Spartan- FPGA ata Sheet. All pin names, parameter names, and paths are consistent with the post-route timing and pre-route static timing reports. Most of the timing parameters found in the section on switching characteristics are described in this chapter. All timing parameters reported in the Spartan- FPGA ata Sheet are associated with slices and CLBs. The following sections correspond to specific switching characteristics sections in the Spartan- FPGA ata Sheet: Slice ( and Storage Element) Timing Models Slice istributed RAM Timing Model (SLIM only) Slice L Timing Model (SLIM only) Slice Carry-Chain Timing Model (SLIM and SLIL only) Slice ( and Storage Element) Timing Models A simplified Spartan- FPGA slice is shown in Figure 2. Some elements of the slice are omitted for clarity. Only the elements relevant to the timing paths described in this section are shown Spartan- FPGA CLB User Guide

35 X-Ref Target - Figure 2 Inputs FF/LAT MUX X C Inputs F7BMUX C FF/LAT CMUX CX F8MUX C B Inputs B FF/LAT BMUX BX A Inputs F7AMUX B A AMUX AX FF/LAT A ug384_2_ Figure 2: Simplified Spartan- FPGA Slice Timing Parameters Table shows the general slice timing parameters for a majority of the paths in Figure 2. Spartan- FPGA CLB User Guide 3

36 Table : Slice ( and Storage Element) Timing Parameters Parameter Function escription Combinatorial elays T (1) ILO T ILO_2 T ILO_3 Sequential elays T O Flip-Flop/ Latch element T O Flip-Flop only element A/B/C/ inputs to A/B/C/ outputs A/B/C/ inputs to AMUX/CMUX outputs A/B/C/ inputs to BMUX output FF Clock () to A/B/C/ outputs FF Clock () to A/B/C/ outputs Propagation delay from the A/B/C/ inputs of the slice, through the look-up tables (s), to the A/B/C/ outputs of the slice (six-input function). Propagation delay from the A/B/C/ inputs of the slice, through the s and F7AMUX/F7BMUX to the AMUX/CMUX outputs (seven-input function). Propagation delay from the A/B/C/ inputs of the slice, through the s, F7AMUX/F7BMUX, and F8MUX to the BMUX output (eight-input function). Time after the clock that data is stable at the A/B/C/ outputs of the slice sequential elements (configured as a flip-flop). Time after the clock that data is stable at the A/B/C/ outputs of the slice sequential elements. T LO Latch Clock () to A/B/C/ outputs Setup and Hold Times for Slice Sequential Elements (2) Time after the clock that data is stable at the X/Y outputs of the slice sequential elements (configured as a latch). T I /T I Flip-Flop/ Latch element T I /T I Flip-Flop only element T /T Flip-Flop/ Latch element T /T Flip-Flop only element T /T Flip-Flop/ Latch element T /T Flip-Flop only element AX/BX/CX/X inputs AX/BX/CX/X inputs input input input input Time before/after the that data from the AX/BX/CX/X inputs of the slice must be stable at the input of the slice sequential elements (configured as a flip-flop). Time before/after the that data from the AX/BX/CX/X inputs of the slice must be stable at the input of the slice sequential elements. Time before/after the that the input of the slice must be stable at the input of the slice sequential elements (configured as a flip-flop). Time before/after the that the input of the slice must be stable at the input of the slice sequential elements. Time before/after the that the (Set/Reset) of the slice must be stable at the inputs of the slice sequential elements (configured as a flipflop). Time before/after the that the (Set/Reset) inputs of the slice must be stable at the inputs of the slice sequential elements 3 Spartan- FPGA CLB User Guide

37 Table : Slice ( and Storage Element) Timing Parameters (Cont d) Parameter Function escription Set/Reset T RPW T R F TOG Minimum Pulse Width for the (Set/Reset). Propagation delay for an asynchronous Set/Reset of the slice sequential elements. From the inputs to the A/B/C/ outputs. Toggle Frequency Maximum frequency that a CLB flip-flop can be clocked: 1 / (T CH + T CL ). Notes: 1. This parameter includes a configured as two five-input functions. 2. T XX = Setup Time (before clock edge), and T XX = Hold Time (after clock edge). Timing Characteristics Figure 27 illustrates the general timing characteristics of a Spartan- FPGA slice. X-Ref Target - Figure AX/BX/CX/X (ATA) (RESET) A/B/C/ (OUT) T O T I T O T T O ug384_27_ Figure 27: General Slice Timing Characteristics At time T O before clock event (1), the clock-enable signal becomes valid-high at the input of the slice register. At time T I before clock event (1), data from either AX, BX, CX, or X inputs become valid-high at the input of the slice register and is reflected on either the A, B, C, or pin at time T O after clock event (1). At time T before clock event (3), the signal (configured as synchronous reset) becomes valid-high, resetting the slice register. This is reflected on the A, B, C, or pin at time T O after clock event (3). Slice istributed RAM Timing Model (SLIM only) Figure 28 illustrates the details of distributed RAM implemented in a Spartan- FPGA slice. Some elements of the slice are omitted for clarity. Only the elements relevant to the timing paths described in this section are shown. Spartan- FPGA CLB User Guide 37

38 X-Ref Target - Figure 28 RAM X I input I1 I2 A[:0] WA[:0] MUX RAM CX CI C input I1 I2 A[:0] WA[:0] C CMUX RAM BX BI B input I1 I2 A[:0] WA[:0] B BMUX RAM AX AI A input I1 I2 A[:0] WA[:0] A AMUX ug384_29_ Figure 28: Simplified Spartan- FPGA SLIM istributed RAM istributed RAM Timing Parameters Table 7 shows the timing parameters for the distributed RAM in SLIM for a majority of the paths in Figure 28. Table 7: istributed RAM Timing Parameters Parameter Function escription Sequential elays for a Slice Configured as RAM (istributed RAM) T (1) SHO to A/B/C/ outputs Time after the of a write operation that the data written to the distributed RAM is stable on the A/B/C/ output of the slice. Setup and Hold Times for a Slice Configured as RAM (istributed RAM) (2) T S /T H (3) AX/BX/CX/X configured as data input (I1) Time before/after the clock that data must be stable at the AX/BX/CX/X input of the slice. T A /T A A/B/C/ address inputs Time before/after the clock that address signals must be stable at the A/B/C/ inputs of the slice (configured as RAM) Spartan- FPGA CLB User Guide

39 Table 7: istributed RAM Timing Parameters (Cont d) Parameter Function escription T WS /T WH input Time before/after the clock that the write enable signal must be stable at the input of the slice (configured as RAM). Clock T WPH T WPL T WC Minimum Pulse Width, High Minimum Pulse Width, Low Minimum clock period to meet address write cycle time. Notes: 1. This parameters includes a configured as a two-bit distributed RAM. 2. T XX = Setup Time (before clock edge), and T XX = Hold Time (after clock edge). 3. Parameter includes AI/BI/CI/I configured as a data input (I2). istributed RAM Timing Characteristics The timing characteristics of a 1-bit distributed RAM implemented in a Spartan- FPGA slice ( configured as RAM) are shown in Figure 29. X-Ref Target - Figure T WC T WPH T WPL A/B/C/ (AR) T AS 2 F 3 4 E AX/BX/CX/X (I) 1 T S X X T WS TILO T ILO ATA_OUT A/B/C/ T SHO 1 MEM(F) WRITE REA WRITE WRITE WRITE REA MEM(E) ug384_29_ Figure 29: Slice istributed RAM Timing Characteristics Clock Event 1: Write Operation uring a Write operation, the contents of the memory at the address on the AR inputs are changed. The data written to this memory location is reflected on the A/B/C/ outputs synchronously. At time T WS before clock event 1, the write-enable signal () becomes valid-high, enabling the RAM for a Write operation. At time T AS before clock event 1, the address (2) becomes valid at the A/B/C/ inputs of the RAM. Spartan- FPGA CLB User Guide 39

40 At time T S before clock event 1, the ATA becomes valid (1) at the I input of the RAM and is reflected on the A/B/C/ output at time T SHO after clock event 1. This is also applicable to the AMUX, BMUX, CMUX, MUX, and COUT outputs at time T SHO and T WOSCO after clock event 1. Clock Event 2: Read Operation All Read operations are asynchronous in distributed RAM. As long as is Low, the address bus can be asserted at any time. The contents of the RAM on the address bus are reflected on the A/B/C/ outputs after a delay of length T ILO (propagation delay through a ). The address (F) is asserted after clock event 2, and the contents of the RAM at address (F) are reflected at the output after a delay of length T ILO. Slice L Timing Model (SLIM only) Figure 30 illustrates shift register implementation in a Spartan- FPGA slice. Some elements of the slice have been omitted for clarity. Only the elements relevant to the timing paths described in this section are shown Spartan- FPGA CLB User Guide

41 X-Ref Target - Figure 30 L X I1 address A MC31 W L CX I1 C C address A MC31 L BX I1 B B address A MC31 L AX A address I1 A MC31 A MUX ug384_30_ Figure 30: Simplified Spartan- FPGA Slice L Slice L Timing Parameters Table 8 shows the SLIM L timing parameters for a majority of the paths in Figure 30. Table 8: Slice L Timing Parameters Parameter Function escription Sequential elays for a Slice Configured as an L T (1) REG to A/B/C/ outputs Time after the of a write operation that the data written to the L is stable on the A/B/C/ outputs of the slice. T (1) REG_MUX to AMUX - MUX output Time after the of a write operation that the data written to the L is stable on the MUX output of the slice. Spartan- FPGA CLB User Guide 41

42 Table 8: Slice L Timing Parameters (Cont d) Parameter Function escription T REG_M31 to MUX output via MC31 output Setup and Hold Times for a Slice Configured L (2) Time after the of a write operation that the data written to the L is stable on the MUX output via MC31 output. T WS /T WH input () Time before/after the clock that the write enable signal must be stable at the input of the slice (configured as an L). T S /T H (3) AX/BX/CX/X configured as data input (I) Time before the clock that the data must be stable at the AX/BX/CX/X input of the slice (configured as an L). Notes: 1. This parameter includes a configured as a two-bit shift register. 2. T XX = Setup Time (before clock edge), and T XX = Hold Time (after clock edge). 3. Parameter includes AI/BI/CI/I configured as a data input (I2) or two bits with a common shift. Slice L Timing Characteristics Figure 31 illustrates the timing characteristics of a 1-bit shift register implemented in a Spartan- FPGA slice (a configured as an L). X-Ref Target - Figure Write Enable () Shift_In (I) Address (A/B/C/) ata Out (A/B/C/) MSB (MC31/MUX) T WS T S T REG T ILO T ILO X T REG X X X X X X X 0 ug384_31_ Figure 31: Slice L Timing Characteristics Clock Event 1: Shift In uring a write (Shift In) operation, the single-bit content of the register at the address on the A/B/C/ inputs is changed, as data is shifted through the L. The data written to this register is reflected on the A/B/C/ outputs synchronously, if the address is unchanged during the clock event. If the A/B/C/ inputs are changed during a clock event, the value of the data at the addressable output (A/B/C/ outputs) is invalid. At time T WS before clock event 1, the write-enable signal () becomes valid-high, enabling the L for the Write operation that follows. At time T S before clock event 1 the data becomes valid (0) at the I input of the L and is reflected on the A/B/C/ output after a delay of length T REG after clock event 42 Spartan- FPGA CLB User Guide

43 1. Since the address 0 is specified at clock event 1, the data on the I input is reflected at A/B/C/ output, because it is written to register 0. Clock Event 2: Shift In At time T S before clock event 2, the data becomes valid (1) at the I input of the L and is reflected on the A/B/C/ output after a delay of length T REG after clock event 2. Since the address 0 is still specified at clock event 2, the data on the I input is reflected at the output, because it is written to register 0. Clock Event 3: Shift In/Addressable (Asynchronous) REA All Read operations are asynchronous to the signal. If the address is changed (between clock events), the contents of the register at that address are reflected at the addressable output (A/B/C/ outputs) after a delay of length T ILO (propagation delay through a ). At time T S before clock event 3, the data becomes valid (1) at the I input of the L and is reflected on the A/B/C/ output T REG time after clock event 3. The address is changed (from 0 to 2). The value stored in register 2 at this time is a 0 (in this example, this was the first data shifted in), and it is reflected on the A/B/C/ output after a delay of length T ILO. Clock Event 32: MSB (Most Significant Bit) Changes At time T REG after clock event 32, the first bit shifted into the L becomes valid (logical 0 in this case) on the MUX output of the slice via the MC31 output of A (L). This is also applicable to the AMUX, BMUX, CMUX, MUX, and COUT outputs at time T REG and T WOSCO after clock event 1. Slice Carry-Chain Timing Model (SLIM and SLIL only) Figure 2, page 33 illustrates a carry chain in a Spartan- FPGA slice. Some elements of the slice have been omitted for clarity. Only the elements relevant to the timing paths described in this section are shown. Slice Carry-Chain Timing Parameters Table 9 shows the slice carry-chain timing parameters for a majority of the paths in Figure 2, page 33. Table 9: Slice Carry-Chain Timing Parameters Parameter Function escription Sequential elays for Slice Configured as Carry Chain T AXCY /T BXCY /T CXCY /T XCY AX/BX/CX/X input to COUT output Propagation delay from the AX/BX/CX/X inputs of the slice to the COUT output of the slice. T BYP CIN input to COUT output Propagation delay from the CIN input of the slice to the COUT output of the slice. T OPCYA /T OPCYB /T OPCYC /T OPCY A/B/C/ input to COUT output Propagation delay from the A/B/C/ inputs of the slice to the COUT output of the slice. Spartan- FPGA CLB User Guide 43