Introduction. APPLICATION NOTE 712 DS80C400 Ethernet Drivers. Jun 06, 2003

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1 Mxim > Design Support > Technicl Documents > Appliction Notes > Microcontrollers > APP 712 Keywords: DS80C400, ethernet drivers, ethernet controller, TCP/IP router, source code, MII, MAC, PHY, ethernet driver, specil function register, SFR, control sttus register, CSR, MAC ddress, high speed microcontroller, micros APPLICATION NOTE 712 DS80C400 Ethernet Drivers Jun 06, 2003 Abstrct: The DS80C400 high-speed microcontroller hs built-in Ethernet medi-ccess controller (MAC) with n industry-stndrd medi independent interfce (MII). This ppliction note presents design considertions nd fully tested exmple ssembly code for n Ethernet interrupt hndler, nd code for sending nd receiving Ethernet pckets. Using these routines, you cn develop custom pplictions such s TCP/IP routers. Introduction The DS80C400 high-speed microcontroller hs built-in Ethernet medi-ccess controller (MAC) with n industry-stndrd medi independent interfce (MII). Plese refer to the High-Speed Microcontroller User's Guide: DS80C400 Supplement nd the DS80C400 dt sheet for detils. This ppliction note presents design considertions nd fully tested exmple ssembly code for n Ethernet interrupt hndler, nd code for sending nd receiving Ethernet pckets. Using these routines, you cn develop custom ppliction such s TCP/IP routers. Full source code nd the heder files defining the symbolic constnts cn be found on the Dlls Semiconductor ftp site t Pge 1 of 13

2 Figure 1. DS80C400 Ethernet Buffer. The DS80C400 MAC Hrdwre Ethernet Buffer Memory The DS80C400 communictes with the network vi set of specil function registers (SFRs) nd 8kB of dul port buffer memory. The buffer memory is divided into the receive nd send memory nd cn be ddressed in blocks of 256 bytes ("pges"). The receive pges re orgnized in circulr fshion, mnged by the DS80C400 hrdwre. The send buffer is mnged by the user's ppliction. The loction for the Ethernet buffer is usully ddress 0FFE000h (defult configurtion estblished by ROM loder), ssigned to the constnt ETH_RECEIVE_BUFFER. Ethernet Control Sttus Registers The primitives RedCSR nd WriteCSR re used to red nd write the DS80C400 Ethernet control sttus registers (CSRs). Note tht the exmple code does not sve the processor registers cross function clls. When using this code, ensure tht you don't destroy the processor stte (this is especilly importnt when using interrupt driven dt trnsfer). Pge 2 of 13

3 Red CSR RedCSR reds control sttus register. *************************************************************************** Function Nme: ETH_RedCSR Description: Red from specified register. Input(s): -> register ddress Outputs(s): r3:r2:r1:r0 -> 32 bit register byte vlue *************************************************************************** ETH_RedCSR: push eie clr eie.5 csr, ; Lod CSRA SFR with the LSB of the ; 16-bit ddress of the trgeted CSR nl bcuc, #0f0h ; Cler BCUC commnd bits orl bcuc, #BCU_READ_CSR ; Write red CSR commnd to BCUC SFR push cc eth_redcsr_busy: ; Wit until Busy bit in BCUC SFR is reset, bcuc ; Move to cc since BCUC is not bit cp. jb cc.7, eth_redcsr_busy pop cc r3, csrd ; Red CSRD SFR for MSB of 32 bit dt r2, csrd r1, csrd r0, csrd ; LSB pop eie Listing 1. RedCSR Reds Control Sttus Register Note tht this code sves, disbles, nd restores the Ethernet ctivity interrupt enble (eie.5) to mke sure tht write to the CSR is not interrupted by n Ethernet ctivity interrupt. The definition for the bcuc, csrd nd csr SFRs cn be found in the include file ds80c400.inc. Constnt vlues such s BCUC_READ_CSR re defined in eth400.inc. Write CSR The WriteCSR function writes 32 bit vlue to control sttus register. *************************************************************************** Function Nme: ETH_WriteCSR Description: Write to specified register. Input(s): -> register ddress r3:r2:r1:r0 -> 32 bit vlue Outputs(s): N/A Pge 3 of 13

4 *************************************************************************** ETH_WriteCSR: push eie clr eie.5 csrd, r3 ; Write CSRD SFR for MSB of 32 bit dt csrd, r2 csrd, r1 csrd, r0 ; LSB csr, ; Lod CSRA SFR with the LSB of the ; 16-bit ddress of the trgeted CSR nl bcuc, #0f0h ; Cler bcuc commnd bits 0-3 orl bcuc, #BCU_WRITE_CSR ; Write write CSR commnd to bcuc SFR push cc eth_writecsr_busy: SFR is reset, bcuc jb pop cc pop eie cc.7, eth_writecsr_busy Listing 2. WriteCSR Writes Control Sttus Register Initiliztion MAC Address ; Wit until Busy bit in BCUC In order to use the DS80C400 on the network, globlly unique MAC ddress needs to be progrmmed into the device. The MAC ddress cn either be cquired from the DS2502-E48 MAC ddress 1-Wire prt (Dlls Semiconductor hs registered rnge of redy-to-go MAC ddresses in order to simplify building embedded devices) or from nother IEEE registered source. Very importnt: Under NO circumstnces select rndom MAC ddress or the ddress of nother existing device. MAC ddresses re globlly unique nd network stbility depends on well behved devices! *************************************************************************** Function Nme: ETH_LodEthernetAddress Description: Lod the 48 bit ethernet ddress into the controller. Input(s): dptr0 -> pointer to the Ethernet ddress (big-endin) ; for exmple Outputs(s): N/A *************************************************************************** ETH_LodEthernetAddress: r0, inc dptr r1, inc dptr r2, Pge 4 of 13

5 inc dptr r3, inc dptr cll x inc x clr cll, #CSR_MAC_LO r0, r1, r2, r3,, #CSR_MAC_HI ETH_WriteCSR Listing 3. LodEthernetAddress Lods the MAC Address into the DS80C400 Note tht two CSR writes re required to fully lod the 6-byte Ethernet MAC ddress. Since this code is only clled during initiliztion, it is not protected ginst Ethernet ctivity interrupts. Initilizing the Ethernet MAC further requires configurtion of the prtition between receive buffer (incoming pckets) nd send buffer (outgoing pckets). Figure 1 shows this prtition between pge n-1 nd pge n. To simplify code nd void dropping inbound pckets, most pplictions will benefit from prtitioning the buffer memory in fshion tht reserves most of the pges for inbound pckets nd only lloctes enough pges for one outbound pcket. The reson for this is tht Ethernet is shred medium nd even in switched networks only frction of incoming pckets re of interest to n ppliction. Therefore, we define the constnts ETH_TRANSMIT_PAGE to 17h nd ETH_SEND_BUFFER to ETH_RECEIVE_BUFFER + 17h x 256. Constnt ETH_TRANSMIT_PAGE ETH_SEND_BUFFER Vlue 17h 0FFF700h The following code first disbles the trnsmitter nd then initilizes the DS80C400 buffer memory to select the 23:9 receive:send prtition. The code then sets the hlf/full duplex sttus (this sttus cn be cquired from the MII, see below) nd enbles the trnsmitter. Enbling the Trnsceiver *************************************************************************** Function Nme: ETH_EnbleTrnsceiver Description: Enble receiver nd trnsmitter for Ethernet controller. Input(s): N/A Outputs(s): N/A Pge 5 of 13

6 *************************************************************************** ETH_EnbleTrnsceiver: push eie clr eie.5 ; First, disble trnsmitter nd receiver (full duplex bit is ; not settble if they re on) clr r3, r2, r1, r0,, #CSR_MAC_CTRL cll ETH_WriteCSR ; Set Ethernet buffer sizes TIMEDACCESS ebs, #ETH_TRANSMIT_PAGE ; Also clers the flush filter filed bit r3, #00h ; Select non-byte swp mode dptr, #ETH_DUPLEX_STATUS swp ; Move bit to position 4 (20:F) jnz eth_et_fullduplex orl, #80h ; Disble receive own (23:DRO) eth_et_fullduplex: orl, #08h ; Pss ll multicst (19:PM) OPTIONAL r2, ; Set duplex mode ccording to PHY detection r1, #10h ; Perfect filtering of multicst, ; lte collision control, no uto pd strip r0, #0ch ; Block-off limit 10, no deferrl check, ; enble trnsmitter nd receiver, #CSR_MAC_CTRL cll ETH_WriteCSR pop eie Listing 4. EnbleTrnsceiver Prtitions the Buffer Memory nd Enbles the Trnsceiver Note tht this code ssumes the duplex sttus informtion is stored t loction ETH_DUPLEX_STATUS in MOVX memory. Flushing the Buffer Next, the Ethernet buffer is flushed to ensure clen strtup. *************************************************************************** Function Nme: ETH_Flush Description: Relese ll resources. Input(s): N/A Outputs(s): N/A *************************************************************************** ETH_Flush: Pge 6 of 13

7 nl bcuc, #0f0h ; Cler bcuc commnd bits orl bcuc, #BCU_INV_CURR ; Write relese commnd to bcuc SFR Listing 5. Flush Flushes the Receive Buffer Sending nd Receiving Sending Pcket To send pcket, the user's ppliction must first plce the pcket dt in the Ethernet send buffer. If previous pcket ws plced t the sme ddress, the ppliction must wit for the trnsmit to be complete before modifying the buffer memory. Note tht the first four bytes of the send buffer re reserved for the send sttus word. The first byte tht will be trnsmitted is t loction ETH_SEND_BUFFER+4. *************************************************************************** Function Nme: ETH_Trnsmit Description: Trnsmit the rw Ethernet pcket currently in the Ethernet send buffer Input(s): r5:r4 = totl pcket length in bytes Outputs(s): N/A *************************************************************************** ETH_Trnsmit: ; Ethernet frme is in trnsmit buffer (Strting t ; pge offset = 4). Byte count is in r5:r4 bcuc SFR ; Lod MSB of byte count to bcud SFR bcud, r5 ; Lod LSB of byte count to bcud SFR bcud, r4 ; Lod strting pge ddress to bcud SFR bcud, #ETH_TRANSMIT_PAGE ; XXX Set trnsmit in progress flg in your softwre here ; XXX so you cn void interrupting trnsmit in progress. ; XXX e.g.: setb ds400_xmit ; Write trnsmit request to bcuc SFR nl bcuc, #0f0h ; Cler bcuc commnd bits orl bcuc, #BCU_XMIT ; Write trnsmit commnd to Listing 6. Trnsmit Sends Pcket Onto the Network Receiving Pcket When pcket is received (usully indicted by n interrupt, see below), the user code needs to unlod the pcket from the Ethernet buffer memory nd then relese the buffer memory, unlike the send buffer, which is mnged by the user, the receive buffer is mnged by the DS80C400. Pge 7 of 13

8 Unloding the Pcket Dt Note tht received pcket cn spn severl pges in the receive buffer nd it cn wrp from the lst pge in the receive buffer to the first pge in the receive buffer. Ensure tht your pcket copy routine properly hndles this cse. *************************************************************************** Function Nme: ETH_Receive Description: Strt unloding the lst pcket from the Ethernet controller. Input(s): N/A Outputs(s): N/A *************************************************************************** ETH_Receive: ; Get loction of buffer nd set dptr0 ccordingly, bcud nl, #1fh ; we re not interested in the pge count ; so now contins the strting pge number ; (1 pge is 256 bytes) dptr, #ETH_RECEIVE_BUFFER ; receive buffer strting ddress b, ; "multiply" pge by 256 to get byte count clr cll Add_Dptr0_16 ; nd dd it to receive buffer strting ddress ; dptr0 now points to the receive sttus word of the pcket inc dptr r2, ; sve LSB of frme length inc dptr r3, ; sve this ; check runt frme, wtchdog time-out nl, #(80h or 40h) jnz eth_ueh_relese, r3 ; restore nd get frme length nl, #3fh r3, ; sve HSB of frme length x dptr ; check CRC error, MII error, collision seen, frme too long nl, #(20h or 08h or 02h or 01h) jnz eth_ueh_relese ; MSB of sttus word ; check for length error, control frme, unsupported ctrl frme ; missed frme b, Pge 8 of 13

9 frme! nl, #(80h or 20h or 04h or 02h or 01h) jnz eth_ueh_relese ; bd bd bd, b nl, #40h ; check for filter mtch jz eth_ueh_relese ; XXX Copy the pcket into your buffer here. ; XXX r3:r2 contin the length of the pcket, ; XXX dptr0 points to the beginning of the dt. ; XXX Note tht the buffer cn wrp! eth_ueh_relese: Listing 7. Receive Receives Pcket from the Network Relesing the Buffer After processing n incoming pcket, the user code needs to relese the buffer memory in the Ethernet receive buffer. *************************************************************************** Function Nme: ETH_Relese Description: Relese resources. Input(s): N/A Outputs(s): N/A *************************************************************************** ETH_Relese: nl bcuc, #0f0h ; Cler bcuc commnd bits orl bcuc, #BCU_INV_CURR ; Write relese commnd to bcuc SFR Listing 8. Relese Releses Pcket from the Receive Buffer Interrupt Driven Opertion Insted of polling the bit flgs in the bcuc SFR, n ppliction should use the Ethernet ctivity interrupt for better performnce. There is one interrupt hndler for both receive nd trnsmit complete interrupts. The Ethernet ctivity interrupt clls loction h. Since there re only 8 bytes per interrupt, we suggest instlling long jump to the ctul function: org 73h ljmp ETH_ProcessInterrupt Processing Interrupts The following code hndles both receive nd trnsmit complete interrupts. *************************************************************************** Function Nme: ETH_ProcessInterrupt Description: ISR for Ethernet interrupt Pge 9 of 13

10 Input(s): N/A Outputs(s): N/A Destroyed: Nothing. *************************************************************************** ETH_ProcessInterrupt: push cc, bcuc nl, #rif ; Received dt? jz eth_pi_no_receive ; XXX Cll your receive pcket hndler here. ; XXX Ensure it sves nd restores ll registers! ; XXX E.g.: cll ETH_ProcessPcket eth_pi_no_receive:, bcuc nl, #tif jz eth_pi_exit ; Trnsmitted dt? ; XXX If you keep trck of send in progress, here's the plce ; XXX to cler the flg. ; XXX E.g.: clr ds400_xmit nl bcuc, #(not(tif) nd 0f0h) ; nd NOOP commnd ; XXX If you keep trnsmit queue, send next pcket from queue ; XXX E.g.: cll ETH_SendNextFromQueue eth_pi_exit: pop cc i Listing 9. ProcessInterrupt Hndles Ethernet Activity Interrupts Enbling Interrupts Finlly, fter enbling the Ethernet interrupt, the DS80C400 is redy to receive nd send pckets. *************************************************************************** Function Nme: ETH_EnbleInterrupts Description: Enble Ethernet trnsmit/receive interrupts. Input(s): Outputs(s): Destroyed: *************************************************************************** ETH_EnbleInterrupts: ; XXX If you keep trck of trnsmits in progress, cler ; XXX the flg here. ; XXX E.g.: clr ds400_xmit nl bcuc, #(not(rif or tif) nd 0f0h) ; Cler interrupt flgs setb eie.5 ; Enble Ethernet ctivity interrupt clr eip ; Set network interrupt priority low Listing 10. EnbleInterrupts Enbles the Ethernet Activity Interrupt Medi Independent Interfce (MII) The Medi Independent Interfce (MII) defines I/O lines tht llow the DS80C400 to communicte with Pge 10 of 13

11 the physicl lyer interfce (PHY). Even though mny PHYs hve vendor-specific commnd set, there re common commnds tht most PHYs shre, defined in the IEEE Std Communictions with PHY cn be used to query PHY for its uto negotition nd duplex stte, nd to isolte nd "unisolte" PHYs (in the cse of multiple PHYs) nd reconfigure PHY. The MII on the DS80C400 is ccessed through CSR registers. The following routines red nd write n MII register in given PHY. Red MII Register *************************************************************************** Function Nme: ETH_RedMII Description: Red MII register Input(s): -> register number, b -> PHY number Outputs(s): r1:r0 -> contents of MII register Notes: MII ddress Register (14h): reserved PHY ddress MII register reserved 1 -- MII write 0 -- MII busy *************************************************************************** ETH_RedMII: push eie clr eie.5 r7, ; Sve register number ; Wit until MII is not busy eth_rmii_busy:, #CSR_MII_ADDR cll ETH_RedCSR jb, r0 cc.0, eth_rmii_busy clr r3, ; Reserved - lwys cler r2,, r7 ; Restore register number rr rr ; And shift to pos 10:8 r7, ; Sve result of shift nl, #07h ; Select bits 0:2 r1,, b ; Lod PHY ddress nl, #1fh rl rl rl ; shift to 7:3 orl, r1 r1,, r7 ; Restore result of shift nl, #0c0h ; Select bits 7:6 r0, cll, #CSR_MII_ADDR ETH_WriteCSR Pge 11 of 13

12 ; Wit until MII is not busy eth_rmii_busy2:, #CSR_MII_ADDR cll ETH_RedCSR, r0 jb cc.0, eth_rmii_busy2 ; Red MII dt register, #CSR_MII_DATA cll ETH_RedCSR pop eie Listing 11. RedMII Reds n MII Register from Given PHY Write MII Register *************************************************************************** Function Nme: ETH_WriteMII Description: Write MII register Input(s): -> register number, b -> PHY number, r1:r0 -> dt Outputs(s): N/A *************************************************************************** ETH_WriteMII: push eie clr eie.5 push 0 ; Sve r1 nd r0 push 1 r7, ; Sve register number ; Wit until MII is not busy eth_wmii_busy:, #CSR_MII_ADDR cll ETH_RedCSR jb pop 1 pop 0, r0 cc.0, eth_wmii_busy clr r3, ; Reserved - lwys cler r2, ; Write MII dt register, #CSR_MII_DATA cll ETH_WriteCSR, r7 ; Restore register number rr rr ; And shift to pos 0:2 r7, ; Sve result of shift nl, #07h ; Select bits 0:2 r1,, b ; Lod PHY ddress nl, #1fh rl rl rl ; shift to 7:3 Pge 12 of 13

13 orl, r1 r1,, r7 ; Restore result of shift nl, #0c0h ; Select bits 7:6 orl, #2 ; Select write bit :1: r0, cll pop, #CSR_MII_ADDR ETH_WriteCSR eie Listing 12. WriteMII Writes n MII Register to Given PHY MII Exmple The following code reds the MII sttus register of PHY: b, #0, #MII_STATUS cll ETH_RedMII Relted Prts DS80C400 Network Microcontroller Free Smples More Informtion For Technicl Support: For Smples: Other Questions nd Comments: Appliction Note 712: APPLICATION NOTE 712, AN712, AN 712, APP712, Appnote712, Appnote Mxim Integrted Products, Inc. Additionl Legl Notices: Pge 13 of 13