Chapter 9. Timing Design. (Based on Chapter 7 and Chapter 8 of Wakerly) Data Path Comb. Logic. Reg. Reg. Reg C <= A + B

Transcription

1 Chapter 9 Timing esign (Based on Chapter 7 and Chapter 8 of Wakerly) Timing Check X State machine Next State Logic * * 0 1 State Memory 0 1 EN Counter * 0 * Incrementer A B Reg Reg ata Path Comb. Logic Reg C <= A + B C We know timing parameters for a combinational logic gate: tphl and tplh But, what are the timing parameters of a sequential logic element such as a FF? 4/12/06 1 / 16

2 1 Metastability in bistables, latches, and flip-flops Bistable uestion: How long the set or reset control should be active before becoming passive? Until the friendly echo arrives. S = 1=>0=>1 =0=>1 =1=>0 R = 1 S R If this pulse is short, then, may go into a metastable state 4/12/06 2 / 16

3 -Latch If clock goes inactive immediately after changes, the latch can go into metastable state. See figure 7-12 (page 531) and figure 7-14 (page 531) in Wakerly. Window t hold t setup metastable violated setup time requirement 4/12/06 3 / 16

4 -FF (positive edge triggered) If clock goes high immediately after changes, the master latch portion of the -FF can go into metastable state. See figure 7-15 (page 532) and figure 7-17 (page 533) in Wakerly. MASTER SLAVE Window t hold t setup violated setup time requirement metastable 4/12/06 4 / 16

5 2 Why would change around the clock Improper timing design Asynchronous inputs (push-button operation by a human) ue to clock Skew (clock may not reach all parts of the chip at the same exact time) 3 Setup time, Hold time, and Propagation delay of a Flip-Flop Setup time t su : The input shall be valid and stable for t su time before the significant edge of the clock. Hold time t h : The input shall be valid and stable for t h time after the significant edge of the clock. [7:0] t su t h After the clock edge, the output may change after a little time called propagation delay. Note: There is only one value for t su and t h : the minimum. There is no typical or maximum for these. 4/12/06 5 / 16

6 SN5474, SN54LS74A, SN54S74 Texas Instruments SN7474. SN74LS74A, SN74S74 UAL -TYPE POSITIVE-EGE-TRIGGERE FLIP-FLOPS WITH PRESET AN CLEAR SLS119 ECEMBER 1983 REVISE MARCH 1988 MIN In our course, if we need the minimum, we simply take it as 1/3rd of the maximum. 4/12/06 6 / 16

7 4 Timing Check, setup time margin and hold time margin State machine X * 0 * Next State Logic 0 * 1 State Memory 1 EN Counter Incrementer 0 * ns 130ns A B Reg Reg ata Path Comb. Logic Reg C ata available Margin C <= A + B ata needed by 4/12/06 7 / 16

8 Please see figure 8-1 (page 682), figure 8-63 (page 760) and figure 8-64 (page 760) in Wakerly S2 if P > F <= + E else F <= - E S3 if X > Y C <= A + B else C <= A - B Assume that the PU consists of just one comparator and one ALU. 4/12/06 8 / 16

9 Setup time Margin = t clk -t ffp(max) - t comb(max) - t setup(min) Hold time Margin = t ffp(min) + t comb(min) - t hold(min) What is hold time and why do we need it? Consider a shift register. Serial In Serial Out Relation between t ffpd t h How do we fix hold time violation? How do we fix setup time violation? Where would you be concerned about the maximum delay path through the combinational logic? Where would you be concerned about the minimum delay path through the combinational logic? Reg Reg Comb. Logic Reg 4/12/06 9 / 16

10 5 Asynchronous Inputs: Examples of asynchronous inputs: Inputs from human, inputs from other subsystems working on a different independent clock If the asynchronous input changes too late into the clock, the system can go into a wrong state! A C X = X = B Wrong state reached due to X changing rather late. X Asynchronous Next State Logic * * 0 1 State Memory 0 1 4/12/06 10 / 16

11 Synchronization of asynchronous signals by using a synchronizing FF: XA X_Asynchronous Synchronizing flip-flop Sample-and-hold flip-flop XS X_Synchronized Next State Logic * * 0 1 State Memory 0 1 Should this sampling edge be the same or opposite of the significant edge of the system? RACE condition? So it should be opposite edge?! The finite propagation delay of the synchronizing FF the hold time requirements of the receiving system/ffs 4/12/06 11 / 16

12 The clock for synchronization shall be the (sending/receiving) system's clock. Example from EE201L homework #9: System-33 System-44 System-33 System-44 System-33 System-44 System based on 33 MHZ Clock O-IT ONE System based on 44 MHZ Clock System based on 33 MHZ Clock O_IT 33 MHZ S_ONE S_O_IT ONE 44 MHZ System based on 44 MHZ Clock System based on 33 MHZ Clock O_IT S_O_IT 44 MHZ S_ONE ONE 33 MHZ System based on 44 MHZ Clock 33MHz 44MHz 33MHz 44MHz 33MHz 44MHz esign # 1 esign # 2 esign # 3 esign # 1 experiences synchronization problems because... Between esign #2 and # 3, is right and is wrong. 4/12/06 12 / 16

13 6 What is meant by flip-flops hardened against metastability? S =0=>1 R =1=>0 7 ouble-synchronization helps to reduce the probability of failure due to metastability: Increases MTBF (Mean Time Between failures) XA XS XSS Next State Logic * * 0 1 State Memory Setup and hold time window shifts because of path delay in "" or "" The setup and hold time of a flip-flop are 0.3ns and 0.1ns, respectively; but because of the routing issues, some delay may occur on one or both input signals ( and ). 4/12/06 13 / 16

14 The amount of this delay is 0.04ns. In the presence of this delay, the setup and hold time of the whole circuit may change. t setup = 0.3ns t hold = 0.1ns A B 0.04ns 0.04ns delay=0.04ns C 0.04ns 0.04ns t setup = ; t hold = 4/12/06 14 / 16

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16 9 Result of severe clock-skew problem Figures 8-65 (page 762) and 8-66 (page 763) from Wakerly. 4/12/06 15 / 16

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19 10. Why does RES (asynchronous RESET) need to be synchronized to produce synchronous RESET? VCC It is not about when you go into reset. It is about when you come out of reset. Reset PB RESET CS= ~RESET S= START = 0 A WATER CS= S= RINSE RAIN RY ONE Too close to clock edge START = 1 RESET ONE A_WATER RAIN CS START NSL A_WATER RINSE START S S CS NSL NSL ONE RAIN RY ONE RESET RESET SYNC_RESET Better to replace this with this. 4/12/06 16 / 16

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