Stanford Linear Accelerator Center Accelerator Controls Electronics & Instrumentation Engineering SLAC IP-QINT-ADC

Transcription

1 SLAC IP-QINT-ADC 8-Channel Industry Pack Charge-Integrating ADC Programming Guide Version 3.0 For Use With Board Part Number: R1 IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 1 of 90 J. Dusatko /

2 Table of Contents 0. MEMORY MAPS OVERVIEW MODULE DESCRIPTION IP-QINT-ADC MODULE I/O SPACE REGISTER DESCRIPTIONS MODULE CONTROL & STATUS REGISTER MODULE CONTROL & STATUS REGISTER MODULE CONTROL & STATUS REGISTER TRIGGER DELAY REGISTER TRIGGER ERROR COUNTER TEST PULSE GENERATOR DELAY REGISTER TEST PULSE GENERATOR WIDTH REGISTER GATE GENERATOR DELAY REGISTER GATE GENERATOR WIDTH REGISTER SYNC GENERATOR DELAY REGISTER SYNC GENERATOR WIDTH REGISTER GENERAL-PURPOSE I/O CONTROL REGISTER GATE ADC DELAY REGISTER SYNC GENERATOR DELAY REGISTER SYNC GENERATOR WIDTH REGISTER CHANNEL FAULT STATUS REGISTERS CHANNEL LATCHED FAULT STATUS REGISTERS SUMMARY FAULTS REGISTER SUMMARY FAULTS REGISTER SUMMARY LATCHED FAULTS REGISTER SUMMARY LATCHED FAULTS REGISTER GATE GENERATOR DELAY REGISTER GATE GENERATOR WIDTH REGISTER GATE GENERATOR WIDTH REGISTER GATE ADC DELAY REGISTER IP MEMORY SPACE REGISTERS BEAM/TEST/BASELINE SHIFT REGISTER RAW DATA CHANNEL DOSE DATA / FAULT THRESHOLD Channel n Baseline Register Channel n Current Beam Charge Value Channel n 1 Second Accumulated Beam Charge Low Channel n 1 Second Accumulated Beam Charge High Channel n 1/10 Second Accumulated Beam Charge Low Channel n 1/10 Second Accumulated Beam Charge High Channel n 1/30 Second Accumulated Beam Charge Low Channel n 1/30 Second Accumulated Beam Charge High Channel n 1/60 Second Accumulated Beam Charge Low Channel n 1/60 Second Accumulated Beam Charge High Channel n Current Test Charge Value Channel n 1 Second Accumulated Test Charge Low Channel n 1 Second Accumulated Test Charge High...64 IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 2 of 90 J. Dusatko /

3 Channel n Lower-Bound Beam Data Fault Threshold Channel n Upper-Bound Beam Data Fault Threshold Channel n Lower-Bound Test Data Fault Threshold Channel n Upper-Bound Test Data Fault Threshold Channel n Lower-Bound Baseline Data Fault Threshold Channel n Upper-Bound Base Data Fault Threshold RAW ADC DATA BASELINE DATA RAW ACCUMULATOR DATA Accumulator Memory Low Word Data Format Accumulator Memory High Word Data Format INDUSTRY PACK ID ROM SEQUENCE OF OPERATIONS HIGH-LEVEL DESCRIPTION OF OPERATIONS SEQUENCE LOW-LEVEL SEQUENCE OF OPERATIONS DATA PAYLOAD DOCUMENT CHANGE HISTORY...86 APPENDIX A: PIC OPERATING MODE...87 IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 3 of 90 J. Dusatko /

4 0. MEMORY MAPS: IP-QINT-ADC I/O Space Memory Map: 16-bits 0x007E Unused 0x0050 0x004E 0x004C 0x004A 0x0048 0x0046 0x0044 0x0042 0x0040 0x003E EGate ADC Delay Reg EGate Width Reg High EGate Width Reg Low EGate Delay Reg Latched Summary Faults Reg_1 Latched Summary Faults Reg_0 Summary Faults Reg_1 Summary Faults Reg_0 Latched Chan 7 Fault Status 0x0030 0x002E Latched Chan 0 Fault Status Chan 7 Fault Status 0x0020 0x001E 0x001C 0x001A 0x0018 0x0016 0x0014 0x0012 0x0010 0x000E 0x000C 0x000A 0x0008 0x0006 0x0004 0x0002 Chan 0 Fault Status Reserved Test-to-Base Delay Reg Beam-to-Test Delay Reg Gate ADC Delay Reg GPIO Ctrl Reg Sync Out Width Reg Sync Out Delay Reg Gate Width Reg Gate Delay Reg Test Pulse Width Reg Test Pulse Delay Reg Trigger Error Cnt Trigger Delay Reg CSR2 / Control & Status Register 3 CSR2 / Control & Status Register 2 Base + 0x0000 CSR1 / Control & Status Register 1 Note that the IP I/O space only uses address lines A6:A1. IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 4 of 90 J. Dusatko /

5 IP-QINT-ADC MEM Space Memory Map: 16-bits 0xFFFFFF Unused 0x0059BE 0x Beam / Test / Baseline Accumulator Raw Data <reserved> 0x00582E 0x x x x x x x BLM Baseline Data Chan 0..7 <reserved> Raw ADC Data Chan <reserved> ADC Diagnostic Memory <reserved> Channel 7 Dose Data / Fault Thresh 0x x x004FFF 0x Channel 0 Dose Data / Fault Thresh <reserved> 0x00437E Beam / Test / Baseline Shift Register Raw Data Base + 0x Note that the IP MEM space uses address lines A22:A1 IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 5 of 90 J. Dusatko /

6 1.0 Overview: This document describes the register structure of the SLAC IP-QINT-ADC module (SLAC P/N R0) from the viewpoint of the software developer. Each register and its respective control bits are described in detail. All registers are 16-bits wide, though all 16 bits may not be utilized. This document is organized into several sections. The first section gives a basic introduction to the module, describing its architecture and functionality. The next two sections describe the registers exiting in each of the separate IP module memory spaces. The section after this describes the IP module s ID ROM contents. Following this is a section describing the relevant data the board produces and how it should be used. This is proceeded by an operations guide that explains how to set up the module s registers to achieve proper operation. 2.0 Module The section gives a functional description of the IP-QINT-AC. The basic function of the IP-QINT-ADC is to sample up to eight analog signals, convert them into digital format and process those signals to give current and accumulated radiation dosage information. This dosage information is then compared against preset thresholds to generate fault conditions if those thresholds are exceeded. The module is controlled and read out over the IP bus. The module is a single-width Industry-Pack bus eight channel analog-to-digital converter. It has been designed as a component of the LCLS Machine Protection Link-Node system. Although it is targeted for the Link-Node chassis, it can be also used on a standard Industry Pack Carrier module interfacing to VMEbus, for example. This module complies with the ANSI/VITA (R002) Industry Pack standard. It supports 8MHz 16-bit bus transfers in ID, I/O and MEMory space. Note that it does not support Direct Memory Access (DMA) or Interrupts. The IP-QINT-ADC is an eight channel ADC configurable for both native charge-integrating or voltage sensitive signal conversion. The particular version of the board is identified in the contents of the ID PROM (see section 5). There are currently three sub-versions of the module corresponding to different charge-integrating types (BLM and PIC) and the voltage-sensitive mode. Other version may be developed at a later date. The function of the module is described by looking at the block diagram and walking through each block. These will be described now; in each sub-description, the registers controlling a particular function will be called out. The description starts with Analog Front End (AFE). AFE: The AFE (Analog Front End) consists of an analog integrator and shaping amplifier. There is one pair for each channel. The integrator is the classic single inverting op-amp structure consisting of a single capacitor in the feedback loop fed by an input resistor. The capacitor is 100pF for the BLM and 0.1uF for the PIC application. The input resistance is 50ohms for termination of the input transmission line. The integrating capacitor is reset by an analog switch controlled by the gate generator block. The integrator is normally in a reset state with the analog switch closed. When an input signal is to be acquired, the switch is opened by the gate signal for approximately 20us. The signal timing is setup so that the input will present itself about 1us to 3us after the gate is opened, collecting all of the charge if the input signal onto the integrating capacitor. Near the end of the gate, the ADCs are commanded to perform a convert; converting the voltage on the integration capacitor (after conditioning by the shaping amplifier) to a digital quantity. Note that the integrating amplifier is inverting. The shaping amplifier has a DC gain of This gain was chosen to give a full scale ADC signal for a full-scale analog input. The maximum expected charge input is 125pC. Note that the ADC expects +/-5V for full-scale. The shaping amplifier has a single pole shaping network arranged as a leaky-integrator. The shaping time constant is 1.24uS. At frequencies above the inverse of the time constant, the gain changes to This was done as a droop compensation scheme to fix the signal distortion due to the interconnecting cable. IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 6 of 90 J. Dusatko /

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8 AFE (cont.) When the module is configured for voltage-sensitive mode, the integrator circuit is bypassed and the shaping amplifier is connected directly to the input connector by removing two resistors and installing two more. The shaping amplifier then has a 50Ω input terminator. For the BLM application, the voltage signal has a relatively long time constant of 50uS. The module s acquisition trigger timing needs to be arranged accordingly. Note also that for the ANL BLM application, the Cremat model CR-112 preamp that is used has a -0.6V offset. The gain of the shaping amplifier was also chosen to remove this offset. ADC: The module s ADC block performs the analog-to-digital conversion of the voltage at the output of the shaping amplifier. Each channel has its own ADC. The ADC is an Analog Device AD bit successive approximation ADC. It is capable of converting data at a maximum of 4uS. Two AD7656 devices are used on the module. Although the AD7656 is a 6-channel device, only four channels on each device are used for the external analog inputs. This was done for PCB layout reasons. The remaining four ADC channels are used to monitor the board s power and ground rails. The ADCs are set for an input signal dynamic range of +/-5Volts; and produce a 16-bit digital word in 2 s complement binary format. With the chosen scale, the ADC bit resolution is 152uV/count. The internal reference of the ADC is used, as it is deemed accurate enough for this application with a stability of 150ppm. The ADC s operation is controlled by the Control/Sequencer Unit, once a trigger is received by the board, all of the conversion and readout is autonomous. The ADC is used in serial interface mode, with the sample data read out, de-serialized and saved into memory for processing by the Accumulate/Average/Compare Unit. The interface between these two units is via dual-port RAM. Another DPR has been included to provide the user the ability to readout the RAW ADC values after a conversion sequence has completed. The ADC data is passed into the Average/Accumulate/Compare (AAC) module. This module will be described later. Registers used by this module: MEM Space: AAC unit registers, Raw ADC Data Gate Generator: When the module operates in charge-integrating mode, the AFE requires a gate signal to open the integrating capacitor reset switch to allow charge to be transferred to it. This block provides that signal. Before the gate closes again to reset the integrating capacitor, the ADC is triggered to sample the integrated charge value. The gate generator provides a signal that is programmable in assertion delay, width, polarity and ADC acquisition time. The last item controls when the ADC is told to perform a sample conversion, prior to the closing of the gate. Although all of these parameters are programmable, default values have been setup for the BLM and PIC applications. This module accepts signals from the Trigger System and Control/Sequence Unit. Note that it actually sends the convert command to the ADC based on the time setting of the ADC sample delay register. For voltage-sensitive versions, the gate generator is not enabled and the ADC sample start control comes from the Trigger System directly. For mixed-mode boards (voltage- and charge-sensitive), the Gate Generator is enabled and the ADC sample command is controlled by this subsystem for the voltage-sensitive channels as well. This should be taken into consideration when sampling the voltage channel signals. <explain how it hand-shakes with the MCSU> Registers used by this module: I/O Space: CSR1, GDEL, GWID, GADEL Test/Heartbeat Pulse Generator: For the BLM application, it is required that a periodic test pulse be sent as a means to verify the BLM detector and readout signal chain from front to back. This signal would be sent during a regular acquisition sequence, after the beam data has been acquired and before a baseline measurement is taken. This signal is used to drive a test LED that sends a flash of light to the photomultiplier tube. The assertion delay, polarity and width of this pulse signal is programmable, but default values are preset for the BLM application. This block is controlled by the Control/Sequencer Unit. The test pulse is sent a fixed time after the beam acquisition sequence has completed. After IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 8 of 90 J. Dusatko /

9 the test pulse has been generated, the module records the resultant detector signal by commanding the ADC to take a sample. A controllable delay is provided to provide a time lag between the issuance of the test pulse and connection of the resulting detector signal to compensate for cable propagation, electronics latencies and so forth. Registers used by this module: I/O Space: CSR2, TPDEL, TPWID, TDEL General-Purpose I/O (GPIO): This subsystem provides two each general-purpose digital inputs and outputs for use in controlling/reading status of external devices to the module. These signals are completely software controlled. The digital inputs are nonlatching, positive logic signals. The digital outputs are set and cleared by writing control bits, which can also be read back. These signals are LVTTL level. Registers used by this module: I/O Space: GPIO Trigger System: The trigger system receives and processes the triggers for the module. A trigger signal is used to initiate the module s acquisition sequence (explained in more detail later). There are two external hardware trigger inputs and a software trigger, all of which are software-selectable. The external triggers are assumed to be asynchronous and are edge-captured and re-synced to the module s 40Mhz system clock. The trigger edge is software selectable. Note that although edge selection on the software trigger is somewhat nebulous, it is suggested that the positive edge be selected for more consistent timing accuracy. The external triggers are TTL level and have 50Ω input terminations. The minimum input trigger pulse width is 25ns. Since the input triggers are re-synced by the 40MHz board system clock, there can be a 50ns timing uncertainty from trigger to trigger because of this. This subsystem also provides a controllable delay that provides a time-delay between the assertion of the input trigger (HW or SW) and the actual start of acquisition. This delay is adjustable in 25ns increments. This module actually sends a start signal to the Control/Sequencer Unit which then initiates and sequences all of the module s operations. The trigger system also provides an error detection mechanism for catching missed triggers. The triggers for the BLM and PIC systems are required to run at 360Hz. If a trigger at 1/360 sec is missed, it is important to know this since the ADC data will not be updated. The trigger system has a missing trigger detector that sets a bit if a trigger does not occur during a 1/360 sec interval; this bit is latching and is cleared by SW. In addition, a missing trigger counter is provided to record each occurrence when a trigger is missed. The counter increments each time a trigger is missed and is read out and cleared via SW. Registers used by this module: I/O Space: CSR1, TRIG_DLY, TRIG_ERR_CNT Module Acquisition Sequence: Before describing the remaining subsystem blocks in the module, the acquisition operation of the board must be described first. Unlike general-purpose ADC boards, the IP-QINT-ADC was designed to perform an applicationspecific acquisition sequence. This is, when a trigger is generated, the board (module) actually does several operations resulting in a group of data presented for readout. The operation is best described by a diagram which is shown in figure 2. The module receives one trigger and performs all of its internal operation autonomously. When finished, it sets a done bit which tells the external processor (over the IP bus) that data is ready to be read out and waits for the next trigger. Note that the done bit (CSR1: DRDY) is not interlocked so that although it needs to be cleared, the clearing operation has nothing to do with the automatic re-arming the module to respond to the next trigger. Although this creates the risk of the data changing before its all read out (if another trigger comes along), the timing of the trigger and readout speed should be such that the risk is remote. IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 9 of 90 J. Dusatko /

10 As shown in the diagram, the trigger is derived from the timing system and is delayed until beam time by an external mechanism (the Link-Node trigger processor, in the BLM case). The three separate acquisition events each collect a different type of data. These measurements occur each time a trigger is received. Fiducial Trigger n (input to Link Node) Fiducial Trigger n+1 (input to Link Node) 1/360 sec = 2.8mS Trigger To IP-QINT-ADC (ACQ Beam Signal) Send LED Pulse & Open Gate ACQ Test Pulse Signal ACQ Baseline Signal Re-init for next cycle ~900us ~900us Programmable short 1.2uS Programmable arbitrary (BTTDEL Reg) (TBLDEL Reg) ~1024us Programmable (TDEL Reg) = Trigger from Timing System Link node internally delays Fiducial signal to time-align it with Beam Time IP-QINT-ADC can also delay this signal = HW trigger from Link node to IP-QINT-QDC Figure 2: BLM System Timing Diagram = Internal Operation of IP-QINT-ADC (all of these are automatic) Within these operations, the module performs three acquisition cycles spaced apart in time from the single input trigger. This trigger is generated by the link node trigger processor and is a derivative of the standard 360Hz accelerator fiducial. Once this trigger is received by the module, all of the operations are automatic from the Link Node s perspective. The trigger causes IP-QINT-ADC to perform three separate acquisition cycles: a) Beam data, b) Test data acquisition and c) Baseline/Pedestal data acquisition. Immediately at the trigger, a beam data acquisition is performed and the resultant data is processed; approximately 900us later the module generates the test pulse signal. This signal is 2us wide; following a short, programmed delay (to account for signal propagation and detector latencies) the test signal acquisition is performed and the resulting data is processed. Approximately 900us after the test sequence, the ADC is again enabled to take a sample during the quiet period of the LCLS machine cycle. This operation measures the baseline offset or pedestal of the detector electronics signal chain. This value is saved and accumulated over a period of one second. The accumulated value is then used to subtract offsets from the beam and test signal data. Note that all of the data is available for readout over IP bus when DRDY is set. IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 10 of 90 J. Dusatko /

11 Control/Sequence Unit: The Control/Sequence Unit (CSU) controls, coordinates and sequences all of the module s operations. It is tightly coupled to all of the blocks in the module, especially the IP bus interface and AAC unit The CSU responsible for instructing the module s blocks to perform all of the operations described in Fig 2. It contains two state machines that receive the selected trigger from the trigger processor and generate control signals to all of the other blocks in the module. The blocks send various status signals back to the CSU indicating that their operation has completed, allowing the CSU s state machines to advance to their next operation. The initialization and running of the CSU is controlled by control & status registers contained in the IP Bus Interface block. At a high level the IP interface tells the CSU to start running is acquisition sequence; when completed, it sets a CSR bit indicating that data is ready for readout. The CSU has normal and diagnostic modes of operation. When in normal mode, the sequence of operations in Fig 2 is followed. When in diagnostic mode, the module can be single-stepped thru either the full three data-type sequence with the stepping occurring at each trigger or a single data type can be selected and stepped thru per trigger. Note that the delays between each operation has a preset default delay. These delays can be changed by setting the appropriate control register. Registers used by this module: I/O Space: CSR1, CSR2, CSR3, BTTDEL, TBLDEL, TDEL IP Bus Interface: The IP bus interface provides a communications conduit between the board and the outside world. This module complies with the ANSI/VITA (R002) Industry Pack standard. It supports 8MHz 16-bit bus transfers in ID, I/O and MEMory space. Note that is does not support Direct Memory Access (DMA) or Interrupts. The IP bus interface handles the IP bus protocol; generating and responding to the control handshake signals. It contains the module s control and status registers and decodes the addresses for all of the module s register and memory locations. It re-synchronizes the 8MHz IP data and address busses to the internal 40Mhz clock and re-syncs outbound data from the module to the 8MHz IP clock. Because of this, there is a latency of four 8MHz clock cycles between the IP_SELECT* signal and the modules assertion of IP_ACK* for all I/O, ID and MEMory IP bus cycles. In addition to the decoded address selects, the IP Interface module generates read and write strobes for use by the subsequent blocks. The interface architecture is set up such that the IP IFC contains the core protocol logic, address decoding and strobe logic, while each functional block in the module has contains its own local registers. Data is sent back to the IP IFC and is muxed into the output datastream. The IP Interface also contains the IP ID PROM. Registers Used by this module: all I/O space, all MEM Space, ID Space Sync Output Generator: The sync output generator provides a means of monitoring many internal board signals for debugging, diagnostics, sequencing external hardware and so on. The sync signal is selectable to be either the raw original signal or a timed pulse controllable in polarity, delay, and width. The sync signal source and characteristics are completely software controllable. The signals that can be monitored include the trigger, gate, ADC go, test pulse, sequencer, faults and others. Registers used by this module: I/O Space: CSR3, SDEL, SWID Clock System: The clock system provides the clock to the board. It takes the 80Mhz crystal oscillator and divides it by two to provide the 40MHz system clock for all of the on-board logic. An additional 20Mhz clock is generated for use by the trigger error detection mechanism. Note that no external clock input is provided as this time. In addition, note that the board clock rate is fixed and not changeable. Registers used by this module: I/O Space: CSR2 (DCM locked bits) IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 11 of 90 J. Dusatko /

12 Power System: The power system receives and conditions the +5V, +12V & -12V DC voltages from the IP bus interface and provides +5V, +3.3V, +2.5V, +1.2V, +12V and -12V to the board s digital and analog circuitry. Note that analog and digital powers are separated and filtered. In addition, separate analog and digital grounds are provided; these grounds are necessarily joined as a common reference at the board s power input. The spare ADC input channels are used to monitor the digital +3.3V, +2.5V, +1.2V and GND rails. Registers used by this module: MEM Space: Raw ADC Data (power rails monitor channels) Accumulate/Average/Compare Unit (AAC): This is the most complex subsystem in the module (see Fig 1). It implements the data processing engine of the IP- QINT-ADC. As described in Module Acquisition Sequence section, the module takes three different measurements. How the measurement data is processed will now be described: The basic goal of the AAC is to take in the data, accumulate it over a fixed time interval and test it along with the most recent data sample against a windowed threshold and set a fault signal if the data is outside of the window. In addition, it provides the most recent and accumulated data values for readout. These operations are performed for the beam and test data types. In addition, the subsystem also measures the baseline/pedestal of the detector/electronics signal chain (the third operation in figure 2), averages it over one second and digitally subtracts off the averaged value from raw Beam and Test ADC data samples. This is the Baseline / Pedestal Correction mechanism. The most recently measured pedestal value is also available for readout. A window comparator is also provided for the baseline signal to generate a fault signal should the baseline stray outside the window, indicating a problem in the detector or readout chain. The following data is provided by the AAC unit for each ADC channel: Beam Data: The beam charge (Qpb) for the last pulse; updated at 360Hz (each trigger) The beam charge (Q60b) accumulated for the last 1/60 Second The beam charge (Q30b) accumulated for the last 1/30 Second The beam charge (Q10b) accumulated for the last 1/10 Second The beam charge (Q1b) accumulated for the last 1Sec. Test Charge Data: The test charge (Qt) for the last led pulse; updated at 360Hz The test charge (Q1t) accumulated for the last 1Sec. Pedestal Data: The pedestal value for the last trigger/acq; updated at 360Hz These data values are updated at each trigger instance. Note that the accumulation rates are based on trigger times and not on an absolute wall clock time. That is, the 1 second accumulation is timed from one second s worth of input fiducial triggers (360 triggers). A comparator window is set around each of the above data quantities. A separate pair of fault thresholds (high & low) is set for each data type. Note that for a given data type, the different accumulation rates all use the same pair of fault thresholds. This is possible based on the reasoning that while longer accumulations will grow more slowly, normal well-behaved data samples will be within the expected threshold. Accumulations will grow and reach the threshold at some point while a new sample if it is very large will also trip on the same threshold level. The accumulation function is analogous to the mathematical integrate function, where a quantity is summed over a fixed time interval. This can be done in either the analog or digital domain. The CAMAC PIC module performed the IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 12 of 90 J. Dusatko /

13 accumulate function using analog integrator circuits. The IP-QINT-ADC does this function digitally. The basic digital integrator function is shown below: This logic circuit actually implements a bounded wind-up or leaky integrator. It works as follows: at each clock tick, a new ADC sample is presented to the input of the shift register. This new sample is passed out of the shift register (Q1 output) and into the accumulator, which sums the new value with whatever the previous value was. We assume that the accumulator is cleared initially. The accumulated sum will continue to increase with each clock tick as each new ADC sample is presented. When the shift register fills up with 360 samples, the subtraction term of the accumulator becomes active, this acts to limit the maximum value to the time accumulation over 360 samples. Hence, we get a fixed-rate accumulation. If, in this example, the clock runs at 360Hz, this circuit will give a one seconds integration. Different accumulation rates can be obtained by adding more accumulators at different taps along the shift register. The circuit is self-limiting in that once the shift register is filled, and the ADC data turns to a stream of zeroes, eventually the accumulator output will decrease to zero. This is the leaky portion of the integrator, akin to adding a resistor across the integration capacitor in the feedback loop of an analog integrator circuit. The integrator s output data then represents the integrated sum of the ADC data over a fixed time interval. Carrying this idea forward to the IP-QINT-ADC, we implement the accumulated dose processing mechanism in a similar way. Focusing on one channel, the Beam and Test data types each have a separate shift register. Since we accumulate beam data at various rates, the beam SR will have several taps, while the test SR will have one tap at 360 for one second accumulation. Baseline accumulation, averaging and subtraction is performed on the incoming ADC data sample. The next page shows a conceptual block diagram of the accumulate/average/compare module. This diagram focuses on the dataflow. Note that although Beam, Test and Baseline data all come from the same source (the ADC sampling at different times), the paths are shown separately for conceptualization. The Beam and Test ADC data are presented to a subtractor block which takes away any pedestal using a one-second averaged sum. The output of this block is presented to the respective data type shift registers. For simplicity, only the Beam data shift register is shown in this diagram. The Beam data shift register is loaded at each time a new ADC sample comes along, which means that the CLK signal runs at 360Hz. Each time a new ADC sample is presented, the shift register advances and new accumulator values are calculated. The Beam Data SR has taps at 1, 6, 12, 36 and 360 giving the different accumulation rates. The accumulator outputs are the passed to the Comparator block which compares each data IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 13 of 90 J. Dusatko /

14 Fig 4: Accumulate/Average/Compare Subsystem (for one chan) ADC Data (Beam, Test) Baseline Subtraction DIVIDE BY Beam Data SR D1 Q Accum To Test Data SR Q 0 Q 1/60 1 Sec Avg Q6 360 Word Shift Register Accum Q 1/30 Baseline Data Baseline Data SR D1 Q Word Shift Register Q Accum Q12 Q36 Q Accum Accum Q 1/10 Q 1 CLK Comparators Fault Outputs Note: Test Data SR is not shown / connections are similar From Test Data SR value against the window thresholds and signifies a fault if any of the different accumulated values lie outside of the setpoints. The accumulated sums themselves are also available for readout. Control and support logic keep track of which data type is being processed and sequence all of the operations of the subsystem. All eight channels of data are processed the same way. The physical implementation of the AAC subsystem is done is such a way that the ADC channels are actually processed in series instead of parallel. This was due to the limited resources available in the FPGA. Thus, one AAC processing engine exists and the ADC channels are processed in a round-robin fashion. Sequencing and counting logic is used to keep track of the channel and data type and FPGA block memory modules are used to store the intermediate and final results. Because of the complexity of this module, extra diagnostic features are built in that allow viewing of the data at various stages of the AAC data pipeline. These are listed in section 4 of this document. The Fault Data, which is output from the comparators, is mapped to the module s IP I/O memory space. Each channel produces one 16-bit word of fault data. This data is available in raw and latched formats. The raw format is updated at each input trigger. The faults bits are set and must be written to to be cleared for the latched format. In addition to fault data for each channel, summary fault data based on sums within each channel for each data type and across all channels for each data type are provided. The Dose Data and fault thresholds are mapped to IP MEMory space. The MEMory space was used because of the significant amount of data. The Dose data size is actually 25-bits wide and is read out in two 16-bit words. The data width is chosen as this size because it s the maximum quantity the accumulator will sum to for the longest accumulation time (360 cycles), assuming that every word is at maximum positive or negative full-scale. Note that IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 14 of 90 J. Dusatko /

15 the fault thresholds are only 16-bits and are compared against the 25-bit accumulated Dose data values. Therefore the comparison occurs between bits [15:0] of the accumulated sum word and bit [15:0] of the threshold word. The upper bits [24:16] of the accumulated Dose word are not compared. Since normal Dose data is expected to be bounded to 16-bit quantities; with a full-scale 16-bit value is considered to unusually high, 16-bit comparisons were deemed adequate. The full 25-bit quantity is provided for completeness, although practice may show that the full bit width value is not useful. In this case, only the lower 16-bits could then be read out. Registers used by this module: I/O Space: Chan[7:0] Fault Registers Chan[7:0] Latched Fault Registers Summary Fault Registers 0 & 1 Latched Summary Fault Registers 0 & 1 MEM Space: Chan[7:0] Dose Data / Fault Threshold Registers Beam/Test/Baseline Shift Register Raw Data Raw ADC Data Chan[0..11] BLM Baseline Data Chan[0..7] Beam/Test/Baseline Accumulator Raw Data IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 15 of 90 J. Dusatko /

16 Typical Charge Integration signal timing: This section shows a diagram of the timing and sequence relationships of various module signals. This diagram is provided to aid in visualizing the various relationships and timing between input trigger and module operations. Fid Dly in Link-Node GWID = 20us Fiducial TRIG_DLY = 0ns (typ) GDLY = 0ns (typ) Trigger to IP-QINT-ADC Gate Closed Gate opens ~5uS before Beam Time Closed Open Beam GADLY = 2uS (typ) Input Current Pulse Integrator Output ADC Sample GO Beam Time = Fid uS (typ) ADC Samples Integrator output HERE Fig 5: IP-QINT-ADC Charge Integration Acquisition Signal Timing and Sequencing A charge integration acquisition sequence is shown in Figure 5. The Fiducial trigger starts the entire sequence off. This signal is received by the Link-Node, delayed by a fixed amount and used to generate the hardware trigger to the IP-QINT-ADC. This signal must be time-delay such that it allows the Integrator Gate to be opened for approximately 5uS before the beam signal comes. The IP-QINT-ADC also has two adjustable internal delays indicated by the TRIG_DLY and GDLY quantities. They operate sequentially: TRIG_DLY receives the input trigger and waits a programmed amount of time before generating delayed copy of the input trigger to the module s internal subsystems. The Gate Generator subsystem receives this delayed trigger and can further delay the opening of the gate by the amount programmed into the GDLY register. Typically the TRIG_DLY and GDLY registers default to zero settings so that the overall delay is dependent upon the Link-Node trigger processor. As noted on the diagram, the Link-Node trigger delay should be set so that the gate opens about 5us before the beam comes. IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 16 of 90 J. Dusatko /

17 When the beam comes, it creates a current pulse at the detector. The opened gate allows this current pulse to accumulate across the integrating capacitor; the output of the integrator is shown below the current pulse signal. The gate has a default open width of 20us, it can be programmed to a different value if necessary. The gate width was chosen for a typical expected BLM pulse and is wide enough so that the system timing is not too critical. About 2uS before the gate closes, the ADC is commanded to sample. This sampling time is controlled by the GADLY register which adjusts the ADC sampling time relative to the gate closing edge. The 2.0uS value is the default value and was chosen to provide enough time for the current pulse fully collect considering the dispersion effects of the long interconnecting cable. Note that in voltage-sensitive mode, the gate is not present and the ADC samples what would be the input voltage pulse as soon as the input trigger is received. This sample time can be controlled by the TRIG_DLY value. IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 17 of 90 J. Dusatko /

18 3.0 IP-QINT-ADC Module I/O Space Register Descriptions: 3.1 Module Control & Status Register 1 Name: CSR1 Offset: 0x0000 Mode: R/W This is the control and status register for the IP-QINT-ADC module. In contains bits that control the basic board functions and provides status as well. GEN GPL GTS GES DRDY SWT TMIS TES TR_S[1:0] DM_S[1:0] ENA ARM DME RST RST Bit(s): [0] ReSeT (R/W resets to 0) 0x0 = board not reset 0x1 = board is reset Software reset. When asserted, the board is reset: internal registers and counters are cleared and all state machines are brought to their idle states. Note that the programmable registers are NOT reset. This bit does not need to be cleared (it is self-clearing). Reads return 0. DME Bit(s): [1] Diagnostic Mode Enable (read/write read returns set state of bit / resets to 0) 0x0 = Diagnostic mode is DISabled 0x1 = Diagnostic mode is ENAbled When enabled, the board is put into diagnostic mode, which allows control over the sequencing of the three data acquisition steps. This bit is set in conjunction with DM_SEL[1:0] to select the specific diagnostic mode the board should be put in. The board trigger is then used to sequence the diagnostic modes. Note that the board must still be ENAbled and ARMed before triggers can be received. ARM Bit(s): [2] ARM (R/W resets to 0) 0x0 = board is DISarmed and will not receive triggers 0x1 = board is ARMed and will receive and process triggers ARMs the board to begin receiving triggers. When set to 0 during an acq cycle, the action is the same as above. IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 18 of 90 J. Dusatko /

19 ENA Bit(s): [3] ENAble (R/W resets to 0) 0x0 = data acquisition is disabled 0x1 = data acquisition is enabled Enables the board to begin acquiring data, boarm must be armed before receiving triggers. Note that if this bit is set to DISable during an acquisition cycle, the board will complete its current acq cycle and go into the DISable state. DM_S[1:0] Bit(s): [5:4] Diagnostic Mode Select (read/write read returns set state of bit / resets to 00) 0x0: Single-shot beam mode 0x1: Single-shot test mode 0x2: Single-shot baseline mode 0x3: Single-Step mode TR_S[1:0] Bit(s): [7:6] Trigger source select (r/w read returns set state of bits / resets to 0x0) 0x0: External Trigger 1 0x1: External Trigger 2 0x2: Software Trigger 0x3: <reserved> (currently selects SW Trigger) TES Bit(s): [8] Trigger Edge Select: source trigger activating edge select (R/W resets to 1) 0x1 = The positive (rising) edge of the source trigger will activate the module 0x0 = The negative (falling) edge of the source trigger will active the module Selects which edge of the input source trigger (selected by TR_S[1:0]) the module will trigger and perform its acquisition cycle on. Note that for the SW trigger this selection is somewhat nebulous, however the rising edge should be selected so that a trigger will occur when a one is written to the SW trigger bit. If the falling edge is selected, the trigger will occur when the SW trigger pulse falls. The timing of this depends upon the timing between the IP master and the module and can vary from cycle to cycle. IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 19 of 90 J. Dusatko /

20 TMIS Bit(s): [9] Missed trigger status (R/W resets to 0 / reads back the set value / writing 1 clears this bit) Read: 0x0 = Trigger OK 0x1 = Trigger Missed Write: 0x0 = no effect 0x1 = clears bit This bit indicated whether a cycle of the 360Hz continuous trigger has been missed. It is a latching bit, and a one indicates if a trigger has been missed on the last 1/360 sec cycle. Writing a one clears this bit. Note that the updating of this bit is enabled by the ARM bit. SWT Bit(s): [10] Software trigger (R/W; resets to 0) 0x0 = No trigger 0x1 = Trigger Writing a 0x1 to this bit will cause the board to trigger if selected as the trigger source. This bit is self-clearing and does not need to be reset. Note that the trigger edge select affects how this bit is processed. Positive should be selected. Reads return 0. DRDY Bit(s): [11] Data ReaDY (R/W) 0x0 = Board data is NOT ready for readout 0x1 = Board data is READY for readout (write 0x1 clears) This bit indicates when the board has finished acquiring and processing its data (following a trigger) and is ready for readout. This bit is latched and must be cleared by writing a one to it. Note that the written one must be cleared back to zero. GES Bit: [12] Gate Generator Select (R/W) / resets to 0 0x0 = Standard Gate generator is selected 0x1 = Extended-width Gate generator is selected This is the extended-width gate generator select bit. When enabled, the extended width (32-bit) gate generator block is muxed in, while the standard-width (16-bit) gate generator is muxed out (see Fig 1). GTS Bit(s): [13] Gate Trigger Select R/W / resets to 0 0x0 = External trigger used 0x1 = SW trigger used The bit selects which trigger source the gate generator will use. Note that when the external trigger is selected, it will select whichever source the TR_S[1:0] bits are set to. Separate control is provided here for diagnostic purposes. IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 20 of 90 J. Dusatko /

21 GPL Bit(s): [14] Gate Polarity R/W / resets to 1 0x0 = Gate signal polarity is Negative-True (low-going pulse) 0x1 = Gate signal polarity is Positive-True (high-going pulse) Controls the polarity of the charge integrator gate pulse. For most purposes, the polarity will always be positive. GEN Bit(s): [15] Gate Enable R/W / resets to 0 0x0 = Gate output is DISabled 0x1 = Gate output is Enabled Enables the generation of the gate signal. Bits [15:13], along with registers 0x000E & 0x0010 control the ADC integrator Gate signal. This signal opens and closes the charge integrating capacitor shorting switch. Open causes charge to collect on the integrating capacitor, closing causes the charge to be drained off, resetting the capacitor for the next measurement. These control bits control the enabling, polarity and trigger source. Note that in the voltage-sensitive version of the IP- QINT-ADC, the gate signal is not generated; and writing to these bits has no effect. IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 21 of 90 J. Dusatko /

22 3.2 Module Control & Status Register 2 Name: CSR2 Offset: 0x0002 Mode: R/W This is the control and status register for the IP-QINT-ADC module. In contains bits that control the basic board functions and provides status as well. TDEL[7:0] PTS PPL PEN D4L D2L D2L Bit(s): [0] 20MHz DCM Lock Status Read Only / Writes have no effect 0x0 = 20MHz DCM is NOT Locked 0x1 = 20MHz DCM IS Locked This bit gives the lock status of the 20MHz FPGA Digital Clock Manager, which uses the 80MHz board clock to generate its 20Mhz clock. This bit is essentially the lock bit from the internal PLL. D4L Bit(s): [1] 40MHz DCM Lock Status Read Only / Writes have no effect 0x0 = 40MHz DCM is NOT Locked 0x1 = 40MHz DCM IS Locked This bit gives the lock status of the 40MHz FPGA Digital Clock Manager, which uses the 80MHz board clock to generate its 40Mhz clock. This bit is essentially the lock bit from the internal PLL. PEN Bit(s): [4] Test Pulse Enable R/W / resets to 0 0x0 = Test Pulse output is DISabled 0x1 = Test Pulse output is Enabled This bit enables the generation of the output test pulse (or heartbeat ) signal. PPL Bit(s): [5] Test Pulse Polarity R/W / resets to 1 0x0 = Test Pulse signal polarity is Negative-True (low-going pulse) 0x1 = Test Pulse signal polarity is Positive-True (high-going pulse) This bit controls the polarity of the output test pulse signal. IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 22 of 90 J. Dusatko /

23 PTS Bit(s): [6] Test Pulse Trigger Select R/W / resets to 0 0x0 = External trigger used 0x1 = SW trigger used The bit selects which trigger source the test pulse generator will use. Note that when the external trigger is selected, it will select whichever source the TR_S[1:0] bits are set to. Separate control is provided here for diagnostic purposes. <unused/reserved> Bit(s): [7, 3:2] Unused/Reserved Bit (Returns 0) These bits are unused and return 0 when read. Writing to it has no effect. TDEL[7:0] Bit(s): [15:8] Test Acquistion Delay Control (read/write read returns set state of bits / resets to 0x2E) This register controls the delay time between the assertion of the LED test pulse and the acquisition of the resultant detector output charge. The delay unit step size is 25ns. The minimum intrinsic delay, when the register is set to 0x00 is 2 counts due to internal logic delays. Therefore, qty = 2 counts must be added to the set value to reflect the actual delay quantity being generated. This register resets to a default value of 0x2E, which is equal to a delay of 1.2uS (46 counts + 2 for intrinsic delay = 48 counts at 25ns). This delay is set for the BLM system and accounts for the round-trip delays of the cables and the intrinsic delays of the detector and electronics. IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 23 of 90 J. Dusatko /

24 3.3 Module Control & Status Register 3 Name: CSR3 Offset: 0x0004 Mode: R/W This is the control and status register for the IP-QINT-ADC module. In contains bits that control the basic board functions and provides status as well. PIC FBC RNG SM_SEL[3:0] SMDE SYPL SYEN SYEN Bit(s): [0] Sync Output Enable (R/W resets to 0) 0x0 = Sync output is DISabled 0x1 = Sync output is ENAbled Sync output enable control. This bit controls whether the sync output will be asserted or not. SYPL Bit(s): [1] Sync Pulse Polarity R/W / resets to 1 0x0 = Test Pulse signal polarity is Negative-True (low-going pulse or level) 0x1 = Test Pulse signal polarity is Positive-True (high-going pulse or level) This bit controls the polarity of the sync output pulse signal. SMDE Bit(s): [2] Sync Output Mode R/W / resets to 0 0x0 = Sync output is timed pulse mode 0x1 = Sync output is level (output = selected input = raw source signal) This bit controls the output mode of the syc signal. SM_SEL[3:0] Bit(s): [7:4] Sync output pulse source selection mux R/W / resets to 0x0 This bit field selects the source of the sync output signals. The selected signal, when asserted, will cause the sync pulse to be output (after the programmed delay). 0x0 = Trigger Signal 0x1 = Gate Signal 0x2 = ADC_Acq_Go signal 0x3 = Get_Beam_Data signal 0x4 = Get_Test_Data signal 0x5 = Get_Base_Data signal 0x6 = Get_Beam_Data Done signal 0x7 = Get_Test_Data Done signal IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 24 of 90 J. Dusatko /

25 0x8 = Get_Base_Data Done signal 0x9 = Sum_Fault_Beam Monitor Signal 0xA = Sum_Fault_Test Monitor Signal 0xB = Sum_Fault_Base Monitor Signal 0xC = SW Trigger 0xD = <reserved> 0xE = <reserved> 0xF = <reserved> RNG Bit(s): [11] ADC Range Control R/W / resets to 1 0x0 = ADC has +/-10V dynamic range 0x1 = ADC has +/-5V dynamic range (default setting) This bit controls ADC input voltage dynamic range. This bit should only be set during initialization, before the ADC receives at SW reset. Note that when in +/-5V range, the ADC has a resolution of 153uV/count; when in +/-10V range, the resolution changes to 305uV/count. Note the range should be set BEFORE SW_RST is issued. <unused/reserved> Bit(s): [13:12], [10:8] & [3] Unused/Reserved Bit (Returns 0) These bits are unused and return 0 when read. Writing to it has no effect. FBC Bit(s): [14] Force Baseline Clear Control R/W / resets to state set in gateware 0x0 = Baseline Correction is applied to incoming data 0x1 = Baseline Correction is NOT applied to incoming data This bit controls whether the Baseline Correction function is applied. When cleared, the baseline corrector functions normally, applying the baseline correction value calculated on the previous acq cycle to the incoming ADC samples. When this bit is set, the baseline correction holding register is kept is constant clear, essentially subtracting a value of 0x0000 from the incoming ADC samples. PIC Bit(s): [15] PIC mode bit Read Only / resets to state set in gateware 0x0 = Module is in BLM mode 0x1 = Module is in PIC mode This bit indicates the mode that the board is in. This bit is set in firmware and is read only. It is provided as status information for the developer. When is BLM mode, the module performs the acquisition sequenced as described in section 2.0 of this document. When in PIC mode, the module only performs a beam acquisition; this mode is described in Appendix A, PIC mode operation, of this document. IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 25 of 90 J. Dusatko /

26 3.4 Trigger Delay Register Name: TRDEL Offset: 0x0006 Mode: R/W This register sets the delay time from the trigger input to actual beginning of the data acquisition cycle. The timing resolution is 25.0 ns per count. Note that there is an intrinsic delay latency of (3) clock cycles; this must be taken into account when setting the delay value. Trigger Assertion Delay Value TRIG_DLY Bit(s): [15:0] Trigger delay setting (R/W resets to 0 / read returns set value) 0x0000: minimum delay value = (3) 25ns clk40 cycles 75ns 0xFFFF: maximum setting ( = cycles ms) 1 count = 25ns This register controls the delay between the reception of the acquisition trigger and the actual beginning of the acquisition cycle. There is an intrinsic three cycle latency due to logic, thus 3 must be added to the decimal set value to reflect that actual delay setting. IP_QINT_ADC_SW_Prog_Guide_V3d0.doc Page 26 of 90 J. Dusatko /