CDA 4253 FPGA System Design FPGA Architectures. Hao Zheng Dept of Comp Sci & Eng U of South Florida
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1 CDA 4253 FPGA System Design FPGA Architectures Hao Zheng Dept of Comp Sci & Eng U of South Florida
2 FPGAs Generic Architecture Also include common fixed logic blocks for higher performance: On-chip mem. DSP/MulHplier Fast arithmehc logic Microprocessors CommunicaHon logic
3 Programming Technologies
4 Programming Technologies: Fuses
5 Programming Technologies: Fuses
6 Programming Technologies: An?-fuses
7 Programming Technologies: An?-fuses
8 Programming Technologies: FLASH
9 Programming Technologies: SRAM Transistor SRAM 1 0 Open Closed
10 Sta?c RAM Cell
11
12 Basic Logic Elements (BLEs) Basic component that can be programmed to logic funchons and provide storage.
13 Lookup Tables (LUTs) SRAM SRAM SRAM SRAM x y Commercial FPGAs Xilinx: 6-LUT Altera: 6-LUT Microsemi: 4-LUT For x-input LUT, it can be programmed into one of funchons. 2 2x
14 LUT = Programmable Truth Table x y x y z A B C z 0 0 A 0 1 B 1 0 C 1 1 D D 11 Also called funchon generator.
15 AND x y x y z z
16 OR x y x y z z
17 NAND x y x y z z
18 NOR x y x y z z
19 XOR XNOR x y x y z z 11 11
20 z = y z = y + x x y x y z z 11 11
21 Features of LUTs A LUT is a piece of RAM. Can be configured as distributed RAM in Xilinx. Can be configured as shix registers. A n-lut can implement any n-input logic funchons. Logic minimizahon should reduce the number of inputs, not logical operators. All logic funchons implemented by a n-lut have the same propagahon delay.
22 Look-up-tables (LUTs) Why aren t FPGAs just a big LUT? Size of truth table grows exponentially based on # of inputs 3 inputs = 8 rows, 4 inputs = 16 rows, 5 inputs = 32 rows, etc. Same number of rows in truth table and LUT LUTs grow exponentially based on # of inputs Number of SRAM bits in a LUT = 2 i * o i = # of inputs, o = # of outputs Example: 64 input combinational logic with 1 output would require 2 64 SRAM bits 1.84 x SRAM bits required. Clearly, not feasible to use large LUTs So, how do FPGAs implement logic with many inputs?
23 Look-up-tables (LUTs) Map circuits onto multiple LUTs Divide circuit into smaller circuits that fit in LUTs (same # of inputs and outputs) Example: 2-input LUTs
24 Configurable Logic Blocks Number of BLEs are grouped with a local network in order to implement funchons with a large number of inputs and mulhple outputs.
25 Configurable Logic Blocks (CLBs) Example: Ripple-carry adder Each LUT implements 1 full adder Use efficient connections between LUTs for carry signals A(1) B(1) A(0) B(0) Cin(0) 2x1 Cin(1) CLB 3-in, 2-out LUT 3-in, 2-out LUT FF FF FF FF 2x1 2x1 Cout(0) 2x1 2x1 Cout(1) S(1) S(0)
26 Programmable Interconnect
27 FPGA Rou?ng Architectures Must be flexible to accommodate various circuit implementa6ons.
28 Connec?on Boxes Programmable switches SRAM
29 Switch Boxes SRAM cell
30 Segmented Rou?ng Short wires: many, local connechons. Long wires: few, low latency, carrying global signals Dedicated long wires for clock/reset signals
31 Hierarchical Rou?ng Architecture Most designs display locality of connec6ons hierarchical rou6ng architecture.
32 FPGA Configura?on
33 Configura?on Comes at a Cost 1T 6T SRAM 4-6 T SRAM 4T SRAM + ConfiguraHon circuitry + Error detechon/correchon + Security features h^ps://en.wikipedia.org/wiki/stahc_randomaccess_memory
34 FPGA Design Flow
35 FPGA CAD Flow Input: A circuit (netlist) Output: FPGA configurahon bitstream Main (Algorithmic) Stages: Logic synthesis/ophmizahon Technology mapping Packing/placement RouHng Bitstream generahon
36 Xilinx FPGA Architecture DS099-1_01_032703
37 Xilinx 7-Series FPGA Architecture Precise, Low Ji^er Clocking On-Chip block RAM On-Chip block RAM Hi-performance Serial I/O Connec?vity Transceiver Technology Hi-performance Serial I/O Connec?vity Transceiver Technology Logic Fabric Logic Fabric DSP Slices
38 Xilinx Ar?x-7 Low end 7-series FPGA manufactured using 28nm Based on 6-input LUT Configurable as distributed memory Support DDR3 memory interfaces High-speed serial interfaces supporhng mulhgigabit communicahons On-chip DSPs, mulhpliers, and block RAMs Clock management Htles to provide high precise and low ji^er clock signals
39 Xilinx Ar?x-7 Device Logic Cells Configurable Logic Blocks (CLBs) Slices (1) Max Distributed RAM (Kb) DSP48E1 Slices (2) Block RAM Blocks (3) 18 Kb 36 Kb Max (Kb) XC7A15T 16,640 2, XC7A35T 33,280 5, ,800 XC7A50T 52,160 8, ,700 XC7A75T 75,520 11, ,780 XC7A100T 101,440 15,850 1, ,860 XC7A200T 215,360 33,650 2, ,140
40 Xilinx Ar?x-7 Device Configurable Logic Blocks (CLBs) CMTs Logic DSP48E1 Cells (4) PCIe (5) XADC GTPs Total I/O Max Slices (2) Slices (1) Blocks Banks (6) Distributed RAM (Kb) Block RAM Block Max User I/O (7) 18 Kb 36 Kb XC7A15T 16, , XC7A35T 33, , XC7A50T 52, , XC7A75T 75, , XC7A100T 101, , , XC7A200T 215, , ,
41 Xilinx Ar?x-7 - CLBs COUT COUT 8 6-LUTs 16 FFs 2 carry chains 256b distributed RAM 128b shi` register Switch Matrix CLB Slice(0) Slice(1) The abundant FFs can be used to improve design performance with pipelining. CIN CIN UG474_c1_01_071910
42 Xilinx Ar?x-7 CLBs Slice Architecture Slice LUT 4 6-LUTs 8 FFs Carry logic for fast addihon
43 Xilinx Ar?x-7 CLBs Slice Architecture Slice Wide-funcHon MUXs to implement funchons with 8 inputs. LUT LUT F7 MUX LUT F8 MUX LUT F7 MUX WP405_06_013012
44 Xilinx Ar?x-7 CLBs 6-LUTs 6-Input LUT D Q CE CLK S/R Register O6 O5 D Q CE CLK S/R Register Each 6-LUT implements any 6-input funchons, or Two 5-input funchons with shared inputs.
45 Distributed RAMs Slices in CLBs of type SLICEM can be configured as synchronous RAMs 256x1b single port 128x1b dual/single port Can also be configured as ROM with up to 256b. Can be instanhated by using special VHDL components.
46 HW, SW, and FPGA TradiHonal approaches to computahon: HW & SW HW (ASICs) Fixed on a parhcular applicahon Efficient: performance, silicon area, power Higher cost/per applicahon SW (microprocessors) Used in many applicahons Less efficient: performance, silicon area, power Lower cost/per applicahon
47 HW, SW, and FPGA Field Programmable Gate Arrays (FPGAs) SpaHal compuhng: similar to HW Reprogrammable: similar to SW Faster than SW and more flexible than HW Harder to program than SW Less efficient than HW: performance, power consumphon & silicon area
48 Temporal vs Spa?al Compu?ng (SW vs. HW) 2 y = Ax + Bx + C Temporal Computation Spatial Computation t1 = x t2 = t1 * A t2 = t2 + B t2 = t2 * t1 y = t2 + C t1 t2 A B x A * * * + B C C + Y
49 Why SW is Slower? Generality: InstrucHon set may not provide the operahons your program needs Processors provide hardware that may not be useful in every program or in every cycle of a given program: MulHpliers, Dividers InstrucHon Memory Program instruchons and intermediate results stored in memory. Accessing memory is very slow. Bit Width Mismatches General purpose processors have a fixed bit width, and all computahons are performed on that many bits
50 Why not just Use HW Dedicated -> not programmable. Takes long Hme and high cost to design and develop (typical processor takes a handful of years to design, with design teams of a few hundred engineers) High non-recurring cost (NRE) -> very expensive! JusHficaHon for high cost: high volume applicahons, or high-performance is more desired
51 ASIC vs FPGA
52 Reading Paper at h^p:// FPGA Architectures: An Overview SecHon 2.1, 2.2, 2.3, 2.4 (skip , , ), Skim 2.6
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