Configurable Logic Blocks (CLBs)

Transcription

1 Chapter Configurable Logic Blocks (CLBs) CLB Overview The Configurable Logic Blocks (CLBs) are the main logic resources for implementing sequential as well as combinatorial circuits. Each CLB element is connected to a switch matrix for access to the general routing matrix (shown in Figure -1). A CLB element contains a pair of slices. These two slices do not have direct connections to each other, and each slice is organized as a column. Each slice in a column has an independent carry chain. For each CLB, slices in the bottom of the CLB are labeled as SLI(0), and slices in the top of the CLB are labeled as SLI(1). X-Ref Target - Figure -1 COUT COUT CLB Slice(1) Switch Matrix Slice(0) CIN CIN UG190 01_1220 Figure -1: Arrangement of Slices within the CLB The Xilinx tools designate slices with the following definitions. An X followed by a number identifies the position of each slice in a pair as well as the column position of the slice. The X number counts slices starting from the bottom in sequence 0, 1 (the first CLB column); 2, 3 (the second CLB column); etc. A Y followed by a number identifies a row of slices. The number remains the same within a CLB, but counts up in sequence from one CLB row to the next CLB row, starting from the bottom. Figure -2 shows four CLBs located in the bottom-left corner of the die. Virtex- FPGA User Guide 173

2 Chapter : Configurable Logic Blocks (CLBs) X-Ref Target - Figure -2 COUT COUT COUT COUT CLB Slice X1Y1 CLB Slice X3Y1 Slice X0Y1 Slice X2Y1 CIN CIN CIN CIN CLB COUT Slice X1Y0 COUT CLB COUT Slice X3Y0 COUT Slice X0Y0 Slice X2Y0 UG190 02_1220 Figure -2: Row and Column Relationship between CLBs and Slices Slice escription Every slice contains four logic-function generators (or look-up tables), four storage elements, wide-function multiplexers, and carry logic. These elements are used by all slices to provide logic, arithmetic, and ROM functions. In addition to this, some slices support two additional functions: storing data using distributed RAM and shifting data with 32-bit registers. Slices that support these additional functions are called SLIM; others are called SLIL. SLIM (shown in Figure -3) represents a superset of elements and connections found in all slices. SLIL is shown in Figure Virtex- FPGA User Guide

3 Virtex- FPGA User Guide 17 CLB Overview X-Ref Target - Figure -3 Figure -3: iagram of SLIM A I2 COUT X C CX B BX A AX I1 MC31 O UG190_c_03_ A A4 A3 A2 A1 I MUX Q C CQ CMUX B BQ BMUX A AQ AMUX Reset Type X WA1-WA WA7 WA8 PRAM4/32 SPRAM4/32 SRL32 SRL1 RAM ROM PRAM4/32 SPRAM4/32 SRL32 SRL1 RAM ROM PRAM4/32 SPRAM4/32 SRL32 SRL1 RAM ROM PRAM4/32 SPRAM4/32 SRL32 SRL1 RAM ROM FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV CK FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV CK FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV CK FF LATCH INIT1 INIT0 SRHIGH SRLOW SR REV Q CK WSGEN CIN 0/1 Sync Async A I2 I1 MC31 O A A4 A3 A2 A1 C CI CX C C4 C3 C2 C1 A I2 I1 MC31 O A A4 A3 A2 A1 B BI BX B B4 B3 B2 B1 A I2 I1 MC31 O A A4 A3 A2 A1 A AI AX SR A A4 A3 A2 A1 Q Q Q WA1-WA WA7 WA8 WA1-WA WA7 WA8 WA1-WA WA7 WA8

4 Chapter : Configurable Logic Blocks (CLBs) X-Ref Target - Figure -4 COUT Reset Type Sync Async MUX X A A A4 A3 A2 A1 ROM O X CK FF LATCH INIT1 Q INIT0 SRHIGH SRLOW SR REV Q CMUX C C C4 C3 C2 C1 CX A A A4 A3 A2 A1 ROM O C CX CK FF LATCH INIT1 Q INIT0 SRHIGH SRLOW SR REV C CQ BMUX B B B4 B3 B2 B1 BX A A A4 A3 A2 A1 ROM O B BX CK FF LATCH INIT1 Q INIT0 SRHIGH SRLOW SR REV B BQ AMUX A A A4 A3 A2 A1 AX SR A A A4 A3 A2 A1 ROM O 0/1 A AX CK FF LATCH INIT1 Q INIT0 SRHIGH SRLOW SR REV A AQ CIN UG190 04_0320 Figure -4: iagram of SLIL Each CLB can contain zero or one SLIM. Every other CLB column contains a SLIMs. In addition, the two CLB columns to the left of the SP48E columns both contain a SLIL and a SLIM Virtex- FPGA User Guide

5 CLB Overview CLB/Slice Configurations Table -1 summarizes the logic resources in one CLB. Each CLB or slice can be implemented in one of the configurations listed. Table -2 shows the available resources in all CLBs. Table -1: Logic Resources in One CLB Slices s Flip-Flops Arithmetic and Carry Chains istributed RAM (1) Shift Registers (1) Table -2: evice bits 128 bits Notes: 1. SLIM only, SLIL does not have distributed RAM or shift registers. Virtex- FPGA Logic Resources Available in All CLBs CLB Array Row x Column Number of -Input s Maximum istributed RAM (Kb) Shift Register (Kb) Number of Flip-Flops XCVLX20T 0 x 2 12, ,480 XCVLX30 80 x 30 19, ,200 XCVFX30T 80 x 38 20, ,480 XCVLX30T 80 x 30 19, ,200 XCVSX3T 80 x 34 21, ,70 XCVLX0 120 x 30 28, ,800 XCVLX0T 120 x 30 28, ,800 XCVSX0T 120 x 34 32, ,40 XCVFX70T 10 x 38 44, ,800 XCVLX8 120 x 4 1, ,840 XCVLX8T 120 x 4 1, ,840 XCVSX9T 10 x 4 8,880 1, ,880 XCVFX100T 10 x 4,000 1, ,000 XCVLX x 4 9,120 1, ,120 XCVLX110T 10 x 4 9,120 1, ,120 XCVFX130T 200 x 81,920 1, ,920 XCVTX10T 200 x 8 92,800 1, ,800 XCVLX1 10 x 7 97,280 1, ,280 XCVLX1T 10 x 7 97,280 1, ,280 XCVFX200T 240 x 8 122,880 2, ,880 XCVLX x ,240 2, ,240 XCVLX220T 10 x ,240 2, ,240 XCVSX240T 240 x ,70 4, ,70 XCVTX240T 240 x ,70 2, ,70 XCVLX x ,30 3, ,30 XCVLX330T 240 x ,30 3, ,30 Virtex- FPGA User Guide 177

6 Chapter : Configurable Logic Blocks (CLBs) Look-Up Table () The function generators in Virtex- FPGAs are implemented as six-input look-up tables (s). There are six independent inputs (A inputs - A1 to A) and two independent outputs (O and ) for each of the four function generators in a slice (A, B, C, and ). The function generators can implement any arbitrarily defined six-input Boolean function. Each function generator can also implement two arbitrarily defined five-input Boolean functions, as long as these two functions share common inputs. Only the output of the function generator is used when a six-input function is implemented. Both O and are used for each of the five-input function generators implemented. In this case, A is driven High by the software. The propagation delay through a is independent of the function implemented, or whether one six-input or two five-input generators are implemented. Signals from the function generators can exit the slice (through A, B, C, output for or AMUX, BMUX, CMUX, MUX output for O), enter the XOR dedicated gate from an output (see Fast Lookahead Carry Logic ), enter the carry-logic chain from an O output (see Fast Lookahead Carry Logic ), enter the select line of the carry-logic multiplexer from output (see Fast Lookahead Carry Logic ), feed the input of the storage element, or go to F7AMUX/F7BMUX from output. In addition to the basic s, slices contain three multiplexers (F7AMUX, F7BMUX, and F8MUX). These multiplexers are used to combine up to four function generators to provide any function of seven or eight inputs in a slice. F7AMUX and F7BMUX are used to generate seven input functions from s A and B, or C and, while F8MUX is used to combine all s to generate eight input functions. Functions with more than eight inputs can be implemented using multiple slices. There are no direct connections between slices to form function generators greater than eight inputs within a CLB or between slices. Storage Elements The storage elements in a slice can be configured as either edge-triggered -type flip-flops or level-sensitive latches. The input can be driven directly by a output via AFFMUX, BFFMUX, CFFMUX or FFMUX, or by the BYPASS slice inputs bypassing the function generators via AX, BX, CX, or X input. When configured as a latch, the latch is transparent when the is Low. The control signals clock (CK), clock enable (), set/reset (SR), and reverse (REV) are common to all storage elements in one slice. When one flip-flop in a slice has SR or enabled, the other flip-flops used in the slice will also have SR or enabled by the common signal. Only the signal has independent polarity. Any inverter placed on the clock signal is automatically absorbed. The, SR, and REV signals are active High. All flip-flop and latch primitives have and non- versions. The SR signal forces the storage element into the state specified by the attribute SRHIGH or SRLOW. SRHIGH forces a logic High at the storage element output when SR is asserted, while SRLOW forces a logic Low at the storage element output. When SR is used, an optional second input (X) forces the storage element output into the opposite state via the REV pin. The reset condition is predominant over the set condition (see Figure -). Table -3 and Table -4 provide truth tables for SR and REV depending on whether SRLOW or SRHIGH is used. Table -3: Truth Table when SRLOW is Used (efault Condition) SR REV Function 0 0 No Logic Change Virtex- FPGA User Guide

7 CLB Overview Table -3: Truth Table when SRLOW is Used (efault Condition) (Continued) SR REV Function Table -4: Truth Table when SRHIGH is Used SR REV Function 0 0 No Logic Change X-Ref Target - Figure - CK FF FF LATCH INIT1 INIT0 SRHIGH Q SRLOW SR REV Q X CX C CK CFF FF LATCH INIT1 INIT0 SRHIGH Q SRLOW SR REV CQ SR BX B CK BFF FF LATCH INIT1 INIT0 SRHIGH Q SRLOW SR REV Reset Type Sync Async BQ AX A CK AFF FF LATCH INIT1 INIT0 SRHIGH Q SRLOW SR REV AQ Figure -: UG190 0_ Register/Latch Configuration in a Slice SRHIGH and SRLOW can be set individually for each storage element in a slice. The choice of synchronous (SYNC) or asynchronous (ASYNC) set/reset (SRTYPE) cannot be set individually for each storage element in a slice. Virtex- FPGA User Guide 179

8 Chapter : Configurable Logic Blocks (CLBs) The initial state after configuration or global initial state is defined by separate INIT0 and INIT1 attributes. By default, setting the SRLOW attribute sets INIT0, and setting the SRHIGH attribute sets INIT1. Virtex- devices can set INIT0 and INIT1 independent of SRHIGH and SRLOW. The configuration options for the set and reset functionality of a register or a latch are as follows: No set or reset Synchronous set Synchronous reset Synchronous set and reset Asynchronous set (preset) Asynchronous reset (clear) Asynchronous set and reset (preset and clear) istributed RAM and Memory (Available in SLIM only) Multiple s in a SLIM can be combined in various ways to store larger amount of data. The function generators (s) in SLIMs can be implemented as a synchronous RAM resource called a distributed RAM element. RAM elements are configurable within a SLIM to implement the following: Single-Port 32 x 1-bit RAM ual-port 32 x 1-bit RAM Quad-Port 32 x 2-bit RAM Simple ual-port 32 x -bit RAM Single-Port 4 x 1-bit RAM ual-port 4 x 1-bit RAM Quad-Port 4 x 1-bit RAM Simple ual-port 4 x 3-bit RAM Single-Port 128 x 1-bit RAM ual-port 128 x 1-bit RAM Single-Port 2 x 1-bit RAM istributed RAM modules are synchronous (write) resources. A synchronous read can be implemented with a storage element or a flip-flop in the same slice. By placing this flipflop, the distributed RAM performance is improved by decreasing the delay into the clockto-out value of the flip-flop. However, an additional clock latency is added. The distributed elements share the same clock input. For a write operation, the Write Enable () input, driven by either the or pin of a SLIM, must be set High Virtex- FPGA User Guide

9 CLB Overview Table - shows the number of s (four per slice) occupied by each distributed RAM configuration. Table -: istributed RAM Configuration RAM Number of s 32 x 1S 1 32 x x 2Q (2) 4 32 x SP (2) 4 4 x 1S 1 4 x x 1Q (3) 4 4 x 3SP (3) x 1S x x 1S 4 Notes: 1. S = single-port configuration; = dual-port configuration; Q = quad-port configuration; SP = simple dual-port configuration. 2. RAM32M is the associated primitive for this configuration. 3. RAM4M is the associated primitive for this configuration. For single-port configurations, distributed RAM has a common address port for synchronous writes and asynchronous reads. For dual-port configurations, distributed RAM has one port for synchronous writes and asynchronous reads, and another port for asynchronous reads. In simple dual-port configuration, there is no data out (read port) from the write port. For quad-port configurations, distributed RAM has one port for synchronous writes and asynchronous reads, and three additional ports for asynchronous reads. In single-port mode, read and write addresses share the same address bus. In dual-port mode, one function generator is connected with the shared read and write port address. The second function generator has the A inputs connected to a second read-only port address and the WA inputs shared with the first read/write port address. Figure - through Figure -14 illustrate various example distributed RAM configurations occupying one SLIM. When using x2 configuration (RAM32X2Q), A and WA are driven High by the software to keep O and independent. Virtex- FPGA User Guide 181

10 Chapter : Configurable Logic Blocks (CLBs) X-Ref Target - Figure - RAM 32X2Q I[1] I[0] AR[4:0] W (X) (AI/BI/CI/I) [:1] () () PRAM32 I1 I2 A[:1] WA[:1] O O[0] O[1] PRAM32 ARC[4:0] C[:1] I1 I2 A[:1] WA[:1] O OC[0] OC[1] ARB[4:0] B[:1] PRAM32 I1 I2 A[:1] WA[:1] O OB[0] OB[1] ARA[4:0] A[:1] PRAM32 I1 I2 A[:1] WA[:1] O OA[0] OA[1] UG190 0_03270 Figure -: istributed RAM (RAM32X2Q) Virtex- FPGA User Guide

11 CLB Overview X-Ref Target - Figure -7 RAM 32XSP unused unused WAR[:1] WAR[] = 1 W [:1] () () I1 I2 A[:1] WA[:1] PRAM32 ATA[1] ATA[2] RAR[:1] RAR[] = 1 C[:1] PRAM32 I1 I2 A[:1] WA[:1] O O[1] O[2] ATA[3] ATA[4] B[:1] PRAM32 I1 I2 A[:1] WA[:1] O O[3] O[4] ATA[] ATA[] A[:1] PRAM32 I1 I2 A[:1] WA[:1] O O[] O[] UG190 0_03270 Figure -7: istributed RAM (RAM32XSP) Virtex- FPGA User Guide 183

12 Chapter : Configurable Logic Blocks (CLBs) X-Ref Target - Figure -8 RAM4X1S (X) I1 SPRAM4 O A[:0] W ([:1]) () (/) A[:1] WA[:1] Q Registered ug190 07_03270 Figure -8: istributed RAM (RAM4X1S) If four single-port 4 x 1-bit modules are built, the four RAM4X1S primitives can occupy a SLIM, as long as they share the same clock, write enable, and shared read and write port address inputs. This configuration equates to 4 x 4-bit single-port distributed RAM. X-Ref Target - Figure -9 RAM4X1 (X) I1 PRAM4 SPO A[:0] W ([:1]) () (/) A[:1] WA[:1] Q Registered I1 PRAM4 PO PRA[:0] (C[:1]) A[:1] WA[:1] Q Registered UG190 09_000 Figure -9: istributed RAM (RAM4X1) If two dual-port 4 x 1-bit modules are built, the two RAM4X1 primitives can occupy a SLIM, as long as they share the same clock, write enable, and shared read and write port address inputs. This configuration equates to 4 x 2-bit dual-port distributed RAM Virtex- FPGA User Guide

13 CLB Overview X-Ref Target - Figure -10 RAM4X1Q I (X) I1 PRAM4 O AR W ([:1]) () () A[:1] WA[:1] Q Registered I1 PRAM4 OC ARC (C[:1]) A[:1] WA[:1] Q Registered I1 PRAM4 OB ARB (B[:1]) A[:1] WA[:1] Q Registered I1 PRAM4 OA ARA (A[:1]) A[:1] WA[:1] Q Registered ug190 10_03270 Figure -10: istributed RAM (RAM4X1Q) Virtex- FPGA User Guide 18

14 Chapter : Configurable Logic Blocks (CLBs) X-Ref Target - Figure -11 RAM 4X3SP unused unused WAR[:1] W [:1] () () I1 I2 A[:1] WA[:1] PRAM32 ATA[1] RAR[:1] C[:1] PRAM32 I1 I2 A[:1] WA[:1] O O[1] ATA[2] B[:1] PRAM32 I1 I2 A[:1] WA[:1] O O[2] ATA[3] A[:1] PRAM32 I1 I2 A[:1] WA[:1] O O[3] UG190 0_000 Figure -11: istributed RAM (RAM4X3SP) Implementation of distributed RAM configurations with depth greater than 4 requires the usage of wide-function multiplexers (F7AMUX, F7BMUX, and F8MUX) Virtex- FPGA User Guide

15 CLB Overview X-Ref Target - Figure -12 A (CX) RAM128X1S (X) I1 SPRAM4 A[:0] W [:0] 7 () (/) A[:1] WA[7:1] 0 [:0] 7 SPRAM4 I1 A[:1] WA[7:1] F7BMUX Q Registered ug190 12_000 Figure -12: istributed RAM (RAM128X1S) If two single-port 128 x 1-bit modules are built, the two RAM128X1S primitives can occupy a SLIM, as long as they share the same clock, write enable, and shared read and write port address inputs. This configuration equates to 128 x 2-bit single-port distributed RAM. Virtex- FPGA User Guide 187

16 Chapter : Configurable Logic Blocks (CLBs) X-Ref Target - Figure -13 RAM128X1 A (CX) X I1 PRAM4 A[:0] W 7 () () A[:1] WA[7:1] SPO 7 PRAM4 I1 A[:1] WA[7:1] F7BMUX Q Registered I1 PRAM4 PRA[:0] 7 A[:1] WA[7:1] PO AX 7 PRAM4 I1 A[:1] WA[7:1] F7AMUX Q Registered UG190 13_000 Figure -13: istributed RAM (RAM128X1) Virtex- FPGA User Guide

17 CLB Overview X-Ref Target - Figure -14 RAM2X1S I1 SPRAM4 A[7:0] W 8 () (/) A[:1] WA[8:1] A (CX) I1 SPRAM4 F7BMUX 8 A[:1] WA[8:1] A7 (BX) O I1 SPRAM4 F8MUX Q Registered 8 A[:1] WA[8:1] A (AX) I1 SPRAM4 F7AMUX 8 A[:1] WA[8:1] UG190 14_000 Figure -14: istributed RAM (RAM2X1S) istributed RAM configurations greater than the provided examples require more than one SLIM. There are no direct connections between slices to form larger distributed RAM configurations within a CLB or between slices. Virtex- FPGA User Guide 189

18 Chapter : Configurable Logic Blocks (CLBs) istributed RAM ata Flow Synchronous Write Operation The synchronous write operation is a single clock-edge operation with an active-high write-enable () feature. When is High, the input () is loaded into the memory location at address A. Asynchronous Read Operation The output is determined by the address A (for single-port mode output/spo output of dual-port mode), or address PRA (PO output of dual-port mode). Each time a new address is applied to the address pins, the data value in the memory location of that address is available on the output after the time delay to access the. This operation is asynchronous and independent of the clock signal. istributed RAM Summary Single-port and dual-port modes are available in SLIMs. A write operation requires one clock edge. Read operations are asynchronous (Q output). The data input has a setup-to-clock timing specification. Read Only Memory (ROM) Each function generator in SLIMs and SLILs can implement a 4 x 1-bit ROM. Three configurations are available: ROM4x1, ROM128x1, and ROM2x1. ROM contents are loaded at each device configuration. Table - shows the number of s occupied by each ROM configuration. Table -: ROM Configuration ROM Number of s 4 x x x 1 4 Shift Registers (Available in SLIM only) A SLIM function generator can also be configured as a 32-bit shift register without using the flip-flops available in a slice. Used in this way, each can delay serial data anywhere from one to 32 clock cycles. The shiftin (I1 pin) and shiftout Q31 (MC31 pin) lines cascade s to form larger shift registers. The four s in a SLIM are thus cascaded to produce delays up to 128 clock cycles. It is also possible to combine shift registers across more than one SLIM. Note that there are no direct connections between slices to form longer shift registers, nor is the MC31 output at B/C/ available. The resulting programmable delays can be used to balance the timing of data pipelines. Applications requiring delay or latency compensation use these shift registers to develop efficient designs. Shift registers are also useful in synchronous FIFO and content addressable memory (CAM) designs. The write operation is synchronous with a clock input () and an optional clock enable (). A dynamic read access is performed through the -bit address bus, A[4:0]. The LSB of the is unused and the software automatically ties it to a logic High. The configurable shift registers cannot be set or reset. The read is asynchronous; however, a storage element Virtex- FPGA User Guide

19 CLB Overview or flip-flop is available to implement a synchronous read. In this case, the clock-to-out of the flip-flop determines the overall delay and improves performance. However, one additional cycle of clock latency is added. Any of the 32 bits can be read out asynchronously (at the outputs) by varying the -bit address. This capability is useful in creating smaller shift registers (less than 32 bits). For example, when building a 13-bit shift register, simply set the address to the 13 th bit. Figure -1 is a logic block diagram of a 32-bit shift register. X-Ref Target - Figure -1 SHIFTIN (MC31 of Previous ) SRLC32E SHIFTIN () A[4:0] (AX) (A[:2]) SRL32 I1 MC31 A[:2] SHIFTOUT (Q31) () (/) Q (Q) (AQ) Registered ug190 1_000 Figure -1: 32-bit Shift Register Configuration Figure -1 illustrates an example shift register configuration occupying one function generator. X-Ref Target - Figure -1 SHIFTIN () 32-bit Shift Register SHIFTOUT(Q31) Address (A[4:0]) MUX Q UG190 1_000 Figure -1: Representation of a Shift Register Virtex- FPGA User Guide 191

20 Chapter : Configurable Logic Blocks (CLBs) Figure -17 shows two 1-bit shift registers. The example shown can be implemented in a single. X-Ref Target - Figure -17 SRL1 SHIFTIN1 (AX) I1 O A[3:0] 4 A[:2] SRL1 SHIFTIN2 (AI) I2 4 A[:2] MC31 UG190 17_000 Figure -17: ual 1-bit Shift Register Configuration As mentioned earlier, an additional output (MC31) and a dedicated connection between shift registers allows connecting the last bit of one shift register to the first bit of the next, without using the output. Longer shift registers can be built with dynamic access to any bit in the chain. The shift register chaining and the F7AMUX, F7BMUX, and F8MUX multiplexers allow up to a 128-bit shift register with addressable access to be implemented in one SLIM. Figure -18 through Figure -20 illustrate various example shift register configurations that can occupy one SLIM. X-Ref Target - Figure -18 SRL32 SHIFTIN () I1 A[:0] () (/) A[:2] MC31 A (AX) (Q) I1 SRL32 F7AMUX Q (AQ) Registered A[:2] MC31 (MC31) SHIFTOUT (Q3) UG190 18_000 Figure -18: 4-bit Shift Register Configuration Virtex- FPGA User Guide

21 CLB Overview X-Ref Target - Figure -19 CX (A) SRL32 SHIFTIN () I1 A[:0] () (/) A[:2] MC31 F7BMUX BX (A) (BMUX) (Q) F8MUX Q (BQ) Registered SRL32 I1 A[:2] MC31 AX (A) I1 A[:2] SRL32 Not Used F7AMUX UG190_c_19_ Figure -19: 9-bit Shift Register Configuration Virtex- FPGA User Guide 193

22 Chapter : Configurable Logic Blocks (CLBs) X-Ref Target - Figure -20 SHIFTIN () I1 SRL32 A[:0] () (/) A[:2] MC31 CX (A) I1 SRL32 F7BMUX A[:2] I1 MC31 SRL32 BX (A) F8MUX Q (BMUX) (BQ) (Q) Registered A[:2] MC31 AX (A) I1 SRL32 F7AMUX A[:2] MC31 (MC31) SHIFTOUT (Q127) UG190 20_000 Figure -20: 128-bit Shift Register Configuration It is possible to create shift registers longer than 128 bits across more than one SLIM. However, there are no direct connections between slices to form these shift registers. Shift Register ata Flow Shift Operation The shift operation is a single clock-edge operation, with an active-high clock enable feature. When enable is High, the input () is loaded into the first bit of the shift register. Each bit is also shifted to the next highest bit position. In a cascadable shift register configuration, the last bit is shifted out on the M31 output. The bit selected by the -bit address port (A[4:0]) appears on the Q output. ynamic Read Operation The Q output is determined by the -bit address. Each time a new address is applied to the -input address pins, the new bit position value is available on the Q output after the time Virtex- FPGA User Guide

23 CLB Overview delay to access the. This operation is asynchronous and independent of the clock and clock-enable signals. Static Read Operation If the -bit address is fixed, the Q output always uses the same bit position. This mode implements any shift-register length from 1 to 32 bits in one. The shift register length is (N+1), where N is the input address (0 31). The Q output changes synchronously with each shift operation. The previous bit is shifted to the next position and appears on the Q output. Shift Register Summary A shift operation requires one clock edge. ynamic-length read operations are asynchronous (Q output). Static-length read operations are synchronous (Q output). The data input has a setup-to-clock timing specification. In a cascadable configuration, the Q31 output always contains the last bit value. The Q31 output changes synchronously after each shift operation. Multiplexers Function generators and associated multiplexers in Virtex- FPGAs can implement the following: 4:1 multiplexers using one 8:1 multiplexers using two s 1:1 multiplexers using four s These wide input multiplexers are implemented in one level or logic (or ) using the dedicated F7AMUX, F7BMUX, and F8MUX multiplexers. These multiplexers allow combinations of up to four s in a slice. Virtex- FPGA User Guide 19

24 Chapter : Configurable Logic Blocks (CLBs) esigning Large Multiplexers 4:1 Multiplexer Each can be configured into a 4:1 MUX. The 4:1 MUX can be implemented with a flipflop in the same slice. Up to four 4:1 MUXes can be implemented in a slice, as shown in Figure -21. X-Ref Target - Figure -21 SLI () 4:1 MUX SEL [1:0], ATA [3:0] Input ([:1]) A[:1] Q (Q) Registered (C) 4:1 MUX SEL C [1:0], ATA C [3:0] Input (C[:1]) A[:1] Q (CQ) Registered (B) 4:1 MUX SEL B [1:0], ATA B [3:0] Input (B[:1]) A[:1] Q (BQ) Registered (A) 4:1 MUX SEL A [1:0], ATA A [3:0] Input (A[:1]) A[:1] Q (AQ) Registered () UG190 21_000 Figure -21: Four 4:1 Multiplexers in a Slice 19 Virtex- FPGA User Guide

25 CLB Overview 8:1 Multiplexer Each slice has an F7AMUX and an F7BMUX. These two muxes combine the output of two s to form a combinatorial function up to 13 inputs (or an 8:1 MUX). Up to two 8:1 MUXes can be implemented in a slice, as shown in Figure -22. X-Ref Target - Figure -22 SLI SEL [1:0], ATA [3:0] Input (1) ([:1]) A[:1] F7BMUX (CMUX) 8:1 MUX (1) SEL C [1:0], ATA C [3:0] Input (1) (C[:1]) A[:1] (CQ) Q Registered SELF7(1) (CX) () SEL B [1:0], ATA B [3:0] Input (2) (B[:1]) A[:1] F7AMUX (AMUX) 8:1 MUX (2) SEL A [1:0], ATA A [3:0] Input (2) (A[:1]) A[:1] (AQ) Q Registered SELF7(2) (AX) UG190 22_09080 Figure -22: Two 8:1 Multiplexers in a Slice Virtex- FPGA User Guide 197

26 Chapter : Configurable Logic Blocks (CLBs) 1:1 Multiplexer Each slice has an F8MUX. F8MUX combines the outputs of F7AMUX and F7BMUX to form a combinatorial function up to 27 inputs (or a 1:1 MUX). Only one 1:1 MUX can be implemented in a slice, as shown in Figure -23. X-Ref Target - Figure -23 SLI SEL [1:0], ATA [3:0] Input ([:1]) A[:1] F7BMUX SEL C [1:0], ATA C [3:0] Input (C[:1]) A[:1] F8MUX SELF7 (CX) (BMUX) (B) Q 1:1 MUX Registered SEL B [1:0], ATA B [3:0] Input (B[:1]) A[:1] F7AMUX SEL A [1:0], ATA A [3:0] Input (A[:1]) A[:1] SELF7 SELF8 (AX) (BX) () UG190 23_000 Figure -23: 1:1 Multiplexer in a Slice It is possible to create multiplexers wider than 1:1 across more than one SLIM. However, there are no direct connections between slices to form these wide multiplexers. Fast Lookahead Carry Logic In addition to function generators, dedicated carry logic is provided to perform fast arithmetic addition and subtraction in a slice. A Virtex- FPGA CLB has two separate carry chains, as shown in Figure -1. The carry chains are cascadable to form wider add/subtract logic, as shown in Figure -2. The carry chain in the Virtex- device is running upward and has a height of four bits per slice. For each bit, there is a carry multiplexer (MUXCY) and a dedicated XOR gate for adding/subtracting the operands with a selected carry bits. The dedicated carry path and Virtex- FPGA User Guide

27 CLB Overview carry multiplexer (MUXCY) can also be used to cascade function generators for implementing wide logic functions. Figure -24 illustrates the carry chain with associated logic elements in a slice. X-Ref Target - Figure -24 COUT (To Next Slice) Carry Chain Block (CARRY4) From S3 MUXCY CO3 MUX/Q* O From X I3 O3 Q MUX Q From C S2 MUXCY CO2 CMUX/CQ* O From C CX I2 O2 Q CMUX CQ From B S1 MUXCY CO1 BMUX/BQ* O From B BX I1 O1 Q BMUX BQ From A S0 MUXCY CO0 AMUX/AQ* O From A AX I0 O0 Q AMUX AQ CYINIT CIN 0 1 CIN (From Previous Slice) * Can be used if unregistered/registered outputs are free. UG190 24_000 Figure -24: Fast Carry Logic Path and Associated Elements The carry chains carry lookahead logic along with the function generators. There are ten independent inputs (S inputs S0 to S3, I inputs I1 to I4, CYINIT and CIN) and eight independent outputs (O outputs O0 to O3, and CO outputs CO0 to CO3). The S inputs are used for the propagate signals of the carry lookahead logic. The propagate signals are sourced from the output of a function generator. The I inputs are used for the generate signals of the carry lookahead logic. The generate signals are sourced from either the O output of a function generator or the BYPASS input (AX, BX, CX, or X) of a slice. The former input is used to create a multiplier, while the latter is used Virtex- FPGA User Guide 199

28 Chapter : Configurable Logic Blocks (CLBs) CLB / Slice Timing Models to create an adder/accumulator. CYINIT is the CIN of the first bit in a carry chain. The CYINIT value can be 0 (for add), 1 (for subtract), or AX input (for the dynamic first carry bit). The CIN input is used to cascade slices to form a longer carry chain. The O outputs contain the sum of the addition/subtraction. The CO outputs compute the carry out for each bit. CO3 is connected to COUT output of a slice to form a longer carry chain by cascading multiple slices. The propagation delay for an adder increases linearly with the number of bits in the operand, as more carry chains are cascaded. The carry chain can be implemented with a storage element or a flip-flop in the same slice. ue to the large size and complexity of Virtex- FPGAs, understanding the timing associated with the various paths and functional elements is a difficult and important task. Although it is not necessary to understand the various timing parameters to implement most designs using Xilinx software, a thorough timing model can assist advanced users in analyzing critical paths or planning speed-sensitive designs. Three timing model sections are described: Functional element diagram basic architectural schematic illustrating pins and connections Timing parameters definitions of Virtex- FPGA ata Sheet timing parameters Timing iagram - illustrates functional element timing parameters relative to each other Use the models in this chapter in conjunction with both the Xilinx Timing Analyzer software (TR) and the section on switching characteristics in the Virtex- FPGA ata Sheet. All pin names, parameter names, and paths are consistent with the post-route timing and pre-route static timing reports. Most of the timing parameters found in the section on switching characteristics are described in this chapter. All timing parameters reported in the Virtex- FPGA ata Sheet are associated with slices and CLBs. The following sections correspond to specific switching characteristics sections in the Virtex- FPGA ata Sheet: General Slice Timing Model and Parameters (CLB Switching Characteristics) Slice istributed RAM Timing Model and Parameters (Available in SLIM only) (CLB istributed RAM Switching Characteristics) Slice SRL Timing Model and Parameters (Available in SLIM only) (CLB SRL Switching Characteristics) Slice Carry-Chain Timing Model and Parameters (CLB Application Switching Characteristics) Virtex- FPGA User Guide

29 CLB / Slice Timing Models General Slice Timing Model and Parameters A simplified Virtex- FPGA slice is shown in Figure -2. Some elements of the slice are omitted for clarity. Only the elements relevant to the timing paths described in this section are shown. X-Ref Target - Figure -2 Inputs O FE/LAT MUX X Q Q SR REV F7BMUX C Inputs C O CMUX FE/LAT CX F8MUX Q CQ SR REV B Inputs B O BMUX FE/LAT BX Q BQ SR REV F7AMUX A Inputs A O AMUX FE/LAT AX Q AQ SR REV SR REV (X) UG190 2_000 Figure -2: Simplified Virtex- FPGA Slice Virtex- FPGA User Guide 201

30 Chapter : Configurable Logic Blocks (CLBs) Table -7: Timing Parameters Table -7 shows the general slice timing parameters for a majority of the paths in Figure -2. General Slice Timing Parameters Parameter Function escription Combinatorial elays T (1) ILO A/B/C/ inputs to A/B/C/ outputs Propagation delay from the A/B/C/ inputs of the slice, through the look-up tables (s), to the A/B/C/ outputs of the slice (six-input function). T ILO_2 T ILO_3 Sequential elays T CKO T CKLO A/B/C/ inputs to AMUX/CMUX outputs A/B/C/ inputs to BMUX output FF Clock () to AQ/BQ/CQ/Q outputs Latch Clock () to AQ/BQ/CQ/Q outputs Propagation delay from the A/B/C/ inputs of the slice, through the s and F7AMUX/F7BMUX to the AMUX/CMUX outputs (seven-input function). Propagation delay from the A/B/C/ inputs of the slice, through the s, F7AMUX/F7BMUX, and F8MUX to the BMUX output (eight-input function). Time after the clock that data is stable at the AQ/BQ/CQ/Q outputs of the slice sequential elements (configured as a flip-flop). Time after the clock that data is stable at the XQ/YQ outputs of the slice sequential elements (configured as a latch). Setup and Hold Times for Slice Sequential Elements (2) T ICK /T CKI AX/BX/CX/X inputs Time before/after the that data from the AX/BX/CX/X inputs of the slice must be stable at the input of the slice sequential elements (configured as a flip-flop). T CK /T CK input Time before/after the that the input of the slice must be stable at the input of the slice sequential elements (configured as a flip-flop). T SRCK /T CKSR SR/BY input Time before/after the that the SR (Set/Reset) and the BY (Rev) inputs of the slice must be stable at the SR/Rev inputs of the slice sequential elements (configured as a flip-flop). Set/Reset T RPW Minimum Pulse Width for the SR (Set/Reset) and BY (Rev) pins. T RQ Propagation delay for an asynchronous Set/Reset of the slice sequential elements. From the SR/BY inputs to the AQ/BQ/CQ/Q outputs. F TOG Toggle Frequency Maximum frequency that a CLB flip-flop can be clocked: 1 / (T CH + T CL ). Notes: 1. This parameter includes a configured as two five-input functions. 2. T XXCK = Setup Time (before clock edge), and T CKXX = Hold Time (after clock edge) Virtex- FPGA User Guide

31 CLB / Slice Timing Models Timing Characteristics Figure -2 illustrates the general timing characteristics of a Virtex- FPGA slice. X-Ref Target - Figure AX/BX/CX/X (ATA) SR (RESET) AQ/BQ/CQ/Q (OUT) T O T ICK T CKO T SRCK T CKO ug190 2_000 Figure -2: General Slice Timing Characteristics At time T O before clock event (1), the clock-enable signal becomes valid-high at the input of the slice register. At time T ICK before clock event (1), data from either AX, BX, CX, or X inputs become valid-high at the input of the slice register and is reflected on either the AQ, BQ, CQ, or Q pin at time T CKO after clock event (1). At time T SRCK before clock event (3), the SR signal (configured as synchronous reset) becomes valid-high, resetting the slice register. This is reflected on the AQ, BQ, CQ, or Q pin at time T CKO after clock event (3). Virtex- FPGA User Guide 203

32 Chapter : Configurable Logic Blocks (CLBs) Slice istributed RAM Timing Model and Parameters (Available in SLIM only) Figure -27 illustrates the details of distributed RAM implemented in a Virtex- FPGA slice. Some elements of the slice are omitted for clarity. Only the elements relevant to the timing paths described in this section are shown. X-Ref Target - Figure -27 RAM X I input I1 I2 A[:0] WA[:0] O MUX RAM CX CI C input I1 I2 A[:0] WA[:0] O C CMUX RAM BX BI B input I1 I2 A[:0] WA[:0] O B BMUX RAM AX AI A input I1 I2 A[:0] WA[:0] O A AMUX UG190 27_000 Figure -27: Simplified Virtex- FPGA SLIM istributed RAM Virtex- FPGA User Guide

33 CLB / Slice Timing Models istributed RAM Timing Parameters Table -8 shows the timing parameters for the distributed RAM in SLIM for a majority of the paths in Figure -27. Table -8: istributed RAM Timing Parameters Parameter Function escription Sequential elays for a Slice Configured as RAM (istributed RAM) T (1) SHCKO to A/B/C/ outputs Time after the of a write operation that the data written to the distributed RAM is stable on the A/B/C/ output of the slice. Setup and Hold Times for a Slice Configured as RAM (istributed RAM) (2) T S /T H (3) AX/BX/CX/X configured as data input (I1) Time before/after the clock that data must be stable at the AX/BX/CX/X input of the slice. T ACK /T CKA A/B/C/ address inputs Time before/after the clock that address signals must be stable at the A/B/C/ inputs of the slice (configured as RAM). T WS /T WH input Time before/after the clock that the write enable signal must be stable at the input of the slice (configured as RAM). Clock T WPH T WPL T WC Minimum Pulse Width, High Minimum Pulse Width, Low Minimum clock period to meet address write cycle time. Notes: 1. This parameters includes a configured as a two-bit distributed RAM. 2. T XXCK = Setup Time (before clock edge), and T CKXX = Hold Time (after clock edge). 3. Parameter includes AI/BI/CI/I configured as a data input (I2). Virtex- FPGA User Guide 20

34 Chapter : Configurable Logic Blocks (CLBs) istributed RAM Timing Characteristics The timing characteristics of a 1-bit distributed RAM implemented in a Virtex- FPGA slice ( configured as RAM) are shown in Figure -28. X-Ref Target - Figure T WC T WPH T WPL A/B/C/ (AR) T AS 2 F 3 4 E AX/BX/CX/X (I) 1 T S X X T WS TILO T ILO ATA_OUT A/B/C/ T SHCKO 1 MEM(F) WRITE REA WRITE WRITE WRITE REA MEM(E) UG190 28_000 Figure -28: Slice istributed RAM Timing Characteristics Clock Event 1: Write Operation uring a Write operation, the contents of the memory at the address on the AR inputs are changed. The data written to this memory location is reflected on the A/B/C/ outputs synchronously. At time T WS before clock event 1, the write-enable signal () becomes valid-high, enabling the RAM for a Write operation. At time T AS before clock event 1, the address (2) becomes valid at the A/B/C/ inputs of the RAM. At time T S before clock event 1, the ATA becomes valid (1) at the I input of the RAM and is reflected on the A/B/C/ output at time T SHCKO after clock event 1. This is also applicable to the AMUX, BMUX, CMUX, MUX, and COUT outputs at time T SHCKO and T WOSCO after clock event 1. Clock Event 2: Read Operation All Read operations are asynchronous in distributed RAM. As long as is Low, the address bus can be asserted at any time. The contents of the RAM on the address bus are reflected on the A/B/C/ outputs after a delay of length T ILO (propagation delay through a ). The address (F) is asserted after clock event 2, and the contents of the RAM at address (F) are reflected at the output after a delay of length T ILO Virtex- FPGA User Guide

35 CLB / Slice Timing Models Slice SRL Timing Model and Parameters (Available in SLIM only) Figure -29 illustrates shift register implementation in a Virtex- FPGA slice. Some elements of the slice have been omitted for clarity. Only the elements relevant to the timing paths described in this section are shown. X-Ref Target - Figure -29 SRL X I1 address A MC31 W SRL CX I1 C C address A MC31 SRL BX I1 B B address A MC31 SRL AX A address I1 A MC31 A MUX UG190 29_000 Figure -29: Simplified Virtex- FPGA Slice SRL Virtex- FPGA User Guide 207

36 Chapter : Configurable Logic Blocks (CLBs) Slice SRL Timing Parameters Table -9 shows the SLIM SRL timing parameters for a majority of the paths in Figure -29. Table -9: Slice SRL Timing Parameters Parameter Function escription Sequential elays for a Slice Configured as an SRL T (1) REG to A/B/C/ outputs Time after the of a write operation that the data written to the SRL is stable on the A/B/C/ outputs of the slice. T (1) REG_MUX to AMUX - MUX output Time after the of a write operation that the data written to the SRL is stable on the MUX output of the slice. T REG_M31 to MUX output via MC31 output Setup and Hold Times for a Slice Configured SRL (2) Time after the of a write operation that the data written to the SRL is stable on the MUX output via MC31 output. T WS /T WH input () Time before/after the clock that the write enable signal must be stable at the input of the slice (configured as an SRL). T S /T H (3) AX/BX/CX/X configured as data input (I) Time before the clock that the data must be stable at the AX/BX/CX/X input of the slice (configured as an SRL). Notes: 1. This parameter includes a configured as a two-bit shift register. 2. T XXCK = Setup Time (before clock edge), and T CKXX = Hold Time (after clock edge). 3. Parameter includes AI/BI/CI/I configured as a data input (I2) or two bits with a common shift. Slice SRL Timing Characteristics Figure -30 illustrates the timing characteristics of a 1-bit shift register implemented in a Virtex- FPGA slice (a configured as an SRL). X-Ref Target - Figure Write Enable () Shift_In (I) Address (A/B/C/) ata Out (A/B/C/) MSB (MC31/MUX) T WS T S T REG T ILO T ILO X T REG X X X X X X X 0 ug190 30_000 Figure -30: Slice SRL Timing Characteristics Virtex- FPGA User Guide

37 CLB / Slice Timing Models Clock Event 1: Shift In uring a write (Shift In) operation, the single-bit content of the register at the address on the A/B/C/ inputs is changed, as data is shifted through the SRL. The data written to this register is reflected on the A/B/C/ outputs synchronously, if the address is unchanged during the clock event. If the A/B/C/ inputs are changed during a clock event, the value of the data at the addressable output (A/B/C/ outputs) is invalid. At time T WS before clock event 1, the write-enable signal () becomes valid-high, enabling the SRL for the Write operation that follows. At time T S before clock event 1 the data becomes valid (0) at the I input of the SRL and is reflected on the A/B/C/ output after a delay of length T REG after clock event 1. Since the address 0 is specified at clock event 1, the data on the I input is reflected at A/B/C/ output, because it is written to register 0. Clock Event 2: Shift In At time T S before clock event 2, the data becomes valid (1) at the I input of the SRL and is reflected on the A/B/C/ output after a delay of length T REG after clock event 2. Since the address 0 is still specified at clock event 2, the data on the I input is reflected at the output, because it is written to register 0. Clock Event 3: Shift In/Addressable (Asynchronous) REA All Read operations are asynchronous to the signal. If the address is changed (between clock events), the contents of the register at that address are reflected at the addressable output (A/B/C/ outputs) after a delay of length T ILO (propagation delay through a ). At time T S before clock event 3, the data becomes valid (1) at the I input of the SRL and is reflected on the A/B/C/ output T REG time after clock event 3. The address is changed (from 0 to 2). The value stored in register 2 at this time is a 0 (in this example, this was the first data shifted in), and it is reflected on the A/B/C/ output after a delay of length T ILO. Clock Event 32: MSB (Most Significant Bit) Changes At time T REG after clock event 32, the first bit shifted into the SRL becomes valid (logical 0 in this case) on the MUX output of the slice via the MC31 output of A (SRL). This is also applicable to the AMUX, BMUX, CMUX, MUX, and COUT outputs at time T REG and T WOSCO after clock event 1. Virtex- FPGA User Guide 209

38 Chapter : Configurable Logic Blocks (CLBs) Slice Carry-Chain Timing Model and Parameters Figure -24, page 199 illustrates a carry chain in a Virtex- FPGA slice. Some elements of the slice have been omitted for clarity. Only the elements relevant to the timing paths described in this section are shown. Slice Carry-Chain Timing Parameters Table -10 shows the slice carry-chain timing parameters for a majority of the paths in Figure -24, page 199. Table -10: Slice Carry-Chain Timing Parameters Parameter Function escription Sequential elays for Slice Configured as Carry Chain T AXCY /T BXCY /T CXCY /T XCY AX/BX/CX/X input to COUT output Propagation delay from the AX/BX/CX/X inputs of the slice to the COUT output of the slice. T BYP CIN input to COUT output Propagation delay from the CIN input of the slice to the COUT output of the slice. T OPCYA /T OPCYB /T OPCYC /T OPCY T CINA /T CINB /T CINC /T CIN A/B/C/ input to COUT output A/B/C/ input to AMUX/BMUX/CMUX/MU X output Propagation delay from the A/B/C/ inputs of the slice to the COUT output of the slice. Propagation delay from the A/B/C/ inputs of the slice to AMUX/BMUX/CMUX/MUX output of the slice using XOR (sum). Setup and Hold Times for a Slice Configured as a Carry Chain (1) T CINCK /T CKCIN CIN ata inputs Time before the that data from the CIN input of the slice must be stable at the input of the slice sequential elements (configured as a flip-flop). Notes: 1. T XXCK = Setup Time (before clock edge), and T CKXX = Hold Time (after clock edge). Slice Carry-Chain Timing Characteristics Figure -31 illustrates the timing characteristics of a slice carry chain implemented in a Virtex- FPGA slice. X-Ref Target - Figure C IN (ATA) SR (RESET) AQ/BQ/CQ/Q (OUT) T CINCK T CKO T SRCK T CKO ug190 31_000 Figure -31: Slice Carry-Chain Timing Characteristics Virtex- FPGA User Guide

39 CLB Primitives CLB Primitives Table -11: At time T CINCK before clock event 1, data from CIN input becomes valid-high at the input of the slice register. This is reflected on any of the AQ/BQ/CQ/Q pins at time T CKO after clock event 1. At time T SRCK before clock event 3, the SR signal (configured as synchronous reset) becomes valid-high, resetting the slice register. This is reflected on any of the AQ/BQ/CQ/Q pins at time T CKO after clock event 3. More information on the CLB primitives are available in the software libraries guide. istributed RAM Primitives Seven primitives are available; from 32 x 2 bits to 2 x 1 bit. Three primitives are singleport RAM, two primitives are dual-port RAM, and two primitives are quad-port RAM, as shown in Table -11. Single-Port, ual-port, and Quad-Port istributed RAM Primitive RAM Size Type Address Inputs RAM32X1S 32-bit Single-port A[4:0] (read/write) RAM32X1 32-bit ual-port A[4:0] (read/write) PRA[4:0] (read) RAM32M 32-bit Quad-port ARA[4:0] (read) ARB[4:0] (read) ARC[4:0] (read) AR[4:0] (read/write) RAM4X1S 4-bit Single-port A[:0] (read/write) RAM4X1 4-bit ual-port A[:0] (read/write) PRA[:0] (read) RAM4M 4-bit Quad-port ARA[:0] (read) ARB[:0] (read) ARC[:0] (read) AR[:0] (read/write) RAM128X1S 128-bit Single-port A[:0] (read/write) RAM128X1 128-bit ual-port A[:0], (read/write) PRA[:0] (read) RAM2X1S 2-bit Single-port A[7:0] (read/write) The input and output data are 1-bit wide (with the exception of the 32-bit RAM). Figure -32 shows generic single-port, dual-port, and quad-port distributed RAM primitives. The A, AR, and PRA signals are address buses. Virtex- FPGA User Guide 211

40 Chapter : Configurable Logic Blocks (CLBs) X-Ref Target - Figure -32 RAM#X1S RAM#X1 RAM#M O SPO I[A:][#:0] O[#:0] W W W A[#:0] A[#:0] R/W Port AR[#:0] R/W Port PRA[#:0] Read Port PO ARC[#:0] Read Port OC[#:0] ARB[#:0] Read Port OB[#:0] ARA[#:0] Read Port OA[#:0] UG190 32_ Figure -32: Single-Port, ual-port, and Quad-Port istributed RAM Primitives Instantiating several distributed RAM primitives can be used to implement wide memory blocks. Port Signals Each distributed RAM port operates independently of the other while reading the same set of memory cells. Clock W The clock is used for the synchronous write. The data and the address input pins have setup times referenced to the W pin. Enable / The enable pin affects the write functionality of the port. An active write enable prevents any writing to memory cells. An active write enable causes the clock edge to write the data input signal to the memory location pointed to by the address inputs. Address A[#:0], PRA[#:0], and ARA[#:0] AR[#:0] The address inputs A[#:0] (for single-port and dual-port), PRA[#:0] (for dual-port), and ARA[#:0] AR[#:0] (for quad-port) select the memory cells for read or write. The width of the port determines the required address inputs. Some of the address inputs are not buses in VHL or Verilog instantiations. Table -11 summarizes the function of each address pins. ata In, I[#:0] The data input (for single-port and dual-port) and I[#:0] (for quad-port) provide the new data value to be written into the RAM. ata Out O, SPO, PO and OA[#:0] O[#:0] The data out O (single-port or SPO), PO (dual-port), and OA[#:0] O[#:0] (quadport) reflects the contents of the memory cells referenced by the address inputs. Following an active write clock edge, the data out (O, SPO, or O[#:0]) reflects the newly written data Virtex- FPGA User Guide

41 CLB Primitives Inverting Clock Pins The clock pin () has an individual inversion option. The clock signal can be active at the negative edge of the clock or the positive edge for the clock without requiring other logic resources. The default is at the positive clock edge Global Set/Reset GSR The global set/reset (GSR) signal does not affect distributed RAM modules. Shift Registers (SRLs) Primitive One primitive is available for the 32-bit shift register (SRLC32E). Figure -33 shows the 32-bit shift register primitive. X-Ref Target - Figure -33 SRLC32E A[4:0] Q Q31 UG190 33_000 Figure -33: 32-bit Shift Register Instantiating several 32-bit shift register with dedicated multiplexers (F7AMUX, F7BMUX, and F8MUX) allows a cascadable shift register chain of up to 128-bit in a slice. Figure -18 through Figure -20 in the Shift Registers (Available in SLIM only) section of this document illustrate the various implementation of cascadable shift registers greater than 32 bits. Port Signals Clock Either the rising edge or the falling edge of the clock is used for the synchronous shift operation. The data and clock enable input pins have setup times referenced to the chosen edge of. ata In The data input provides new data (one bit) to be shifted into the shift register. Clock Enable - The clock enable pin affects shift functionality. An inactive clock enable pin does not shift data into the shift register and does not write new data. Activating the clock enable allows the data in () to be written to the first location and all data to be shifted by one location. When available, new data appears on output pins (Q) and the cascadable output pin (Q31). Address A[4:0] The address input selects the bit (range 0 to 31) to be read. The nth bit is available on the output pin (Q). Address inputs have no effect on the cascadable output pin (Q31). It is always the last bit of the shift register (bit 31). Virtex- FPGA User Guide 213