GS1881, GS4881, GS4981 Monolithic Video Sync Separators

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1 GS11, GS1, GS91 Monolithic Video Sync Separators DATA SHEET FEATURES noise tolerant odd/even flag, back porch and horizontal sync pulse fast recovery from impulse noise excellent temperature stability.5 V to Vpp input signal amplitude with 5 V supply wellcontrolled clamp discharge current and slicing level programmable horizontal scan rate (up to 13 khz) composite, vertical, back porch, odd/even (GS11, GS1), horizontal (GS91) outputs predictable vertical output pulse width with default trigger for nonstandard video signals 5 V to 1 V supply voltage range pin compatible with LM11 sync separator SELECTION CHART APPLICATION Direct LM11 Replacement with Improved Performance New Applications Substitution for LM11 New Applications Requiring Horizontal Sync Output CHOOSE DEVICE: GS11 GS1 GS91 DESCRIPTION The GS11, GS1 and GS91 are general purpose sync separators for use in a wide variety of video applications. The devices extract the timing information from composite video signals with scan rates from 15 to 13 khz. The GS11 is a dropin replacement for the industry standard LM11 with much improved performance. The device generates composite sync, vertical sync, back porch and odd/even field signals. The GS1 is identical to the GS11 but features a noise immune back porch pulse which maintains a constant H rate during the vertical interval. The GS91 is identical to the GS1, except that it provides horizontal sync in place of the odd/even output. All three devices feature a selfadjusting windowing circuit for noise immunity, which synchronizes to H rate. This windowing circuit determines the odd or even field in the GS11 and GS1, gates the back porch pulse in the GS1 and GS91, and generates the horizontal sync output in the GS91. The devices feature an improved input stage which ensures that the input signal is sliced at a predictable point due to wellcontrolled input clamp discharge current and sync slicing level. A missing pulse detector enables the devices to recover quickly from impulse noise disturbances by temporarily increasing the clamp discharge current by roughly ten times. The input stage will operate with signals from.5 to volts peak to peak with a 5 volt supply. The GS11, GS1 and GS91 also feature a predictable vertical output pulse width with a default trigger for nonstandard video signals. All three are available in commercial and industrial temperature ranges and are packaged in both DIP and SOIC. PIN CONNECTIONS GS11, GS1 GS91 SYNC OUT 1 V cc SYNC OUT 1 V cc VIDEO IN VERTICAL SYNC OUT 3 7 ODD/EVEN VIDEO IN VERTICAL SYNC OUT 3 7 HORIZONTAL GROUND 5 GROUND 5 PIN DIP PIN SOIC PIN DIP PIN SOIC Patent No. 5,3,559 Revision Date: October 1995 Document No GENNUM CORPORATION P.O. Box 9, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (95) 399 fax: (95) 355 Japan Branch: A3 Miyamae Village, 1 Miyamae, Suginamiku, Tokyo 1, Japan tel. (3) 373 fax (3) 3739

2 GS11 ELECTRICAL CHARACTERISTICS (V CC = 5 V, = kω, T A = 5 C, unless otherwise specified) PARAMETER CONDITIONS MIN TYP MAX UNITS Supply Voltage V Supply Current Outputs at Logic 1 V CC = 5 V..5 ma V CC = 1 V ma Video Input (Pin ) (a) Signal Level V CC = 5 V.5 Vpp (b) Clamp Current Charge µa Discharge normal µa Nosync flag raised µa (c) Delay to raising of Nosync flag Video input held high µs (d) Sync Tip Clamp Voltage 1.55 V Sync Slice Level Relative to sync tip clamp voltage 7 77 mv Pin Reference Voltage (Pin ) See Note V Composite Sync Out (Pin 1) See Note ns Delay from Video C L = 15p Back Porch Pulse Out (Pin 5) C L = 15p (a) Delay from Rising Edge of Sync 5 5 ns (b) Pulse Width µs Vertical Sync Out (Pin 3) (a) Pulse Width Serrations during vertical interval µs (b) Default Starting Time No serrations during the vertical interval 5 µs Horizontal Scan Rate Modified khz Logic Outputs (a) V OH I OH = µa V CC = 5 V.. V V CC = 1 V V I OH = 1. ma V CC = 5 V. 3. V V CC = 1 V V (b) V OL I OL = 1. ma.3. V Note 1: When placing the resistor and the.1µf decoupling capacitor careful attention should be made to ensure that they are as close as possible to pin. Care should also be taken to avoid parasitic capacitive coupling from any output pin (pins 1, 3, 5 and 7) to pin. Note : Measured from slicing point of input falling edge to 5% point of composite sync falling edge. ORDERING INFORMATION Part Number Package Type Temperature Range GS11 CDA PDIP to 7 C GS11 CKA SOIC to 7 C GS11 CTA TAPE to 7 C GS11 IDA PDIP 5 to 5 C GS11 IKA SOIC 5 to 5 C GS11 ITA TAPE 5 to 5 C CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATICFREE WORKSTATION 5 3 3

3 GS1 ELECTRICAL CHARACTERISTICS (V CC = 5 V, = kω, T A = 5 C, unless otherwise specified) PARAMETER CONDITIONS MIN TYP MAX UNITS Supply Voltage V Supply Current Outputs at Logic 1 V CC = 5 V..5 ma V CC = 1 V ma Video Input (Pin ) (a) Signal Level V CC = 5 V.5 Vpp (b) Clamp Current Charge µa Discharge normal µa Nosync flag raised µa (c) Delay to raising of Nosync flag Video input held high µs (d) Sync Tip Clamp Voltage 1.55 V Sync Slice Level Relative to sync tip clamp voltage 7 77 mv Pin Reference Voltage (Pin ) See Note V Composite Sync Out (Pin 1) See Note ns Delay from Video C L = 15p Back Porch Pulse Out (Pin 5) C L = 15p (a) Delay from Rising Edge of Sync 5 5 ns (b) Pulse Width µs (c) Occurence Rate H H H Vertical Sync Out (Pin 3) (a) Pulse Width Serrations during vertical interval µs (b) Default Starting Time No serrations during the vertical interval 5 µs Horizontal Scan Rate Modified khz Logic Outputs (a) V OH I OH = µa V CC = 5 V.. V V CC = 1 V V I OH = 1. ma V CC = 5 V. 3. V V CC = 1 V V (b) V OL I OL = 1. ma.3. V Note 1: When placing the resistor and the.1µf decoupling capacitor careful attention should be made to ensure that they are as close as possible to pin. Care should also be taken to avoid parasitic capacitive coupling from any output pin (pins 1, 3, 5 and 7) to pin. Note : Measured from slicing point of input falling edge to 5% point of composite sync falling edge. ORDERING INFORMATION Part Number Package Type Temperature Range GS1 CDA PDIP to 7 C GS1 CKA SOIC to 7 C GS1 CTA TAPE to 7 C GS1 IDA PDIP 5 to 5 C GS1 IKA SOIC 5 to 5 C GS1 ITA TAPE 5 to 5 C

4 GS91 ELECTRICAL CHARACTERISTICS (V CC = 5 V, = kω, T A = 5 C, unless otherwise specified) PARAMETER CONDITIONS MIN TYP MAX UNITS Supply Voltage V Supply Current Outputs at Logic 1 V CC = 5 V..5 ma V CC = 1 V ma Video Input (Pin ) (a) Signal Level V CC = 5 V.5 Vpp (b) Clamp Current Charge µa Discharge normal µa Nosync flag raised µa (c) Delay to raising of Nosync flag Video input held high µs (d) Sync Tip Clamp Voltage 1.55 V Sync Slice Level Relative to sync tip clamp voltage 7 77 mv Pin Reference Voltage (Pin ) See Note V Composite Sync Out (Pin 1) See Note ns Delay from Video C L = 15p Back Porch Pulse Out (Pin 5) C L = 15p (a) Delay from Rising Edge of Sync 5 5 ns (b) Pulse Width µs (c) Occurence Rate H H H Vertical Sync Out (Pin 3) (a) Pulse Width Serrations during vertical interval µs (b) Default Starting Time No serrations during the vertical interval 5 µs Horizontal Sync Out (Pin 7) C L = 15p (a) Delay from Video ns (b) Pulse Width µs Horizontal Scan Rate Modified khz Logic Outputs (a) V OH I OH = µa V CC = 5 V.. V V CC = 1 V V I OH = 1. ma V CC = 5 V. 3. V Note 3 V CC = 1 V V (b) V OL I OL = 1. ma.3. V Note 1: When placing the resistor and the.1µf decoupling capacitor careful attention should be made to ensure that they are as close as possible to pin. Care should also be taken to avoid parasitic capacitive coupling from any output pin (pins 1, 3, 5 and 7) to pin. Note : Measured from slicing point of input falling edge to 5% point of composite sync falling edge. Note 3: Applies only to composite sync, vertical sync, and back porch outputs. Horizontal sync has a passive 1 kω pullup to V CC. ORDERING INFORMATION Part Number Package Type Temperature Range GS91 CDA PDIP to 7 C GS91 CKA SOIC to 7 C GS91 CTA TAPE to 7 C GS91 IDA PDIP 5 to 5 C GS91 IKA SOIC 5 to 5 C GS91 ITA TAPE 5 to 5 C 5 3 3

5 TYPICAL PERFORMANCE CHARACTERISTICS (V S = 5V, T A = 5 C unless otherwise shown) 7 7 (kω) VERTICAL DEFAULT TIME (µs) SCAN RATE (khz) (kω) Fig. 1 vs Scan Rate Fig. Vertical Sync Default Starting Time vs 7 3 DELAY (ns) WIDTH (ns) (kω) (kω) Fig. 3 Back Porch Delay vs Fig. Back Porch Width vs 11 HORIZONTAL WIDTH (µs) NOSYNC DELAY TIME (µs) (kω) (kω) Fig. 5 Horizontal Width vs Fig. Nosync Delay Time vs

6 TEMPERATURE CHARACTERISTICS (V S = 5V, = kω unless otherwise shown) Commercial Temperature Range ( 7 C) 1 5 SYNC DELAY VARIATION (ns) CLAMPING CURRENT (µa) TEMPERATURE ( C) Fig. 7 Composite Sync Delay Variation vs Temperature TEMPERATURE ( C) Fig. Clamping Current vs Temperature 3 15 DELAY VARIATION (ns) WIDTH VARIATION (ns) TEMPERATURE ( C) TEMPERATURE ( C) Fig. 9 Back Porch Delay Variation vs Temperature Fig. 1 Back Porch Width Variation vs Temperature 5 HORIZONTAL DELAY VARIATION (ns) HORIZONTAL WIDTH VARIATION (ns) TEMPERATURE ( C) Fig. 11 Horizontal Delay Variation vs Temperature TEMPERATURE ( C) Fig. 1 Horizontal Width Variation vs Temperature

7 CIRCUIT DESPCRIPTION The block diagrams for the GS11, GS1 and GS91, are shown in Figures 17 through 19, with timing diagrams for the devices shown in Figure. When stimulated by a composite input signal, the GS11 and GS1 sync separators output composite sync, vertical sync, back porch, and odd/even field information. The GS91 substitutes the odd/even output of the GS1 with a horizontal output. An external resistor on pin is used to define internal currents allowing the devices to accommodate horizontal scan rates from 15 khz to 13 khz. VIDEO INPUT (pin ) and SYNC (pin 1) Composite video is AC coupled via an external coupling capacitor to pin. The device clamps the sync tip of the input video to 1.5 V ( V clamp ) and then slices at 77 mv above the clamp voltage ( V slice ). The resultant signal, provided at pin 1, is a reproduction of the input signal with the active video portion removed. As V clamp and V slice are supply and input signal independent, for.5 V pp signals (sync height of 13 mv) slicing will occur at just above the 5% point and for V pp signals (sync height of 57 mv) slicing will occur at approximately 13% of sync height. The video signal path and composite sync slicing circuitry have been optimized and compensated to achieve a low propagation delay that is stable over temperature. The typical delay is ns with less than 3 ns drift over the commercial temperature range. (pin 5) In an NTSC composite video signal, horizontal sync pulses are followed by the back porch interval. The device generates a negative going pulse on pin 5 during this time. It is delayed typically 5 ns from the rising edge of sync and has a typical width of.5 µs. Both of these times are set by the external resistor. During the preequalizing, vertical sync, and postequalizing periods, composite sync doubles in frequency. The GS1 and GS91 maintain the back porch output at the horizontal rate due to Back Porch Enable (BPEN), generated by the internal windowing circuit, which forces back porch to be asserted at the horizontal rate. This gating circuit is also the reason for the excellent impulse noise immunity of the back porch output as shown in Figure 1. Video Input Back Porch Output GS1 GS91 Impulse Noise Fig. 1 Back Porch Noise Immunity The typical input clamp discharge current is 11 µa. This current is optimal under normal operating circumstances but needs to be increased when the clamp is trying to recover from negative going impulse noise. The device improves the recovery time by raising a NOSYNC flag when there has not been a sync pulse for approximately 1 1 / horizontal lines. When this flag is raised the discharge current is increased by 5 µa so that the recovery time is sped up by nearly 1 times. Figure 13 shows a comparison between the recovery times with and without the increased discharge current. VIDEO INPUT IMPULSE NOISE SYNC RECOVERY TIME without INCREASED DISCHARGE CURRENT (LM11) RECOVERY TIME T1 SYNC RECOVERY TIME with INCREASED DISCHARGE CURRENT (GS11, GS1, GS91) RECOVERY TIME T1 / 1 Fig. 13 Impulse Noise: Recovery Time Comparison The GS11 does not gate the Back Porch which allows for total pin compatibility with the LM11. VERTICAL SYNC (pin 3) The vertical sync interval is detected by integrating the composite sync pulses. The first broad vertical sync pulse causes an internal capacitor to charge past a fixed threshold and raises an internal vertical flag. Once the vertical flag is raised, the positive edge of the next serration clocks out the vertical output. When the vertical sync interval ends, the first post equalizing pulse is unable to charge the capacitor sufficiently, causing the internal vertical flag to go high. The rising edge of the second postequalizing pulse then clocks out the high flag to end the vertical sync pulse. The vertical output is clocked in and out and therefore is a fixed width of µs (3H.7 µs.3 µs). In the case of a nonstandard vertical interval that has no serrations, a second internal capacitor is charged and clocks the vertical pulse out after typically 5 µs. In this case the end of the vertical pulse will still be the rising edge of the second postequalizing pulse. As the vertical detector is designed as a true integrator, it provides improved noise immunity

8 ODD/EVEN FIELD (pin 7 GS11, GS1) NTSC PAL and SECAM composite video standards are interlaced video schemes and therefore have odd and even fields. For odd fields the first broad vertical sync pulse is coincident with the start of horizontal, while for even fields the first broad vertical sync pulse starts in the middle of a horizontal line. Therefore by comparing the vertical sync with an internally generated horizontal sync the odd/even field information is determined. This output is clocked out by the falling edge of vertical sync. The odd/even output is low during even fields and high during odd fields. This method of detecting odd and even fields is very noise tolerant. Noise during the preequalizing pulses does not affect the output since the field decision is made at the beginning of the vertical interval. This noise immunity is displayed in Figure 15 in which an extra preequalizing pulse has been added to the video input with no negative effect on the odd/even field information. HORIZONTAL (pin 7 GS91) As mentioned above, the odd/even field output of the GS11 and GS1 is generated by comparing vertical sync with an internal horizontal sync signal. This horizontal sync signal is a true horizontal signal (i.e. maintained during the vertical interval) and is outputted on pin 7 for the GS91. A delay of 19 ns from the video input and a width of.5 µs are typically characteristics for this signal. The windowing circuit which generates horizontal provides excellent impulse noise immunity as shown in Figure 1. This output buffer is an open collector stage with an internal 1 kω pull up resistor. Video Input Impulse Noise Video Input Horizontal Output Impulse Noise Fig. 1 Horizontal Output Odd/Even Output Even Odd Fig. 15 Odd/Even Output 5 3 3

9 VIDEO INPUT (Pin ) V SLICE C SYNC HORIZONTAL SYNC (Pin 1) V CLAMP WINDOWING CIRCUIT D G D CLK ODD / EVEN (Pin 7) 11µ 5µ NOSYNC V CC (Pin ) VOLTAGE REGULATOR VERTICAL DETECTOR D CLK VERTICAL SYNC (PIN 3) R_SET (Pin ) TIMING CURRENTS 1.V DETECTOR (Pin 5) Fig. 17 GS11 Block Diagram VIDEO INPUT (Pin ) V SLICE C SYNC HORIZONTAL SYNC (Pin 1) V CLAMP WINDOWING CIRCUIT D G D CLK ODD / EVEN (Pin 7) 11µ 5µ NOSYNC B PEN V CC (Pin ) VOLTAGE REGULATOR VERTICAL DETECTOR D CLK VERTICAL SYNC (PIN 3) R_SET (Pin ) TIMING CURRENTS 1.V DETECTOR (Pin 5) Fig. 1 GS1 Block Diagram

10 VIDEO INPUT (Pin ) V 1 C SYNC 1k SYNC (Pin 1) V WINDOWING CIRCUIT HORIZONTAL (Pin 7) 11µ 5µ NOSYNC B PEN V CC (Pin ) VOLTAGE REGULATOR VERTICAL DETECTOR D CLK VERTICAL SYNC (PIN 3) R_SET (Pin ) TIMING CURRENTS 1.V DETECTOR (Pin 5) Fig. 19 GS91 Block Diagram VIDEO INPUT SYNC GS11, GS1, GS91 GS1, GS91 GS11 HORIZONTAL GS91 VERTICAL SYNC GS11, GS1, GS91 ODD/EVEN GS11, GS1 ns.5µs VIDEO INPUT 5ns.5µs Fig. GS11, GS1, GS91 Video Sync Separator Timing Diagram

11 APPLICATION NOTES (1) Choosing the Appropriate Input Coupling Capacitor to Optimize Slicing Level and Hum Rejection The video designer can adjust the slicing level by choosing the value of the input coupling capacitor. The relationship between slicing level and input coupling capacitor is described by the following equation. V SLICE = I DIS C C T = V DROOP where: I DIS = clamp discharge current = 11 µa T = T LINE T SYNC = (3.5 µs.7 µs) C C = input coupling capacitor Figure 1 is a graphical representation of this equation and photographs 1 and show the input video waveforms for.1 µf and.1 µf input capacitors respectively. The advantage in choosing a smaller input coupling capacitor, is increased hum rejection as the following analyses illustrates. SLICING LEVEL (mv) INPUT COUPLING CAPACITOR (µf) Fig. 1 Slicing Level vs Input Coupling Capacitor CH1 CH1 CH VIDEO.1µF 75Ω k.1µ CH Test Circuit 1 Photograph 1 CH1 CH1 CH VIDEO.1µF 75Ω k.1µ CH Test Circuit Photograph

12 The interfering hum component is defined by: v HUM (t) = V P cos(πƒ HUM t) where: V P = Peak voltage of AC hum = Frequency of hum (5 Hz or Hz) ƒ HUM The maximum rate of change of this hum signal occurs at the zero crossing points and is: verifying that there is enough clamping current V t = 9. mv 9. mv = 5. mv ( ) 5. mv... i =. µ = 75 µa.7 µ which is less than 5 µa. () FIltering dv HUM dt π 3π t =, = ± V P πƒ HUM Since the horizontal scan period is much faster than the period of the interference ( 3.5 µs << 1/ƒ HUM ) a good approximation is to assume that the maximum line to line voltage change resulting from the interfering hum is: V HUM = ± V P πƒ HUM T LINE where: T LINE = 3.5 µs The total line to line voltage change ( V T ) can then be calculated by adding the hum component ( V HUM ) and the droop component (V DROOP ). This calculation results in two cases: V T Case A Case B V T = V HUM V DROOP To correct for V T in case A, the input stage must be able to charge the input capacitor V T volts in.7 µs. This is not a constraint as the typical clamping current of 5 µa can accomplish this for practical values of coupling capacitor. The only way to compensate for V T in case B is to make V DROOP > V HUM. V DROOP is increased by decreasing the input coupling capacitor value. Therefore the video designer can increase hum rejection by decreasing the value of this capacitor. The following is a numerical example: V T In order to keep the input to output delay small and temperature stable, no chrominance filtering is done within the device. External filtering may be necessary if the input signal contains large chrominance components (less than 77 mv from sync tip) or has significant amounts of high frequency noise. This filter can be a simple low pass RC network constructed by a resistance (R S ) in series with the source and a capacitor (C ƒ ) to ground. A single pole low pass filter having a corner frequency of approximately 5 khz will provide ample bandwidth for passing sync pulses with almost 1 db attenuation at 3.5 MHz. Care should be taken in choosing the value of the series resistor in the filter since the source resistance seen by the sync separator affects its performance. As the source resistance rises, the video input sync tip starts to be clipped due to the clamping current during the sync. This clamping current is relatively large due to the nonsymmetric duty cycle of video. To a good approximation the amount of sync clamp current can be calculated as follows: ( I CLAMP ) (T SYNC ) = (I DIS ) (T LINE T SYNC ) AVG I CLAMP AVG (.7 µs) = (11 µa) (3. 5 µs.7 µs)... I CLAMP = 137. µa AVG This clamp current flows in the source resistance causing a voltage drop equal to : V CLIP = ( I CLAMP ) (R S ) AVG = (137. µ) (R S ) choosing C c =. µf V DROOP = (3.5 µ.7 µ) = 9. mv. the maximum amount of Hz hum that could be rejected would be when: VIDEO INPUT R S V CLIP 75Ω I CLAMP C ƒ C C k.1µ V DROOP = V HUM = V P πƒ HUM T LINE.. V DROOP 9.mV. V P = = =1.3v PEAK HUM πƒ HUM T LINE π() (3.5 µ) Fig. Simple Chrominance Filtering

13 Photograph 3 shows the amount of sync clipping for a 5 Ω source resistor. A graph of V CLIP versus R S is shown in Figure 3, and Figure shows the corresponding capacitor value for a particular series resistor to provide a corner frequency of 5 khz. In applications where signal levels are small the amount of attenuation should be minimized. It follows from Figure 3 and Figure that in order to minimize attenuation a small series resistor and a larger capacitor to ground should be chosen. This however, increases the capacitive loading of the signal source. Another way to minimize the amount of attenuation is to control the source resistance seen by the sync separator by using a PNP emitter follower (Figure 5). A PNP emitter follower works well to drive the sync separator, and does not require much DC current because the transistor provides the current when it is needed during sync. Figure is a typical application circuit that minimizes sync tip clipping. CH1 CH1 CH VIDEO 5Ω 75Ω.1µF k.1µ CH Test Circuit 3 Photograph V CLIP (mv) 5 Cƒ (nf) SERIES RESISTOR (Ω) SERIES RESISTOR (Ω) Fig. 3 V CLIP vs Series Resistor Fig. Cƒ vs Series Resistor V CC V CC VIDEO INPUT 75Ω FILTER 5.k C C k.1µ VIDEO INPUT 75Ω 5.k 5p 5.k C C k.1µ 5V 5V Fig. 5 PNP Emitter Follower Buffer Fig. Typical NTSC Application Circuit

14 (3) Deriving Odd/Even Using the GS91 Odd/even field information can be derived using the vertical and horizontal outputs from the GS91 along with an external positive edge D flip/flop. The horizontal output is used as the D input and the vertical output as the clock, as shown in Figure 7. At the start of an odd field the vertical output ends in the middle of the horizontal line and a high will be latched. At the start of an even field, the vertical output ends near the beginning of the horizontal line and since the horizontal output is low, a low will be latched. This timing sequence is shown in Figure. SYNC VIDEO INPUT VERTICAL SYNC.1µF GS kω.1µf V 5 1V CC HORIZONTAL D FLIP/FLOP D CLK V ODD/EVEN Fig. 7 Derivation of Odd/Even with GS91 START OF ODD FIELD VIDEO INPUT HORIZONTAL GS91 VERTICAL SYNC GS91 ODD/EVEN START OF EVEN FIELD VIDEO INPUT HORIZONTAL GS91 VERTICAL SYNC GS91 ODD/EVEN Fig. Timing Diagram DOCUMENT IDENTIFICATION PRODUCT PROPOSAL This data has been compiled for market investigation purposes only, and does not constitute an offer for sale. ADVANCE INFORMATION NOTE This product is in development phase and specifications are subject to change without notice. Gennum reserves the right to remove the product at any time. Listing the product does not constitute an offer for sale. REVISION NOTES The only change from 53 to 533 is that the document has been upgraded to a full DATA SHEET. It is no longer Preliminary. PRELIMINARY The product is in a preproduction phase and specifications are subject to change without notice. DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. Copyright March 1991 Gennum Corporation. All rights reserved. Printed in Canada

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