ECE 331 Digital System Design
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1 ECE 331 Digital System Design Counters (Lecture #20) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.
2 Counters A counter is a sequential circuit (aka. finite state machine) that cycles through a fixed sequence of states. The state of the counter is stored in Flip-Flops. An n-bit counter has n Flip-Flops can cycle through at most 2 n states. Spring 2011 ECE Digital System Design 2
3 Counters bit Counter 3-bit Counter Spring 2011 ECE Digital System Design 3
4 Counters bit Counter using only 3 states bit Counter using only 5 states Spring 2011 ECE Digital System Design 4
5 Binary Counters An n-bit binary counter is a counter that cycles through all 2 n states in ascending (or descending) order bit Binary Counter Cycles through all 8 states in ascending order Spring 2011 ECE Digital System Design 5
6 Binary Counters: Design 1.Draw a state graph that specifies the desired sequence of the counter. 2.Construct a state table from the state graph. One Flip-Flop for each bit in the state. 3.Derive a K-map from the state table for each Flip-Flop input. Select the type of Flip-Flop to be used. 4.Determine the input equation(s) for each Flip-Flop. Spring 2011 ECE Digital System Design 6
7 Binary Counters: Design Example: State Table (using D FF) Present State Next State FF Inputs C B A C + B + A + D C D B D A Characteristic Equation: Q + = D Spring 2011 ECE Digital System Design 7
8 Binary Counters: Design Example: K-maps (for D FF inputs) Spring 2011 ECE Digital System Design 8
9 Binary Counters: Design Example: Circuit Diagram (using D FF) Spring 2011 ECE Digital System Design 9
10 Binary Counters: Design Example: State Table (using T FF) Present State Next State FF Inputs C B A C + B + A + T C T B T A Characteristic Equation: Q + = T xor Q Excitation Table: Q Q + T Spring 2011 ECE Digital System Design 10
11 Binary Counters: Design Example: K-maps (for T FF inputs) Spring 2011 ECE Digital System Design 11
12 Binary Counters: Design Example: Circuit Diagram (using T FF) Spring 2011 ECE Digital System Design 12
13 Binary Up-Down Counters What constraints must be placed on the U and D control signals? Spring 2011 ECE Digital System Design 13
14 Binary Up-Down Counters Spring 2011 ECE Digital System Design 14
15 Loadable Counter with Enable Spring 2011 ECE Digital System Design 15
16 Counters: Design 1.Draw a state graph that specifies the desired sequence of the counter. 2.Construct a state table from the state graph. One Flip-Flop for each bit in the state. 3.Derive a K-map from the state table for each Flip-Flop input. Select the type of Flip-Flop to be used. 4.Determine the input equation(s) for each Flip-Flop. Spring 2011 ECE Digital System Design 16
17 Counters: Design Example: Design the following counter using D Flip-Flops. Spring 2011 ECE Digital System Design 17
18 Counters: Design Example: State Table (using D FF) Excitation Equation: D = Q + Present State Next State FF Inputs C B A C + B + A + D C D B D A x x x x x x x x x Spring 2011 ECE Digital System Design 18
19 Counters: Design Example: K-maps (for D FF inputs) D C D B D A Spring 2011 ECE Digital System Design 19
20 Counters: Design Example: Circuit Diagram (using D FF) Spring 2011 ECE Digital System Design 20
21 Counters: Design Example: Design the following counter using T Flip-Flops. Spring 2011 ECE Digital System Design 21
22 Counters: Design Example: State Table (using T FF) Excitation Equation: T = Q xor Q + Present State Next State FF Inputs C B A C + B + A + T C T B T A x x x x x x x x x Spring 2011 ECE Digital System Design 22
23 Counters: Design Example: K-maps (for T FF inputs) Spring 2011 ECE Digital System Design 23
24 Counters: Design Example: K-maps (for T FF inputs) We could derive T C, T B, and T A directly from the state table, but it is often more convenient to plot next-state maps showing C +, B +, and A + as functions of C, B, and A, and then derive T C, T B, and T A from these maps. Spring 2011 ECE Digital System Design 24
25 Counters: Design Example: Circuit Diagram (using T FF) Spring 2011 ECE Digital System Design 25
26 Counters: Design Example: Next States (for T FF inputs) Although the original state table for the counter is not completely specified, the next states of states 001, 101, and 110 have been specified in the process of completing the circuit design Spring
27 Counters: Design Example: Design the following counter using JK Flip-Flops. Spring 2011 ECE Digital System Design 27
28 Counters: Design Example: Using JK Flip-Flops Excitation Table: Q Q + J K x x 1 0 x x 0 Spring 2011 ECE Digital System Design 28
29 Counters: Design Example: State Table (using JK FF) Present State Next State FF Inputs C B A C + B + A + J C K C J B K B J A K A x x x x x x x x x Spring 2011 ECE Digital System Design 29
30 Counters: Design Example: K-maps (for JK FF inputs) Spring 2011 ECE Digital System Design 30
31 Counters: Design Example: Circuit Diagram (using JK FF) Spring 2011 ECE Digital System Design 31
32 Questions? Spring 2011 ECE Digital System Design 32
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