Synchronous sequential circuits

Size: px
Start display at page:

Download "Synchronous sequential circuits"

Transcription

1 8.6.5 Synchronous sequential Table of content. Combinational circuit design. Elementary combinatorial for data transmission. Memory structures 4. Programmable logic devices 5. Algorithmic minimization approaches 6. Sequential circuit design 6. Synthesis of sequential 6. Standard sequential 6.. Counters 6Shift 6.. Registers 7. Testing digital

2 Synthesis of sequential Specify the problem, circuit behaviour Definition of In- and Output variables Derive state diagram/ state table/ type of state machine (Moore, Mealy, ) => Result: uncoded state table of a certain type of machine; e.g. Moore Machine State coding Calculate FF equations Design circuit for the output function Choose type of flip flop and calculate flip-flops flops input functions Design of the circuit for the state transition function Eventual transformation of the logical expressions into suitable structured expressions Application in the circuit diagram 6. Synthesis of sequential Specify the problem, circuit behaviour Definition of In- and Output variables Derive state diagram/ state table/ type of state machine (Moore, Mealy, ) => Result: uncoded state table of a certain type of machine; e.g. Moore Machine 4

3 Synthesis of sequential Specify the problem, circuit behaviour Definition of In- and Output variables Derive state diagram/ state table/ type of state machine (Moore, Mealy, ) => Result: uncoded state table of a certain type of machine; e.g. Moore Machine 5 6. Synthesis of sequential Specify the problem, circuit behaviour Definition of In- and Output variables Derive state diagram/ state table/ type of state machine (Moore, Mealy, ) => Result: uncoded state table of a certain type of machine; e.g. Moore Machine State coding Present state Z Z. Zn Input Variables x x x xn Next states zij Out put Y Y.. Yn 6

4 Synthesis of sequential Specify the problem, circuit behaviour Definition of In- and Output variables Derive state diagram/ state table/ type of state machine (Moore, Mealy, ) => Result: uncoded state table of a certain type of machine; e.g. Moore Machine State coding/ number of FFs See example State minimization; if needed e.g. Moore Algorithm Present state Z Z. Zn Present state Input Variables x x x xn Next states zij Out put Y Y.. Yn ab ab ab ab Out I I II put Z= I I I Z= I I Z= I I Q Q Q Q 7 6. Synthesis of sequential Derive FF equations Present state ab ab ab ab Out I I II put Z= I I I Z= I I Z= I I Q Q Q Q 8 4

5 Synthesis of sequential Derive FF equations Present state ab ab ab ab Out I I II put Z= I I I Z= I I Z= I I Q Q Q Q 9 6. Synthesis of sequential Derive FF equations Present state ab ab ab ab Out I I II put Z= I I I Z= I I Z= I I Q Q Q Q Derive output function 5

6 Synthesis of sequential Combinatorial circuit Design circuit for the output function Flip Flops Combinatorial circuit 6. Synthesis of sequential Combinatorial circuit Choice of type of flip flop and calculate flip-flops input functions e.g. JK Flip Flops Flip Flops Combinatorial circuit 6

7 Synthesis of sequential Combinatorial circuit Flip Flops Combinatorial circuit 6. Synthesis of sequential Combinatorial circuit Design the circuit for the state transition function Flip Flops Combinatorial circuit 4 7

8 Synthesis of sequential 5 6. Synthesis of sequential Specify the problem, circuit behaviour Definition of In- and Output variables Derive state diagram/ state table/ type of state machine (Moore, Mealy, ) => Result: uncoded state table of a certain type of machine; e.g. Moore Machine State coding Calculate FF equations Design circuit for the output function Choose type of flip flop and calculate flip-flops flops input functions Design of the circuit for the state transition function Eventual transformation of the logical expressions into suitable structured expressions Application in the circuit diagram 6 8

9 Sequential standard 6.. Counters One common requirement in digital is counting, both forward and backward. Example: Digital clocks and watches, timers in a range of appliances from microwave ovens to VCRs counters for other reasons are found in everything from automobiles to test equipment Sequential standard 6.. Counters A binary counter is a sequential circuit that counts, while it proceeds through a pre-defined sequence of states every state of the circuit can be given a number => a counter produces a sequence of numbers => as our counter is a digital system; it counts in a dual number system => every state is interpreted as a dual number Example: - if flip-flop A,B and C are all => counter s state is. - if A is, B is and C is the counter s state is = 5 - and so on. 8 9

10 Sequential standard 6.. Counters The most basic counters will simply increment by with every clock pulse => so after state it will go to => the next pulse will let it switch to etc. It is possible to design counters with any needed counting sequence. Counters can be designed as synchronous sequential asynchronous sequential 9 6. Sequential standard 6.. Counters Characteristics of counters Step Size gives the (fixed) value by which the counter output is incremented/decremented by every pulse most binary counters use a step size of digital in contrast: offset-counters have a variable step size, that can change with every pulse Counting direction uni- directional counters can count in only one direction (forward OR backward) bi-directional counters can count in both directions => a special input line is needed to specify the direction Number format the actual state needs to be stored in a number system. any dual number system can be chosen influence on complexity, power consumption, etc. Implementation ti counters can be implemented in different ways. most common implementations as synchronous and asynchronous counters Even if in this lecture only synchronous sequential are discussed, a short overview on asynchronous counters will be given

11 Sequential standard 6.. Counters Counter Taxonomy of counters Offset Counter Binary Counter Synchronous Asynchronous Forward Backward Bidirektional Forward... Dual Code Dual Code BCD-Code BCD-Code Gray Code Gray Code Sequential standard 6.. Counters Counter design generally follows this scheme: Determination of the number of flip-flopsflops Setting up the state table Determination of the input functions for the flip-flops Creation of the circuit Determination of possible initial conditions at initiation of the circuit

12 Sequential standard 6.. Counters Synchronous counters all flip flops a clocked with the same pulse states of all flip flops change synchronous every of the n flip flops represents one digit of the counters output The simplest variation Uses no input lines Conects output lines direct to the flip flop output Example: Design of a 4-bit forward counter Counting sequence of a 4-bit forward counter Flip Flop Output is connected to flip flop output y=f(z) Moore Machine D C B A 4

13 8.6.5 Example: State table of 4-bit forward counter Current state Next state Current state Next state Q Q Q Q Q Q Q Q Fachgebiet Technische Informatik Q Q Q Q Q Q Q Q Q Q Q Q Q Q 5 Q Q Example: Flip Flop Equations From the KV-Maps it can be found: Q = QQ QQ Q = Q Q Q = Q Q Q Q Q Q Q = ( Q Q ) Q Q Q Q = Q ( Q Q Q ) Q Q Q Q = Q Q Q Q Q Q Q Q Q Q Implementation with JK-Flip Flops k = = J K = Q = J K = Q = Q Q = Q Q Q K = J = J = Q Q = Q Q Q = Q Q Q Q 6

14 Sequential standard 6.. Counters Asynchronous counters do not use the same clock signal for all flip-flops. the first flip-flop however is always controlled by the master clock signal. the clocking of the remaining flip-flops occurs by the outputs of the primary flip-flops. By that: not all flip-flops have to be designed for the maximum clock-input frequency C as not all flip-flops are switched by the master clock, the control functions for those flip-flops simplify. In total this leads: to less complex combinational for controlling the flip-flops to diffent timing beavior: for asynchronous counters propagation time grows with bit-width. 7 Asynchronous 4-bit forward counter Counting sequence from to IIII 8 4

15 Sequential standard 6.. Registers Registers are used to store complete data words (outside view) rather than a single bit use n flip flops, that are synchronously clocked 9 6. Sequential standard 6.. Registers Shift Registers In digital systems data words often are to be send or received bitwise => i.e. one bit every clock pulse. to store such data shift registers are used. a shift register has only one input. with every clock pulse - one bit is loaded into the first flip-flop of the register - while all the actual flip-flop contents are shifted and the oldest bit got dropped. From a circuit-based view the shift register as well as the counter consists of a pure sequential part and a pure combinational part. The data in the register are shifted by the clock pulses from one memory-cell to the next. Mostly a conversion of the data format is possible, such that serial inputs/outputs can be converted into parallel inputs/outputs. 5

16 8.6.5 Example: Design of a serial shift register Task: A -staged shift register for right shifting input-sequences x={,i} is to be designed. The state of the first input is constantly I and the flip-flops are clocked synchronously. Symbol: State table of a shift register Current State Next State I Q Q Q Q Q Q Q = I Q = Q Q = Q Realisation with D-Flip Flops Flip Flop Equations: 6

Logic and Computer Design Fundamentals. Chapter 7. Registers and Counters

Logic and Computer Design Fundamentals. Chapter 7. Registers and Counters Logic and Computer Design Fundamentals Chapter 7 Registers and Counters Registers Register a collection of binary storage elements In theory, a register is sequential logic which can be defined by a state

More information

Final Exam review: chapter 4 and 5. Supplement 3 and 4

Final Exam review: chapter 4 and 5. Supplement 3 and 4 Final Exam review: chapter 4 and 5. Supplement 3 and 4 1. A new type of synchronous flip-flop has the following characteristic table. Find the corresponding excitation table with don t cares used as much

More information

1. Convert the decimal number to binary, octal, and hexadecimal.

1. Convert the decimal number to binary, octal, and hexadecimal. 1. Convert the decimal number 435.64 to binary, octal, and hexadecimal. 2. Part A. Convert the circuit below into NAND gates. Insert or remove inverters as necessary. Part B. What is the propagation delay

More information

EE292: Fundamentals of ECE

EE292: Fundamentals of ECE EE292: Fundamentals of ECE Fall 2012 TTh 10:00-11:15 SEB 1242 Lecture 23 121120 http://www.ee.unlv.edu/~b1morris/ee292/ 2 Outline Review Combinatorial Logic Sequential Logic 3 Combinatorial Logic Circuits

More information

Sri Vidya College of Engineering And Technology. Virudhunagar Department of Electrical and Electronics Engineering

Sri Vidya College of Engineering And Technology. Virudhunagar Department of Electrical and Electronics Engineering Sri Vidya College of Engineering And Technology Virudhunagar 626 005 Department of Electrical and Electronics Engineering Year/ Semester/ Class : II/ III/ EEE Academic Year: 2017-2018 Subject Code/ Name:

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 8 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter

More information

Lecture 11: Synchronous Sequential Logic

Lecture 11: Synchronous Sequential Logic Lecture 11: Synchronous Sequential Logic Syed M. Mahmud, Ph.D ECE Department Wayne State University Aby K George, ECE Department, Wayne State University Contents Characteristic equations Analysis of clocked

More information

RS flip-flop using NOR gate

RS flip-flop using NOR gate RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two

More information

Synchronous Sequential Logic. Chapter 5

Synchronous Sequential Logic. Chapter 5 Synchronous Sequential Logic Chapter 5 5-1 Introduction Combinational circuits contains no memory elements the outputs depends on the inputs Synchronous Sequential Logic 5-2 5-2 Sequential Circuits Sequential

More information

Figure 30.1a Timing diagram of the divide by 60 minutes/seconds counter

Figure 30.1a Timing diagram of the divide by 60 minutes/seconds counter Digital Clock The timing diagram figure 30.1a shows the time interval t 6 to t 11 and t 19 to t 21. At time interval t 9 the units counter counts to 1001 (9) which is the terminal count of the 74x160 decade

More information

Synchronous Sequential Logic

Synchronous Sequential Logic Synchronous Sequential Logic ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2012 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines Sequential

More information

ECE 301 Digital Electronics

ECE 301 Digital Electronics ECE 301 Digital Electronics Derivation of Flip-Flop Input Equations and State Assignment (Lecture #24) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design,

More information

Digital Logic Design I

Digital Logic Design I Digital Logic Design I Synchronous Sequential Logic Mustafa Kemal Uyguroğlu Sequential Circuits Asynchronous Inputs Combinational Circuit Memory Elements Outputs Synchronous Inputs Combinational Circuit

More information

MC9211 Computer Organization

MC9211 Computer Organization MC9211 Computer Organization Unit 2 : Combinational and Sequential Circuits Lesson2 : Sequential Circuits (KSB) (MCA) (2009-12/ODD) (2009-10/1 A&B) Coverage Lesson2 Outlines the formal procedures for the

More information

Registers and Counters

Registers and Counters Registers and Counters Clocked sequential circuit = F/Fs and combinational gates Register Group of flip-flops (share a common clock and capable of storing one bit of information) Consist of a group of

More information

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 26.3.9. DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 5. LECTURE: ANALYSIS AND SYNTHESIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS 2nd (Spring) term 25/26 5.

More information

Registers and Counters

Registers and Counters Registers and Counters Clocked sequential circuit = F/Fs and combinational gates Register Group of flip-flops (share a common clock and capable of storing one bit of information) Consist of a group of

More information

Sequential Logic. Analysis and Synthesis. Joseph Cavahagh Santa Clara University. r & Francis. TaylonSi Francis Group. , Boca.Raton London New York \

Sequential Logic. Analysis and Synthesis. Joseph Cavahagh Santa Clara University. r & Francis. TaylonSi Francis Group. , Boca.Raton London New York \ Sequential Logic Analysis and Synthesis Joseph Cavahagh Santa Clara University r & Francis TaylonSi Francis Group, Boca.Raton London New York \ CRC is an imprint of the Taylor & Francis Group, an informa

More information

NH 67, Karur Trichy Highways, Puliyur C.F, Karur District UNIT-III SEQUENTIAL CIRCUITS

NH 67, Karur Trichy Highways, Puliyur C.F, Karur District UNIT-III SEQUENTIAL CIRCUITS NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF ELETRONICS AND COMMUNICATION ENGINEERING COURSE NOTES SUBJECT: DIGITAL ELECTRONICS CLASS: II YEAR ECE SUBJECT CODE: EC2203

More information

Synchronous Sequential Logic

Synchronous Sequential Logic Synchronous Sequential Logic ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines Sequential

More information

Digital Fundamentals: A Systems Approach

Digital Fundamentals: A Systems Approach Digital Fundamentals: A Systems Approach Counters Chapter 8 A System: Digital Clock Digital Clock: Counter Logic Diagram Digital Clock: Hours Counter & Decoders Finite State Machines Moore machine: One

More information

Chapter 6. Flip-Flops and Simple Flip-Flop Applications

Chapter 6. Flip-Flops and Simple Flip-Flop Applications Chapter 6 Flip-Flops and Simple Flip-Flop Applications Basic bistable element It is a circuit having two stable conditions (states). It can be used to store binary symbols. J. C. Huang, 2004 Digital Logic

More information

CHAPTER 6 COUNTERS & REGISTERS

CHAPTER 6 COUNTERS & REGISTERS CHAPTER 6 COUNTERS & REGISTERS 6.1 Asynchronous Counter 6.2 Synchronous Counter 6.3 State Machine 6.4 Basic Shift Register 6.5 Serial In/Serial Out Shift Register 6.6 Serial In/Parallel Out Shift Register

More information

Counters. ENT 263 Digital Electronics

Counters. ENT 263 Digital Electronics Counters ENT 263 Digital Electronics Objectives Describe the difference between an asynchronous and a synchronous counter Analyze counter timing diagram Analyze counter circuits Determine the sequence

More information

Chapter 4. Logic Design

Chapter 4. Logic Design Chapter 4 Logic Design 4.1 Introduction. In previous Chapter we studied gates and combinational circuits, which made by gates (AND, OR, NOT etc.). That can be represented by circuit diagram, truth table

More information

Chapter 5: Synchronous Sequential Logic

Chapter 5: Synchronous Sequential Logic Chapter 5: Synchronous Sequential Logic NCNU_2016_DD_5_1 Digital systems may contain memory for storing information. Combinational circuits contains no memory elements the outputs depends only on the inputs

More information

UNIT III. Combinational Circuit- Block Diagram. Sequential Circuit- Block Diagram

UNIT III. Combinational Circuit- Block Diagram. Sequential Circuit- Block Diagram UNIT III INTRODUCTION In combinational logic circuits, the outputs at any instant of time depend only on the input signals present at that time. For a change in input, the output occurs immediately. Combinational

More information

Sequential Digital Design. Laboratory Manual. Experiment #7. Counters

Sequential Digital Design. Laboratory Manual. Experiment #7. Counters The Islamic University of Gaza Engineering Faculty Department of Computer Engineering Spring 2018 ECOM 2022 Khaleel I. Shaheen Sequential Digital Design Laboratory Manual Experiment #7 Counters Objectives

More information

Counters

Counters Counters A counter is the most versatile and useful subsystems in the digital system. A counter driven by a clock can be used to count the number of clock cycles. Since clock pulses occur at known intervals,

More information

Logic Design II (17.342) Spring Lecture Outline

Logic Design II (17.342) Spring Lecture Outline Logic Design II (17.342) Spring 2012 Lecture Outline Class # 05 February 23, 2012 Dohn Bowden 1 Today s Lecture Analysis of Clocked Sequential Circuits Chapter 13 2 Course Admin 3 Administrative Admin

More information

DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute

DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 27.2.2. DIGITAL TECHNICS Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 6. LECTURE (ANALYSIS AND SYNTHESIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS) 26/27 6. LECTURE Analysis and

More information

WEEK 10. Sequential Circuits: Analysis and Design. Page 1

WEEK 10. Sequential Circuits: Analysis and Design. Page 1 WEEK 10 Sequential Circuits: Analysis and Design Page 1 Analysis of Clocked (Synchronous) Sequential Circuits Now that we have flip-flops and the concept of memory in our circuit, we might want to determine

More information

DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) COUNTERS

DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) COUNTERS COURSE / CODE DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) COUNTERS One common requirement in digital circuits is counting, both forward and backward. Digital clocks and

More information

L5 Sequential Circuit Design

L5 Sequential Circuit Design L Sequential Circuit Design Sequential Circuit Design Mealy and Moore Characteristic Equations Design Procedure Example Sequential Problem from specification to implementation Ref: Unit 14 of text 9/2/2012

More information

Switching Circuits & Logic Design, Fall Final Examination (1/13/2012, 3:30pm~5:20pm)

Switching Circuits & Logic Design, Fall Final Examination (1/13/2012, 3:30pm~5:20pm) Switching Circuits & Logic Design, Fall 2011 Final Examination (1/13/2012, 3:30pm~5:20pm) Problem 1: (15 points) Consider a new FF with three inputs, S, R, and T. No more than one of these inputs can be

More information

Logic Design. Flip Flops, Registers and Counters

Logic Design. Flip Flops, Registers and Counters Logic Design Flip Flops, Registers and Counters Introduction Combinational circuits: value of each output depends only on the values of inputs Sequential Circuits: values of outputs depend on inputs and

More information

CHAPTER1: Digital Logic Circuits

CHAPTER1: Digital Logic Circuits CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits 1 Sequential Circuits Introduction Composed of a combinational circuit to which the memory elements are connected to form a feedback

More information

Asynchronous (Ripple) Counters

Asynchronous (Ripple) Counters Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory. The chapter about flip-flops introduced

More information

EKT 121/4 ELEKTRONIK DIGIT 1

EKT 121/4 ELEKTRONIK DIGIT 1 EKT 2/4 ELEKTRONIK DIGIT Kolej Universiti Kejuruteraan Utara Malaysia Sequential Logic Circuits - COUNTERS - LATCHES (review) S-R R Latch S-R R Latch Active-LOW input INPUTS OUTPUTS S R Q Q COMMENTS Q

More information

Sequential Logic Circuits

Sequential Logic Circuits Sequential Logic Circuits By Dr. M. Hebaishy Digital Logic Design Ch- Rem.!) Types of Logic Circuits Combinational Logic Memoryless Outputs determined by current values of inputs Sequential Logic Has memory

More information

ELE2120 Digital Circuits and Systems. Tutorial Note 8

ELE2120 Digital Circuits and Systems. Tutorial Note 8 ELE2120 Digital Circuits and Systems Tutorial Note 8 Outline 1. Register 2. Counters 3. Synchronous Counter 4. Asynchronous Counter 5. Sequential Circuit Design Overview 1. Register Applications: temporally

More information

Chapter. Synchronous Sequential Circuits

Chapter. Synchronous Sequential Circuits Chapter 5 Synchronous Sequential Circuits Logic Circuits- Review Logic Circuits 2 Combinational Circuits Consists of logic gates whose outputs are determined from the current combination of inputs. Performs

More information

Decade Counters Mod-5 counter: Decade Counter:

Decade Counters Mod-5 counter: Decade Counter: Decade Counters We can design a decade counter using cascade of mod-5 and mod-2 counters. Mod-2 counter is just a single flip-flop with the two stable states as 0 and 1. Mod-5 counter: A typical mod-5

More information

Administrative issues. Sequential logic

Administrative issues. Sequential logic Administrative issues Midterm #1 will be given Tuesday, October 29, at 9:30am. The entire class period (75 minutes) will be used. Open book, open notes. DDPP sections: 2.1 2.6, 2.10 2.13, 3.1 3.4, 3.7,

More information

The reduction in the number of flip-flops in a sequential circuit is referred to as the state-reduction problem.

The reduction in the number of flip-flops in a sequential circuit is referred to as the state-reduction problem. State Reduction The reduction in the number of flip-flops in a sequential circuit is referred to as the state-reduction problem. State-reduction algorithms are concerned with procedures for reducing the

More information

Chapter 5 Synchronous Sequential Logic

Chapter 5 Synchronous Sequential Logic Chapter 5 Synchronous Sequential Logic Chih-Tsun Huang ( 黃稚存 ) http://nthucad.cs.nthu.edu.tw/~cthuang/ Department of Computer Science National Tsing Hua University Outline Introduction Storage Elements:

More information

CS6201 UNIT I PART-A. Develop or build the following Boolean function with NAND gate F(x,y,z)=(1,2,3,5,7).

CS6201 UNIT I PART-A. Develop or build the following Boolean function with NAND gate F(x,y,z)=(1,2,3,5,7). VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603203 DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING Academic Year: 2015-16 BANK - EVEN SEMESTER UNIT I PART-A 1 Find the octal equivalent of hexadecimal

More information

Department of CSIT. Class: B.SC Semester: II Year: 2013 Paper Title: Introduction to logics of Computer Max Marks: 30

Department of CSIT. Class: B.SC Semester: II Year: 2013 Paper Title: Introduction to logics of Computer Max Marks: 30 Department of CSIT Class: B.SC Semester: II Year: 2013 Paper Title: Introduction to logics of Computer Max Marks: 30 Section A: (All 10 questions compulsory) 10X1=10 Very Short Answer Questions: Write

More information

Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill

Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Objectives: Analyze the operation of sequential logic circuits. Understand the operation of digital counters.

More information

EET2411 DIGITAL ELECTRONICS

EET2411 DIGITAL ELECTRONICS 5-8 Clocked D Flip-FlopFlop One data input. The output changes to the value of the input at either the positive going or negative going clock trigger. May be implemented with a J-K FF by tying the J input

More information

Experiment 8 Introduction to Latches and Flip-Flops and registers

Experiment 8 Introduction to Latches and Flip-Flops and registers Experiment 8 Introduction to Latches and Flip-Flops and registers Introduction: The logic circuits that have been used until now were combinational logic circuits since the output of the device depends

More information

Section 6.8 Synthesis of Sequential Logic Page 1 of 8

Section 6.8 Synthesis of Sequential Logic Page 1 of 8 Section 6.8 Synthesis of Sequential Logic Page of 8 6.8 Synthesis of Sequential Logic Steps:. Given a description (usually in words), develop the state diagram. 2. Convert the state diagram to a next-state

More information

Switching Theory And Logic Design UNIT-IV SEQUENTIAL LOGIC CIRCUITS

Switching Theory And Logic Design UNIT-IV SEQUENTIAL LOGIC CIRCUITS Switching Theory And Logic Design UNIT-IV SEQUENTIAL LOGIC CIRCUITS Sequential circuits Classification of sequential circuits: Sequential circuits may be classified as two types. 1. Synchronous sequential

More information

Counter dan Register

Counter dan Register Counter dan Register Introduction Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory.

More information

Unit 11. Latches and Flip-Flops

Unit 11. Latches and Flip-Flops Unit 11 Latches and Flip-Flops 1 Combinational Circuits A combinational circuit consists of logic gates whose outputs, at any time, are determined by combining the values of the inputs. For n input variables,

More information

UNIT IV. Sequential circuit

UNIT IV. Sequential circuit UNIT IV Sequential circuit Introduction In the previous session, we said that the output of a combinational circuit depends solely upon the input. The implication is that combinational circuits have no

More information

CHAPTER 4: Logic Circuits

CHAPTER 4: Logic Circuits CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits

More information

Digital Design, Kyung Hee Univ. Chapter 5. Synchronous Sequential Logic

Digital Design, Kyung Hee Univ. Chapter 5. Synchronous Sequential Logic Chapter 5. Synchronous Sequential Logic 1 5.1 Introduction Electronic products: ability to send, receive, store, retrieve, and process information in binary format Dependence on past values of inputs Sequential

More information

Universidad Carlos III de Madrid Digital Electronics Exercises

Universidad Carlos III de Madrid Digital Electronics Exercises 1. Complete the chronogram for the circuit given in the figure. inst7 NOT A INPUT VCC AND2 inst5 DFF D PRN Q CLRN inst XOR inst2 TFF PRN T Q CLRN inst8 OUTPUT OUTPUT Q Q1 CLK INPUT VCC CLEARN INPUT VCC

More information

Chapter 6 Digital Circuit 6-5 Department of Mechanical Engineering

Chapter 6 Digital Circuit 6-5 Department of Mechanical Engineering MEMS1082 Chapter 6 Digital Circuit 6-5 General digital system D Flip-Flops, The D flip-flop is a modification of the clocked SR flip-flop. The D input goes directly into the S input and the complement

More information

Lecture 8: Sequential Logic

Lecture 8: Sequential Logic Lecture 8: Sequential Logic Last lecture discussed how we can use digital electronics to do combinatorial logic we designed circuits that gave an immediate output when presented with a given set of inputs

More information

CHAPTER 4: Logic Circuits

CHAPTER 4: Logic Circuits CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits

More information

Find the equivalent decimal value for the given value Other number system to decimal ( Sample)

Find the equivalent decimal value for the given value Other number system to decimal ( Sample) VELAMMAL COLLEGE OF ENGINEERING AND TECHNOLOGY, MADURAI 65 009 Department of Information Technology Model Exam-II-Question bank PART A (Answer for all Questions) (8 X = 6) K CO Marks Find the equivalent

More information

Solution to Digital Logic )What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it,

Solution to Digital Logic )What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it, Solution to Digital Logic -2067 Solution to digital logic 2067 1.)What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it, A Magnitude comparator is a combinational

More information

1.b. Realize a 5-input NOR function using 2-input NOR gates only.

1.b. Realize a 5-input NOR function using 2-input NOR gates only. . [3 points] Short Questions.a. Prove or disprove that the operators (,XOR) form a complete set. Remember that the operator ( ) is implication such that: A B A B.b. Realize a 5-input NOR function using

More information

ECE 331 Digital System Design

ECE 331 Digital System Design ECE 331 Digital System Design Counters (Lecture #20) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and were used

More information

ECE 301 Digital Electronics

ECE 301 Digital Electronics ECE 301 Digital Electronics Counters (Lecture #20) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and were used with

More information

B.Tech CSE Sem. 3 15CS202 DIGITAL SYSTEM DESIGN (Regulations 2015) UNIT -IV

B.Tech CSE Sem. 3 15CS202 DIGITAL SYSTEM DESIGN (Regulations 2015) UNIT -IV B.Tech CSE Sem. 3 5CS22 DIGITAL SYSTEM DESIGN (Regulations 25) UNIT -IV SYNCHRONOUS SEQUENTIAL CIRCUITS OUTLINE FlipFlops SR,D,JK,T Analysis of Synchronous Sequential Circuit State Reduction and Assignment

More information

Using minterms, m-notation / decimal notation Sum = Cout = Using maxterms, M-notation Sum = Cout =

Using minterms, m-notation / decimal notation Sum = Cout = Using maxterms, M-notation Sum = Cout = 1 Review of Digital Logic Design Fundamentals Logic circuits: 1. Combinational Logic: No memory, present output depends only on the present input 2. Sequential Logic: Has memory, present output depends

More information

Digital Logic Design ENEE x. Lecture 19

Digital Logic Design ENEE x. Lecture 19 Digital Logic Design ENEE 244-010x Lecture 19 Announcements Homework 8 due on Monday, 11/23. Agenda Last time: Timing Considerations (6.3) Master-Slave Flip-Flops (6.4) This time: Edge-Triggered Flip-Flops

More information

Experiment # 9. Clock generator circuits & Counters. Digital Design LAB

Experiment # 9. Clock generator circuits & Counters. Digital Design LAB Digital Design LAB Islamic University Gaza Engineering Faculty Department of Computer Engineering Fall 2012 ECOM 2112: Digital Design LAB Eng: Ahmed M. Ayash Experiment # 9 Clock generator circuits & Counters

More information

CSE Latches and Flip-flops Dr. Izadi. NOR gate property: A B Z Cross coupled NOR gates: S M S R Q M

CSE Latches and Flip-flops Dr. Izadi. NOR gate property: A B Z Cross coupled NOR gates: S M S R Q M CSE-4523 Latches and Flip-flops Dr. Izadi NOR gate property: A B Z A B Z Cross coupled NOR gates: S M S R M R S M R S R S R M S S M R R S ' Gate R Gate S R S G R S R (t+) S G R Flip_flops:. S-R flip-flop

More information

CPS311 Lecture: Sequential Circuits

CPS311 Lecture: Sequential Circuits CPS311 Lecture: Sequential Circuits Last revised August 4, 2015 Objectives: 1. To introduce asynchronous and synchronous flip-flops (latches and pulsetriggered, plus asynchronous preset/clear) 2. To introduce

More information

Objectives. Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath

Objectives. Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath Objectives Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath In the previous chapters we have studied how to develop a specification from a given application, and

More information

RS flip-flop using NOR gate

RS flip-flop using NOR gate RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two

More information

DIGITAL SYSTEM DESIGN UNIT I (2 MARKS)

DIGITAL SYSTEM DESIGN UNIT I (2 MARKS) DIGITAL SYSTEM DESIGN UNIT I (2 MARKS) 1. Convert Binary number (111101100) 2 to Octal equivalent. 2. Convert Binary (1101100010011011) 2 to Hexadecimal equivalent. 3. Simplify the following Boolean function

More information

# "$ $ # %!"$!# &!'$("!)!"! $ # *!"! $ '!!$ #!!)! $ "# ' "

# $ $ # %!$!# &!'$(!)!! $ # *!! $ '!!$ #!!)! $ # ' !" #!""! # "$ $ # %!"$!# &!'$("!)!"! $ # *!"! $ '!!$ #!!)! $ "# ' " % &! # Design a combinational logic circuit 10:4 encoder which has a 10-bit input (D9 to D0) and a 4-bit output. If bit position i of

More information

Combinational / Sequential Logic

Combinational / Sequential Logic Digital Circuit Design and Language Combinational / Sequential Logic Chang, Ik Joon Kyunghee University Combinational Logic + The outputs are determined by the present inputs + Consist of input/output

More information

Registers and Counters

Registers and Counters Registers and Counters ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2011 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Registers Shift Registers

More information

Analysis of Clocked Sequential Circuits

Analysis of Clocked Sequential Circuits Analysis of Clocked Sequential Circuits COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Analysis of Clocked Sequential circuits State

More information

INC 253 Digital and electronics laboratory I

INC 253 Digital and electronics laboratory I INC 253 Digital and electronics laboratory I Laboratory 9 Sequential Circuit Author: ID Co-Authors: 1. ID 2. ID 3. ID Experiment Date: Report received Date: Comments For Instructor Full Marks Pre lab 10

More information

MUHAMMAD NAEEM LATIF MCS 3 RD SEMESTER KHANEWAL

MUHAMMAD NAEEM LATIF MCS 3 RD SEMESTER KHANEWAL 1. A stage in a shift register consists of (a) a latch (b) a flip-flop (c) a byte of storage (d) from bits of storage 2. To serially shift a byte of data into a shift register, there must be (a) one click

More information

UNIT 1 NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES 1. Briefly explain the stream lined method of converting binary to decimal number with example. 2. Give the Gray code for the binary number (111) 2. 3.

More information

Logic Design Viva Question Bank Compiled By Channveer Patil

Logic Design Viva Question Bank Compiled By Channveer Patil Logic Design Viva Question Bank Compiled By Channveer Patil Title of the Practical: Verify the truth table of logic gates AND, OR, NOT, NAND and NOR gates/ Design Basic Gates Using NAND/NOR gates. Q.1

More information

Computer Organization & Architecture Lecture #5

Computer Organization & Architecture Lecture #5 Computer Organization & Architecture Lecture #5 Shift Register A shift register is a register in which binary data can be stored and then shifted left or right when a shift signal is applied. Bits shifted

More information

Registers and Counters

Registers and Counters Registers and Counters ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Registers Shift Registers

More information

Dr. Shahram Shirani COE2DI4 Midterm Test #2 Nov 19, 2008

Dr. Shahram Shirani COE2DI4 Midterm Test #2 Nov 19, 2008 Page 1 Dr. Shahram Shirani COE2DI4 Midterm Test #2 Nov 19, 2008 Instructions: This examination paper includes 13 pages and 20 multiple-choice questions starting on page 3. You are responsible for ensuring

More information

Vignana Bharathi Institute of Technology UNIT 4 DLD

Vignana Bharathi Institute of Technology UNIT 4 DLD DLD UNIT IV Synchronous Sequential Circuits, Latches, Flip-flops, analysis of clocked sequential circuits, Registers, Shift registers, Ripple counters, Synchronous counters, other counters. Asynchronous

More information

Contents Circuits... 1

Contents Circuits... 1 Contents Circuits... 1 Categories of Circuits... 1 Description of the operations of circuits... 2 Classification of Combinational Logic... 2 1. Adder... 3 2. Decoder:... 3 Memory Address Decoder... 5 Encoder...

More information

Advanced Digital Logic Design EECS 303

Advanced Digital Logic Design EECS 303 Advanced Digital Logic Design EECS 303 http://ziyang.eecs.northwestern.edu/eecs303/ Teacher: Robert Dick Office: L477 Tech Email: dickrp@northwestern.edu Phone: 847 467 2298 Outline Introduction Reset/set

More information

Lecture 12. Amirali Baniasadi

Lecture 12. Amirali Baniasadi CENG 24 Digital Design Lecture 2 Amirali Baniasadi amirali@ece.uvic.ca This Lecture Chapter 6: Registers and Counters 2 Registers Sequential circuits are classified based in their function, e.g., registers.

More information

Chapter 6 Registers and Counters

Chapter 6 Registers and Counters EEA051 - Digital Logic 數位邏輯 Chapter 6 Registers and Counters 吳俊興國立高雄大學資訊工程學系 January 2006 Chapter 6 Registers and Counters 6-1 Registers 6-2 Shift Registers 6-3 Ripple Counters 6-4 Synchronous Counters

More information

Chapter 2. Digital Circuits

Chapter 2. Digital Circuits Chapter 2. Digital Circuits Logic gates Flip-flops FF registers IC registers Data bus Encoders/Decoders Multiplexers Troubleshooting digital circuits Most contents of this chapter were covered in 88-217

More information

St. MARTIN S ENGINEERING COLLEGE

St. MARTIN S ENGINEERING COLLEGE St. MARTIN S ENGINEERING COLLEGE Dhulapally, Kompally, Secunderabad-500014. Branch Year&Sem Subject Name : Electronics and Communication Engineering : II B. Tech I Semester : SWITCHING THEORY AND LOGIC

More information

Chapter 11 State Machine Design

Chapter 11 State Machine Design Chapter State Machine Design CHAPTER OBJECTIVES Upon successful completion of this chapter, you will be able to: Describe the components of a state machine. Distinguish between Moore and Mealy implementations

More information

Universal Asynchronous Receiver- Transmitter (UART)

Universal Asynchronous Receiver- Transmitter (UART) Universal Asynchronous Receiver- Transmitter (UART) (UART) Block Diagram Four-Bit Bidirectional Shift Register Shift Register Counters Shift registers can form useful counters by recirculating a pattern

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter

More information

Synchronous Sequential Logic

Synchronous Sequential Logic MEC520 디지털공학 Synchronous Sequential Logic Jee-Hwan Ryu School of Mechanical Engineering Sequential Circuits Outputs are function of inputs and present states Present states are supplied by memory elements

More information

Introduction. NAND Gate Latch. Digital Logic Design 1 FLIP-FLOP. Digital Logic Design 1

Introduction. NAND Gate Latch.  Digital Logic Design 1 FLIP-FLOP. Digital Logic Design 1 2007 Introduction BK TP.HCM FLIP-FLOP So far we have seen Combinational Logic The output(s) depends only on the current values of the input variables Here we will look at Sequential Logic circuits The

More information

EECS150 - Digital Design Lecture 19 - Finite State Machines Revisited

EECS150 - Digital Design Lecture 19 - Finite State Machines Revisited EECS150 - Digital Design Lecture 19 - Finite State Machines Revisited April 2, 2013 John Wawrzynek Spring 2013 EECS150 - Lec19-fsm Page 1 Finite State Machines (FSMs) FSM circuits are a type of sequential

More information