HW#3 - CSE 237A. 1. A scheduler has three queues; A, B and C. Outgoing link speed is 3 bits/sec

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1 HW#3 - CSE 237A 1. A scheduler has three queues; A, B and C. Outgoing link speed is 3 bits/sec a. (Assume queue A wants to transmit at 1 bit/sec, and queue B at 2 bits/sec and queue C at 3 bits/sec. What actual rate are connections operating on if maxmin fairness allocation is in effect? b. You are given queue weights (A,B,C) = (1,2,3) for a set of packets P1-3 whose size is shown in bits for each queue. All packets are ready for transmission at time 0. Answer the following: i. What is the order of first 5 packet transmission assuming WFQ? ii. How long does the transmission of those 5 packets take? Finish numbers: P1A = 2 P2A=5 P3A=7 P1B=2 P2B=3 P3B=4 P1C=1/3 P2C=1 P3C=2 Final order of first five packets: P1C, P2C, P3C, P1B, P1A Note: any permutation of P1A, P1B and P3C is correct since their finish numbers are the same Length of packets in bits: 1, 2, 3, 4, 2 Total length transmitted: 12 bits Outgoing link speed: 3 bits/sec Transmit time: 4 seconds prof. Tajana Simunic Rosing 1

2 2. Two processors (P1,P2) are used to execute three tasks (A,B,C) with restriction that tasks A and C can execute only on P1, while B only on P2. Computation is complete when final result of computation of task C is stored in memory. Note that memory transfer time does not include the network time. You may assume that data for tasks A and B is available in on-chip cache and thus does not need to be loaded from memory at start of execution. Exec time at max freq Component Exec Time Task A 2 on P1 Task B 3 on P2 Task C 1 on P1 Mem 3 Net 2 Power values State Active Idle P1,2 Max Freq. 5 1 P1,2 Half Freq. 2 1 Mem 3 1 Net 2 0 a. Derive a schedule that gives the fastest time to completion of the three processes given the data flow graph. Fastest completion time from start to storing result of process C in memory is 11 cycles. prof. Tajana Simunic Rosing 2

3 b. What is the minimum power consumption you can obtain while still meeting the fastest completion time computed in part a? How much power savings is that over the original schedule? Assume processors can run only at two speeds maximum and half the maximum. Original schedule power consumption: Component # active cycles # idle cycles Pactive Pidle Ptotal P1 - A P1 - C P Mem Net System 71 Since there is slack only in one task task A, there will be savings only due to slowing down task A. New schedule power consumption: Component # active cycles # idle cycles Pactive Pidle Ptotal P1 - A P1 - C P Mem Net System 67 Power savings are relatively small (61-57)/61 = 6.6% or only 4 units prof. Tajana Simunic Rosing 3

4 4. Show why Lamport s scalar clock is not strongly consistent the example below. Label all events with their logical clock values. Show how it can be extended to become strongly consistent on the same example. Again, make sure to label all events. Strong consistency: C(e1) < C(e2) => e1 -> e2 With Lamport s clock it is not possible to keep strong consistency, it has to be extended with a vector clock in order to become strongly consistent Lamport s logical clock e.g. we can t tell if event 3 on p1 happened before or after event 3 on p P1 P vectored time [1,0] [2,2] [3,2] [4,4] [5,4] P1 P2 prof. Tajana Simunic Rosing 4

5 [0,1] [0,2] [0,3] [3,4] [3,5] [4,6] 5. Schedule the following independent tasks on the single processor; the task period equals the deadline: T1 (start time = 2, exec time=5,period=8), T2 (0,1,10), T3 (6,1,5) using: a. EDF Priorities are dynamic available process with soonest deadline wins. Given the periods of the tasks, the schedule should repeat every 40 time units. Task Exec Period (Available time, deadline) T ,10 10,18 18,26 26,34 34,42 T ,10 10,20 20,30 30,40 T ,11 11,16 16,21 21,26 26,31 31,36 36,41 b. RM Check utilization: 5/8+1/10+1/5 = 37/40 > 0.78 = max utilization for a guaranteed feasible schedule. Note that the schedule might still be possible as long as utilization is <100%. In our case, task priorities are T3>T1>T2. prof. Tajana Simunic Rosing 5

6 c. Determine the maximum possible execution time and minimum period of an additional task T4(0,e,p) and show the schedule of all four tasks using: RM & EDF: 5/8 + 1/10 + 1/5 = 37/40 -> thus we have space for 3 exec units in period of 40: T4 ( 0, 3, 40 ) The task T4 just fills the gaps in schedule given in part a. Note that there is one extra gap in the first hyperperiod since task T3 started after its first period was over. prof. Tajana Simunic Rosing 6

7 6. Draw a block diagram of a CPU, memory and peripheral connected with a system bus, in which peripheral gets serviced using vectored interrupts. Assume servicing moves data from the peripheral to the memory. Show all relevant control and data lines of the bus, label component inputs/outputs clearly. Use symbolic values for addresses. Provide a timing diagram illustrating what happens over the system bus during the interrupt. Program memory ISR 16: MOV R0, 0x : # modifies R0 18: MOV 0x8001, R0 19: RETI # ISR return... Main program : 101: instruction instruction μp PC Int Data memory System bus P1 P2 0x8000 0x8001 Description of what happens: 1(a): μp is executing its main program 1(b): P1 receives input data in a register with address 0x : P1 asserts Int to request servicing by the microprocessor 3: After completing instruction at 100, μp sees Int asserted, saves the PC s value of 100, and sets PC to the ISR fixed location of 16. 4(a): The ISR reads data from 0x8000, modifies the data, and writes the resulting data to 0x (b): After being read, P1 deasserts Int. 5: The ISR returns, thus restoring PC to 100+1=101, where μp resumes executing. prof. Tajana Simunic Rosing 7

8 7. You are given five tasks (T1-5) and four different HW implementations: HW1-3 (costs 25,20,30) and a processor P (cost 15). The table below shows the execution times for running each task at each HW/P unit. The task graph deadline is 90 units. Show a) fastest and b) minimum cost partitioning of tasks among HW elements and the processor. Is there an optimal solution that is faster than all others while being minimum cost? Show. T H1 H2 H3 P a) Fastest: T1 on H1 10 T3 on H3 10 concurrent T2 on H1 T4 on H3 10 T5 on H1 10 Total exec time: 40 units b) Lowest cost: order of cost starting from lowest: P, H2, H1, H Critical path: t1,3,4,5 must execute in 90 time units Task HW Exec time Cost Concurrent HW 1 H H Task 2 H1 4 H H1 10 Total cost: 55 units for H3 and H1; note that P/H3 combination can t be used due to deadline miss due to concurrency of tasks 3-4 and 2. Exec time: 40 units c) Minimum exec time that is also very cost efficient: Select H1 and H3 same answer as before Minimum cost while exec time is 45 instead of 40 units: select HW1 for T1,2,4,5 and P for task 3 prof. Tajana Simunic Rosing 8

9 8. Your job is to design a new small (and cheap!) automated insulin regulator capable of the following major tasks: 1. Sample blood sugar levels at regular intervals preset by the doctor (not the patient!) 2. If levels are high, inject appropriate amount of insulin; the amount is calculated as follows; 3. If levels are too low, inject sugar into the patient, the amount is calculated as follows: 4. Sample sugar levels at short intervals after injection 30s, 1min, 5min, and every 5min until 30min passes. Sound an alarm if within 30min period sugar levels don t stabilize. 5. Sound an alarm when either insulin or sugar containers are close to empty (10% level). 6. Sounding an alarm includes sending a notification to the patient s cell phone via Bluetooth, and dialing the doctor s phone. 7. If the patient s sugar levels are below 50 at 30min mark, sound an alarm and dial 911. Outline how you would perform the design process. Specifically: 1. Draw a block diagram of HW components you d need to use, explain why you selected the given configuration and how communication between components should be implemented 2. Discuss what SW you would need to implement and what kind of OS, if any, might you use? 3. Is there a need for computation/communication scheduling? If so, what schedulers are appropriate? 4. What model of computation would you use for each part of the design? Illustrate. 5. What kinds of sensors/actuators do you need? How do you interface with them? What kinds of AD/DA converters might you need? Comment on their characteristics. 6. Is there a need for open and/or closed loop control in the design, and if so, describe where and how it would be implemented This problem will be graded based on completeness of the answers, there are many possible correct answers. prof. Tajana Simunic Rosing 9

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