Registers. Unit 12 Registers and Counters. Registers (D Flip-Flop based) Register Transfers (example not out of text) Accumulator Registers

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1 Unit 2 Registers and Counters Fundamentals of Logic esign EE2369 Prof. Eric Maconald Fall Semester 23 Registers Groups of flip-flops Can contain data format can be unsigned, 2 s complement and other more complex formats (floating point, etc.) share common input (bus) and output (bus as well) share common clock (gated identically) Can contain control information each bit enabling/disabling feature of bigger design Outputs can be tri-statable and ganged with other registers to form tri-state bus. Registers ( Flip-Flop based) Register Transfers (example not out of text) [3:] [3] [2] [] [] resetn load [3] [2] [] [] [3:] A load B load C load load 8 bit reg 8 bit reg 8 bit reg 8 bit reg ALU (+,-) two 8b tri-state busses two b enable busses How should the inputs be set to add B + C and store result in A? Accumulators Accumulators can add stream of numbers to take average (must divide number after sum complete) for digital signal processing algorithm serial multiplication (to add partial products) Combines Adder with Register one input of adder is register output output of adder is input of register Must include reset to start from zero Accumulator Registers [3:] X[3] X[2] X[] X[] resetn load fa fa fa fa SP Algorithm = A*X + A2*X2 + A3*X3 (e.g. low pass filter) Average = (X + X2 + X3 + X + X5 + X6 + X7 + X8) / 8 Y[3:] Y[3] Y[2] Y[] Y[]

2 Accumulator example Accumulator in action Clr In[3:] Next Out [7:] 8 bit register Out [7:] In[3:] Out[7:] x clrn Next Out[7:] x Shift Registers Shift Registers Chain of Flip-Flops (input of one to output of next) Can convert serial data to/from parallel data Can add multiple cycles of delay to signal Most likely circuit to fail hold requirements data path between FF can be nothing more than a wire clock skew must be monitored with care Shift Registers multiple cycles of delay Counters SI 2 SO One of the simplest forms of state machine state of a circuit means the value of the flops and latches the next state is the values in the next clock cycle determined by current state (at least) and also circuit inputs use next state information to design inputs to FF and latches Counters repeatedly run through sequence of numbers most commonly in an ascending order with wrap around can be descending can be any arbitrary sequence (useful for control) can be several sequences one of which is chosen based on inputs 2

3 T-Flop Counter Ripple Counter (not in book or test) Using data signal as clock is often discouraged in chip design methodologies. But this is a dense design style -Flop Counter Up-own Counter Up-own Counter Loadable Counter - specification A + = a = (Ld *A + Ld* a ) ^ Ld *Ct B + = b = (Ld *B + Ld* b ) ^ Ld *Ct*A C + = c = (Ld *C + Ld* c ) ^ Ld *Ct*B*A 3

4 Loadable Counter implementation Second Example with -Flops Microcontroller Instruction Sequencer no pipelining fetch decode execute write side note: bad processor design to leave a bubble in the pipe - done for enhance example

5 Microcontroller Instruction Sequencer Counter with hold control input write back results bubble for example only Fetch instruction Fetch and decode finish decode execute (need two cycles) h= h= h= h= h= h= Reset input could be added that forces the next state to be Otherwise, at power up some random value will be in the flops and the sequence will start from that point. Counter with hold control input state table Example istributor two choices A B C Hold A+ B+ C+ Specification: Four enables to fire spark plugs in a car. Enables must be mutually exclusive or damage to engine can occur. Enables must be periodic. Case : states requires two flops and a. Small but glitches. Case 2: states uses four flops and will not glitch. Known as one-hot state-machine Can not tolerate glitches. 5