Fault Detection And Correction Using MLD For Memory Applications

Transcription

1 Fault Detection And Correction Using MLD For Memory Applications Jayasanthi Sambbandam & G. Jose ECE Dept. Easwari Engineering College, Ramapuram shanthisindia@yahoo.com & josejeyamani@gmail.com Abstract This paper proposes a error detection mechanism with Majority Logic Decoding and a novel test pattern generator (TPG) for built-in self test. The Majority Logic Decodable codes can correct a large number of errors and they are suitable for memory applications. Our method reduces the memory access time. The reason for using ML decoding is that it is very simple to implement and thus it is very practical and has low complexity. The TPG generates multiple single input change (MSIC)vectors in a pattern. It is flexible to both test per clock and test per scan schemes. The decoder makes minimal area overhead and low power consumption. The TPG can be demonstrated with ISCAS benchmarks,which also achieves target fault coverage. Index Terms Single Event Upset (SEU), Multiple Single Input Change (MSIC), Majority Logic(ML),Test Pattern Generator (TPG). I. INTRODUCTION The SRAM memory failure rates are increasing significantly, therefore posing a major reliability concern for memory applications. The commonly used mitigation technique is error correction code(ecc). The ECC codes are the best way to mitigate memory soft errors. The frequently used ECC codes are SER(Single Error Correction) SEC--DED(Single Error Correction Double Error Detection) RS(Reed Solomon) BCH(Bose Chaudhuri Hocquenghem) Cyclic Codes The above codes are not suitable for mitigating memory soft errors. Because they use more sophisticated decoding algorithms like complex decoders, and they use iterative algorithms. Along with that they are very complex and increase computational costs [1]. Among the ECC codes, cyclic codes are identified to be good because of the higher error correction capability and low decoding complexity [2],[3]. Also it has the property of being Majority Logic Decodable. In this paper one specific type of LDPC codes called Difference Set Cyclic Codes are used. It is widely used in Japanese teletext system or FM multiplex broadcasting system [4]-[6]. The drawback is that for a coded word of N bits it takes N cycles. It poses a big impact on system performance [1]. The solution for this problem is to implement parallel encoders and decoders. But by doing so, the complexity will be increased and so does the power consumption. The memory reading pare will be working all the time. So the number of cycles will be more. This motivated the use of fault detector module that checks only if the codeword contains an error [7]. This ultimately speeds up the average read memory access. A. Prior Work In MLD MLD is based on the number of parity check equations. The majority result of these parity check equation decide the correctness of the bit under decoding. A memory system schematic with MLD is shown in Fig. 1. The data words are encoded in the encoder block. The encoded bits are then stored in the memory. When the memory is read, the codeword is sent to the ML decoder. Here all the bit flips get corrected. 65

2 The ML decoder is simple and powerful, capable of correcting multiple random bit flips. As illustrated in Fig. 2 the ML decoder consists of four parts:1)a cyclic shift register;2)an x-or matrix;3)a majority gate;4)an x- or. The input signal x is stored into the cyclic shift register and is shifted through all the taps. The intermediate values are used to calculate the parity check equations. The final tap will be producing output signal y, which is the decoded version of input x. While calculating the parity check equations, if the number of 1 s received is greater than the number of 0 s, then it indicates that the current bit under decoding is wrong. Next the signal to correct the bit would be triggered. Otherwise, the bit under decoding would be correct and no further operations are needed. The above procedure is repeated until all the codeword bits have been processed. Finally the parity checksums should be zero, if the codeword has been correctly decoded [8]. It needs as many cycles as the number of bits in the decoder. This is a big impact on system performance. One possibility is to add a separate fault detector module, by calculating the syndrome. So faulty codewords alone are decoded [9]. Since most of the codewords are error free the performance will not be affected. It is not applicable because it adds complexity to the design and also it requires large amount of additional hardware and power consumption. In order to overcome this, a new design and the modified version of ML decoder is presented. B. BIST Techniques The BIST techniques are further classified in to three classes. It is classified into three classes. In the first class, the method used is LFSR tuning. It is mainly used for energy reduction [10]. The second class is low power TPGs. The two LFSR s of different speed are used to control those inputs that have elevated transition densities. Another low power TPG based on the cellular automata to reduce the test power. The third class makes use of the prevention of pseudorandom patterns [11-13]. They have minimum number of test vectors to attain the target fault coverage and therefore reduce the power. Several low power approaches have also been proposed for scan-based BIST. Using multiple scan chains, the TPG can reduce average power consumption and the peak power in the CUT [14]. The proposed method generates SIC sequences and converts them into low transition sequences. This decreases the switching activity. The advantages of the proposed sequences can be summarized as follows. 1) Minimum Transitions The generated vector applied to each scan chain is an SIC vector, which minimizes the input transition and reduce the test power. 2) Uniqueness of patterns The sequence does not contain any repeated patterns. The distinct patterns in the sequence can meet the target fault coverage. 3) Uniform Distribution of Patterns The conventional algorithms use extra hardware to get more correlated test vectors. They may reduce the randomness in the patterns. It is proved that MSIC sequence is uniformly distributed. 4) Low Hardware Overhead It has the benefit of generating a sequence with a sequential decompressor. Hence, it can be easily implemented by hardware. II. PROPOSED MLDD This section presents a modified version of the ML decoder. It has been implemented using DSCC. In this paper a new class of random error correcting cyclic codes is defined. These codes have two desirable features: the binary members of the class are as powerful as the best known codes in the range of interest, and they can be decoded with the simplest known decoding algorithm. Unfortunately, there are relatively few codes with useful parameters in this class, despite the fact that the class is infinite. Because the codes are cyclic they can be encoded easily. The code efficiency for the DSCC code is The number of transistors used is 1200.The decoder clock rate is 1.It is very simple ease of design, construction and testing. Consequently they are concluded to be attractive for use 66

3 in error control systems where forward acting error correction is required. These codes have the following properties: ability to correct large number of errors modular encoder and decoder blocks that allow an efficient hardware implementation; systematic code structure for clean partition of information and code bits in the memory. In general, the decoding algorithm is still the same as the one in the plain ML decoder version. The basic difference is that, instead of decoding all codeword bits by processing the ML decoding during N cycles, the proposed method stops intermediately in the third cycle, as illustrated in Fig. 3. If in the first three cycles of the decoding process, the evaluation of the XOR matrix for all {B j }is 0, the codeword is determined to be error-free and forwarded directly to the output. If the {B j }contain in any of the three cycles at least a 1, the proposed method would continue the whole decoding process in order to eliminate the errors. The additional hardware to perform the error detection is: i) the control unit which triggers a finish flag when no errors are detected after the third cycle and ii) the output tristate buffers. The output tristate buffers are always in high impedance unless the control unit sends the finish signal, so that the current values of the shift register are forwarded to the output. The control unit manages detection process. It uses a counter that counts upto three, which distinguishes the first three iterations of the ML decoding. In these first three iterations, the control unit evaluates {B j } the by combining them with the OR1 function. This value is fed into a three-stage shift register, which holds the results of the last three cycles. In the third cycle, the OR2 gate evaluates the content of the detection register. When the result is 0, the FSM sends out the finish signal indicating that the processed word is error-free. In the other case, if the result is 1, the ML decoding process runs until the end. III PROPOSED MSIC TPG This section develops a TPG scheme that can convert an SIC vector to unique low transition vectors, for multiple scan chains. First, the SIC vector is decompressed to its multiple codewords. Meanwhile, the generated codewords will bit-xor with a same seed vector in turn. Hence, a test pattern with similar test vectors will be applied to all scan chains. The proposed MSIC-TPG consists of an SIC generator, a seed generator, an XOR gate network, and a clock and control block. Fig. 3 Flow Diagram of the MLDD Algorithm A. Reconfigurable Johnson Counter For a short scan length, we develop a reconfigurable Johnson counter to generate an SIC sequence in time domain. it can operate in three modes. 1) Initialization: When RJ_Mode is set to 1 and Init is set to logic 0, the reconfigurable Johnson counter will be initialized to all zero states by clocking CLK2 more than l times. 2) Circular shift register mode: When RJ_Mode and Init are set to logic 1, each stage of the Johnson counter will output a Johnson codeword by clocking CLK2 l times. 3) Normal mode: When RJ_Mode is set to logic 0, the reconfigurable Johnson counter will generate 2l unique SIC vectors by clocking CLK2 2l times. IV RESULTS Thus the double bit error can be detected and corrected using this MLDD. The percentage of errors that can be detected with just one iteration has increased. The memory read access delay of the plain MLDD is code length independent. The MLDD version requires a much lower area overhead ranging from 10.16% to 0.43%. An important final comment is that the area overhead of the MLDD actually decreases with 67

4 N. Fig. 4. shows the output window for MLDD for double bit error correction. The DSCC code can be compared with the Hamming for the performance and the results are tabulated. The parameters compared are memory usage, time, number of LUT used, input buffer, output buffer, combinational path delay TABLE I Thus the TPG is generated and is checked using ISCAS 89 benchmark circuit. The MSIC sequences are generated and given to the TPG. The system can be used as a real time circuit. V. CONCLUSION A fault detection mechanism, MLDD, has been presented using the DSCCs. Simulation test results show that the proposed technique is able to detect double bit errors. This improves the performance of the design with respect to the traditional MLD approach. Area overhead is reduced compared with other approaches. Combined with the fault detection mechanism the proposed TPG with MSIC sequences can be easily generated. It could be easily implemented by hardware. The TPG can be tested by ISCAS 89 benchmark circuit. Analysis results show that an MSIC sequence had the favourable features of uniform distribution, low input transition density. The MSIC-TPG is scalable to scan length and has negligible impact on the test overhead. The generated MSIC sequences are given to the benchmark circuit and is verified with the LUT. Thus the output of LUT is then given to the MLDD for error correction. VI. REFERENCES [1] S.Lin and D.J.Costello, Error control coding,2 nd ed. Englewood Cliffs, NJ: Prentice- Hall, [2] I. S. Reed, A class of multiple-error-correcting codes and the decoding scheme, IRE Trans. Inf. Theory, vol. IT-4, pp , [3] J. L. Massey, Threshold Decoding. Cambridge, MA: MIT Press, [4] Y. Kato and T. Morita, Error correction circuit using difference-set cyclic code, in Proc. ASP-DAC, 2003, pp [5] T. Kuroda, M. Takada, T. Isobe, and O. Yamada, Transmission scheme of high capacity FM multiplex broadcasting system, IEEE Trans. Broadcasting, vol. 42, no. 3, pp , Sep [6] O. Yamada, Development of an error-correction method for data packet multiplexed with TV signals, IEEE Trans. Commun., vol. COM-35, no. 1, pp , Jan [7] H. Naeimi and A. DeHon, Fault secure encoder and decoder for NanoMemory applications, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 4, pp , Apr [8] S. Lin and D. J. Costello, Error Control Coding, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, [9] P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, J. Figueras, S. Manich, P. Teixeira, and M. Santos, Low-energy BIST design: Impact of the LFSR TPG parameters on the weighted switching activity, in Proc. IEEE Int. Symp. Circuits Syst., vol. 1. Jul. 1999, pp

5 [10] P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, A test vector inhibiting technique for low energy BIST design, in Proc. 17 th IEEE VLSI Test Symp., Apr. 1999, pp [11] S. Manich, A. Gabarro, M. Lopez, J. Figueras, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, P. Teixeira, and M. Santos, Low power BIST by filtering non-detecting vectors, J. Electron. Test.-Theory Appl., vol. 16, no. 3, pp , Jun [12] S. Manich, A. Gabarro, M. Lopez, J. Figueras, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, P. Teixeira, and M. Santos, Low power BIST by filtering non-detecting vectors, J. Electron. Test.-Theory Appl., vol. 16, no. 3, pp , Jun