A Quasi-Static Optoelectronic ATM Switch

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Cory Payne
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1 A Quasi-Static Optoelectronic ATM Switch (NSF Grant ) Polytechnic University

2 Project Objectives and Challenging Issues Objectives: Based on the concept of the path switching, we propose a multiterabit/s multicast ATM switch architecture that interconnects electronic switch modules with a quasi-static controlled optical interconnection network (OIN). Routing in the OIN is redetermined to avoid slot-by-slot processing and to provide flexible switching capacity on virtual path level. The surrounding electronic switch modules support multicasting, fast dynamic routing, and statistical multiplexing to compensate the quasi-static routing in the OIN to achieve totally a multi-terabit/s switching capacity. This quasi-static switching architecture simplifies the design of a multi-terabit/s ATM switch to specially featured 10 Gbit/s switch modules: the electronic multicast input and output modules and optical central interconnection, which are all feasible with existing technology. We will investigate several approaches of performing output contention resolution within multicast electronic switch modules: determine a cost-effective design for each approach, study the performance in terms of throughput, cell delay and loss rate, and finally identify the best approach that has high performance and feasible construction complexity. 03/10/2002 H. Jonathan Chao 2

3 WDM-ATM Multicast (3M) Switch 03/10/2002 H. Jonathan Chao 3

4 Photonic ATM Front-End Processor 03/10/2002 H. Jonathan Chao 4

5 Optical Shared Memory Switch Fabric and Route Controller 03/10/2002 H. Jonathan Chao 5

6 WDM Loop Memory 03/10/2002 H. Jonathan Chao 6

7 Cell Delineation Unit Objective: Identify cell boundary Methods of cell delineation The use of empty cells It could take some time before the next empty cell will appear The inserting of periodic cells Trade off between repeating rate and fast confirmation The inserting of simple pattern in every cell Unreliable The checking of the header error code (HEC) 03/10/2002 H. Jonathan Chao 7

8 Cell Format Cells back to back, no SONET frame structure Cell length = 64 bytes, arbitrarily chosen for experiment Guard time : Time reserved for compensating slow response of optical devices 03/10/2002 H. Jonathan Chao 8

9 Block Diagram of Cell Delineation Unit 03/10/2002 H. Jonathan Chao 9

10 VCI Overwrite Unit Objective: Replace VPI/VCI and HEC bytes optically Key components and functions VCI lookup table Maintain new header data in the memory (EPROMs) Parallel to serial converter Switching-controlling signal generator Generate a 6-bytes of pulse in every cell slot Control on-off of optical switch Optical devices Laser driver and DFB Diode Laser A 2x1 optical switch 03/10/2002 H. Jonathan Chao 10

11 Block Diagram of VCI Overwrite Unit 03/10/2002 H. Jonathan Chao 11

12 Cell Synchronization Unit Align optical ATM cells from different inputs to ¼bit resolution (100ps at 2.5 Gb/s line rate, or 2cm optical delay line) Align input cell streams to a reference cell clock Coarse synchronization circuit Use a high-speed 9-bit counter to adjust the phase difference between 1 to 511 bits Fine synchronization circuit Use sampling concept (each two samples apart by 100ps) to adjust the phase difference of 100, 200 or 300ps; i.e. ¼, ½, and ¾bit 03/10/2002 H. Jonathan Chao 12

13 Block Diagram of Cell Synchronization Unit 03/10/2002 H. Jonathan Chao 13

14 Fine Adjustment Circuit 03/10/2002 H. Jonathan Chao 14

15 Summary of Three PCB Characteristics 03/10/2002 H. Jonathan Chao 15

16 Route Controller Unit Objective: Control the loop memory for cell switching Methods of switching control: Treat wavelengths as memory units, then it behaves like a shared memory switch Maintaining two FIFOs to store wavelength IDs destined for each output port respectively Maintaining one FIFO to store idle wavelength IDs that can be allocated to input cells Wavelength IDs pulled out from output FIFOs are recycled back to idle wavelength FIFO for future use. 03/10/2002 H. Jonathan Chao 16

17 Route Controller Block Diagram R0&R1 Ref_Clk ECL - TTL Logic Conversion Ref_Clk (0V ~ +5V) Clock Synthesizer R0&R1 Cell_Clk HF_Clk Ouput 1 Ouput Idle Wavelength FIFO Pool Control State Machine Signal Delay Adjustment WC1[1..4] WC2[1..4] S[1..4] O[1..4] LVTTL - TTL Logic Conversion & Driver Laser Set #1 Control Laser Set #2 Control 1x2 Switch Control Ouput Port Control Delay Adjustment Control Reg_clk Reg_Addr Reg_Val Clock Manag ement Delay Register File FPGA FGPA Confuguration 03/10/2002 H. Jonathan Chao 17

18 Route Controller Board Picture Route Controller 03/10/2002 H. Jonathan Chao 18

19 Testing Setup of Cell Delineation & VCI Overwrite Units 03/10/2002 H. Jonathan Chao 19

20 Cell Delineation & VCI Overwrite Units Setup Picture 03/10/2002 H. Jonathan Chao 20

21 Optical Setup for 2x2 Loop Switch WC1_1 LD <?1> Data_in 1 Data_in 2 Tunable DC Bias Sampling Ocilliscope O/E WC1_2 WC1_3 WC1_4 LD <?2> LD <?3> LD <?4> Coupler 4x1 Coupler Modulator Modulator CPL 2x1 Coupler 2x2 Coupler Fiber Delay Line Coupler 4x1 Coupler Data_out 1 Attenuator Tunable Attenuator & Power Monitor AWG Wavelength Splitter WC2_1 WC2_2 WC2_3 WC2_4 LD <?1> LD <?2> LD <?3> LD <?4> Coupler 4x1 Coupler EDFA Optical Amplifier WDM LOOP Coupler 4x1 Coupler?1?2?3?4 1x2 Switch 1x2 Switch 1x2 Switch 1x2 Switch Coupler 4x1 Coupler Data_out 2 Electrical Signal Optical Signal 03/10/2002 H. Jonathan Chao 21

22 Optical Setup Picture I VCI Overwriting 03/10/2002 H. Jonathan Chao 22

23 Optical Setup Picture II 2x2 Loop Switch 03/10/2002 H. Jonathan Chao 23

24 Optical Setup Picture III Wavelength Converter 03/10/2002 H. Jonathan Chao 24

All-optical Write/Read Memory for 20 Gb/s Data Packets

All-optical Write/Read Memory for 20 Gb/s Data Packets M. Kalyvas, C. Bintjas, K. Zoiros, T. Houbavlis, H. Avramopoulos, L. Occhi, L. Schares, G. Guekos, S. Hansmann and R. Dall Ara We demonstrate a writeable