EECS 140 Laboratory Exercise 7 PLD Programming

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1 1. Objectives EECS 140 Laboratory Exercise 7 PLD Programming A. Become familiar with the capabilities of Programmable Logic Devices (PLDs) B. Implement a simple combinational logic circuit using a PLD. The circuit you will design and implement for this laboratory will output on a 7-segment display, a sequence of the letters KU followed by a space and then the digits forming your KUID. For example, if your KUID number were , then your circuit should repeatedly produce the sequence KU_ on the 7-segment display. The _ represents a space in the sequence where no segments on the display are driven. During the first week of this laboratory, you will become familiar with how to map a simple combinational logic circuit into a PLD and how to program the PLD. During the second week of this laboratory, you will implement and test a logic circuit using a PLD. 2. Discussion In this exercise you will implement a simple combinational circuit using a PLD rather than the discrete gates used in the previous lab. Remember the steps outlined for performing a top down design that were discussed in Lab 5. Whether you are planning on implementing your circuit using discrete gates (AND, OR, NAND, NOR gates) or a PLD, your approach to developing your design should remain the same. You should first perform your requirements analysis to understand what you are being asked to design. Then you should progress into your top level design, and through detailed design and test. You should still use the basic tools you have learned for performing a design, including specifying your system in a truth table, and using techniques for minimizing your design. Where do you think any differences will appear in the design flow if you are using a PLD instead of discrete gates to implement your circuit? In terms of our structured design approach, you will be given the top level design and will be required to finish the detailed design. The top level design consists of the oscillator from your second laboratory, the 4 bit binary counter from your third laboratory, an EPLD (Erasable PLD), and the 7-segment display you implemented in your previous lab. Because EPLDs can be erased and re-programmed many times, you don't have to be perfect the first time! You will perform a detailed design for a collection of seven functions, with each individual function responsible for driving an individual segment on the 7-segment display. To generate the seven functions, you must first determine what input values to the 7-segment display produce the character you wish to see for each of the counter outputs.. Considering the earlier example, KU_295331, the counter output 0000 should cause the display to produce a K. The counter output 0001 should cause the display to produce U, the output 0010 a blank output, the output 0011 the first number of your ID (2 in the example), 0100 the second (9 in the example), and so forth. You will learn what inputs are associated with each segment and how to drive them later in this report. You should proceed through your design

2 steps for each individual function just as you have for previous circuits. Specifically, you will generate a 4 variable truth table for each of the seven driver functions using the outputs of the counter as the inputs for each function. Note that you only care about counter outputs from 0 through 9, as only 10 symbols will be output on the display. You may be able to simplify your circuit by using don t cares for outputs 10 through 15. Because you only need the first 10 values, remember to design your circuit to have the counter return to 0 after the value 9 is output. Hint* consider using the RESET input on the counter. You will be using two new components that you have not utilized in Lab before. The first is a PLD. Specifically, you will be provided with a GAL22V10 family programmable logic device. You will use this device to implement the circuits that: (i) drive the 7-segment display inputs; and (ii) modify the counter to run from 0 to 9. The second is a 7-segment display that allows you to display characters and numbers using a single character display package. These devices are described in the following sections. 2.1 The GAL22V10 Family The EPLD you will use is a GAL22V10, a PAL22V10 or another device in the 22V10 series. All are pin compatible (meaning that the pinouts are identical), but the EPLD programming tool treats each device differently. Thus, from this point forward, we will only describe the implementation using a GAL22V10. The GAL22V10 has 10 input pins, 11 pins that can be inputs or outputs, and one pin that can be used as a clock or 22nd input. TheGAL22V10 pinouts are shown in Figure 1 and the circuit diagram of the GAL22V10 is shown in Figure 2. The GAL22V10 is a PAL (Programmable Array Logic), thus product terms are hardwired to OR gates for each output. You specify the product terms for each output, but the number of product terms and their sum is fixed. Note the GAL22V10 has some devices in its output circuit called flip-flops. We'll not be using the flip-flops in this design. Figure 1: Pinouts of the GAL22V10.

3 Figure 2: The logic diagram of the GAL22V10. The GAL22V10 is a programmable logic device (PLD). That means you write a short description of the logic you want to implement, translate the description to a "bit file", and then using a hardware programmer transfer your bit file to the actual device. You then plug your device into your circuit for testing. Section 2.3 describes how you write the description file and program your device. Note that the GAL22V10 is a CMOS circuit that is very sensitive to static electricity. Your GAL22V10 will be given to you pushed into a black foam sponge. This sponge is conductive and prevents a static

4 charge from building up on the device's pins. You should keep your GAL22V10 in this foam unless you are moving it to or from the programmer, or inserting it into or removing it from your circuit. 2.2 The 7-Segment Display The second new component you will use in this exercise is a seven-segment display. The sevensegment display had seven LEDs (light emitting diodes) arranged in a squared-off figure eight. By lighting different combinations of LEDs, the ten digits 0-9 and a few alphanumeric characters can be displayed. Figure 4 shows the arrangement of the LEDs in a seven -segment display and the pin-outs of the display. A (1) F (2) G (11) B (13) E (7) D (8) C (10) Figure 4: The arrangement of the LEDs in a 7-segment display and the associated pin-outs. The segments are labeled A through G respectively. Pins 1,2,7,8,10,11 and 13 are used to drive the various LED segments. Unfortunately, the numeric ordering of pins and the names of segments do not correspond. Segment A corresponds to Pin 1 and segment B to Pin 13, while segment F corresponds to Pin 2. Pins 3 and 14 are connected to the +5 VDC power supply and provide power to drive the LEDs. Pin 9 is connected to a decimal point that we will not use. Pins 4, 5, 6, and 12 are not used by the package and can be ignored. To illuminate a segment of the LED, you need to set the pin to a low voltage. Because a low voltage turns a segment on, the inputs are considered negative logic. Remember that VDC is at +5 volts. By setting the pin associated with a segment to a low voltage, current flows from the higher voltage, through the LED, to the low voltage causing the LED to light up. Assuming that we want the number 5 to appear on the display in Figure 4, we need segments A, F, G, C and D to be driven. Thus, we would set pins 1,2,8,10 and 11 to low voltage and pins 7 and 13 to high voltage. If we want the letter K to be displayed, we would need segments F, G, B, E, and C to be driven. Thus, we set pins 2,7,10, 11, and 13 to low voltages and 1 and 8 to high voltages. To design a circuit to drive a 7-segment display, you must specify a function for each of the 7 segments. Each of the segment pins will be connected to the GAL22V10 outputs. So, to turn segments on and off, you will generate appropriate outputs from the GAL22V10. If a low voltage is needed to turn on a segment, then a 0 is output. If a high voltage is needed to turn off a segment, then a 1 is output. All segments will be connected to the GAL22V10 outputs through 270 resistors to limit the amount of current that flows through the seven-segment display. Inserting appropriate shorting jumpers achieves this interconnection. If you are uncertain how to set your jumpers, please ask your TA for assistance. Remember that V=IR and if the resistance is low, a great deal of current is needed to produce the

5 voltage drop. With the current limiting resistors, the current needed is lessened. Be careful not to use too much resistance as more current flowing through a segment produces a brighter output. 2.3 PLD Design File Format You will use Intel's PLDasm tool to specify your design and program your GAL22V10 device. PLDasm is intuitive and simple to use, so only the basics will be discussed here. Your TA will provide additional details, and manuals are available in the lab. You can/should create files ahead of time, but you must save your files in a text only, line delimited format. This means that if you use Word or another formatting editor, you must save the resulting file in text only format. The PLDasm expects an extension of "PDS" for files that you want to program your PLD with. So, a filename such as PRIME.PDS would be an appropriate name for the instructions to program the PLD to perform the function from the prime number recognition lab. Most of the PLDasm file follows the keyword/value format. Specifically, each line of the program will be a keyword followed by a value for that keyword. The header of the file looks like the following: Title Prime Number Recognizer Pattern pds Revision 1.0 ; for your first try, comments after ";" Author Gary Minden ; The person to call when there is trouble Company Univ of Kansas ; Well, use "University of Kansas" for now Date CHIP ID Output 22V10 ; Check with you TA for the exact chip code to put here. In this header, the keyword Title is associated with the value Prime Number Recognizer, the keyword Pattern is associated with pds, and so forth. Note that the special keyword CHIP is used to identify the type of chip being programmed. We use several variants of the GAL22V10, so it is important that you find out from your TA what chip you are actually using. Failure to enter the correct chip ID will result in a failure to load your circuit description into the device. The next step in writing your file is to specify the pins that you will use. An example to consider is: Pin 1 Clk ; Clock Pin Pin 2 QD ; MSB of counter Pin 3 QC ; next MSB of counter Pin 4 QB ; next LSB of counter Pin 5 QA ; LSB of counter Pin 23 C9 ; Active low on count 9 What we are doing is associating a variable name with the pins that serve as inputs and outputs for the device. For example, the second line of the specification associates pin 2 with the name QD, which will be connected to the MSB of the counter. At this point we would also specify the outputs that drive the seven-segment display by identifying the associated pin and providing a name for the pin. It is wise to name your signals meaningfully, such as using SegA, SegB, etc to name the pins driving the segments

6 of the display. Remember, the seven-segment display is negative logic, thus the / character should appear prior to the variable name. Next you can specify your Boolean equations. This is easy, but there is a specific syntax. For example, if we wanted to implement a function to recognize the value 11 in the counter and output the result on the pin associated with C9, we would state: EQUATIONS C9 = QD * /QC * /QB * QA ; C9 is True when QD..QA is 1001 This equation states that the value output on C9 is equivalent to QD and not QC and not QB and QA. The equations are the same equations that result from your K-map simplification. We are simply using a different format to specify negation, XOR and some other operations. Your EPLD programmer will figure out how to implement the function using its logic elements. Thus, you need only provide the function to the EPLD programming environment. We will write equations similar to this one for each of the outputs that drive 7-segment display and the output that resets the counter after 9 is output. Remember that any text appearing after a ; is a comment and is not encoded by the PLD programming environment. The equation syntax uses the following notation for various logical operations. * An asterisk indicates an AND Boolean function + A plus indicates an OR Boolean function / A slash indicates the complement of a variable. :+: Indicates the XOR Boolean function = An equal sign indicated a combinatorial output := Indicates the result will be held in a flip-flop in the output macro-cell. You should not need this operator for this design. Note that the / operation is used for negation and that :+: is exclusive or. Most other symbols are the same as those we normally use in class. To indicate an active low output you can either put a slash before the output signal name as in: Pin 22 /SegA ; Segment A output Or you can put a slash before the output signal in the Boolean expression as in: /SegA = QA + /QB ; Don't trust this expression, it is made up! You will need one equation for each desired output. As mentioned earlier, this includes each of the seven segments and the RESET input on the counter. You will design and specify a total of eight different circuits.

7 Note that you are not specifying how each equation is implemented. The programming software determines what components on the GAL22V10 should be used to implement the function and sets up the connections automatically. This is much simpler and requires far less time than selecting components and connecting pins. Further, because the GAL22V10 is re-programmable, you needn t get the circuit perfect the first time. You can enter and try many circuit combinations to find the correct combination for your problem. Each output of the GAL22V10 that you use in your implementation must be enabled. If the outputs are not enabled, the results of your circuit s calculations will not appear on the output pins. To enable the SegA output you would enter: SegA.TRST = 1 ; Enable the SegA output Where SegA is the output variable name and the suffix.trst indicates that we are defining when the output is enabled. Sometimes it is useful to enable an output based on a logic function. However, that is a subject for a later lab. In this case, all our outputs are always enabled. Thus, we use the constant 1 as the enabling equation. Thus, for each output variable to your display or another circuit, you must include a line similar to the previous command to enable outputs. A complete file that would combine your prime number recognizer and your recognize 11 circuit might look like the following: Title Prime number recognizer Pattern pds Revision 1.0 ; for your first try, comments after ";" Author G. Minden ; The person to call when there is trouble Company EECS 140; Well, use "University of Kansas" for now Date CHIP 22V10 ; Check with you TA for the exact chip code to put here. Pin 1 Clk ; Clock Pin Pin 2 QD ; MSB of counter Pin 3 QC ; next MSB of counter Pin 4 QB ; next LSB of counter Pin 5 QA ; LSB of counter Pin 23 /C11 ; Active low on count 11 Pin 22 Prime ; Active high on prime number EQUATIONS C11 = QD * /QC * QB * QA ; C11 is True when QD..QA is 1011 Prime = /QD * QA + QC * /QB * QA + /QD * /QC * QB + /QC * QB * QA

8 3. Tasks Week 1: In the first week you should design your combinational logic circuit, prepare you design files, and figureout the resistor and capacitor values needed to set your oscillator to about 1 Hz. You should have previously inserted and soldered most of the IC sockets, resistors, and wire-wrap pins. Step 1 Design your logic circuit. The inputs to your logic circuit will be the four outputs of your counter. The outputs of your logic circuit will be the signals to drive the seven-segment display and a signal to reset the counter to a value of zero (0). Remember, that the seven-segment display expects negative logic inputs, that is, to light a display segment, you must bring the pin associated with the segment to a low value. 1. Generate a truth table that specifies the driving function for each of the 7 display segments. Do this by determining which segments must be driven in response to each counter state. Remember to use don t cares in your truth tables to facilitate simplification later. 2. Generate a truth table that specifies the function necessary to cause your counter to repeatedly run from 0 to 9. Use the same technique used in the 3 to 11 counter to achieve this goal. Note that you may want to use the RESET input on the counter rather than the LOAD input to load a constant 0. Both will work, but using RESET may save you some implementation time. If you use RESET, make certain you pull up LOAD to +5 VDC to make certain you will never load a new initial value from A through D. 3. From the truth tables, generate a sum-of-products expression for each of the segments and, if necessary, the 0 to 9 counter modification circuit. Simplify your function using Boolean algebra simplification techniques or Karnaugh maps. 4. Convert your design to the PLD Design format described in Section 2.3. Save your design description in a text only file on a PC-DOS floppy. Step 2 - Design your RC time constant circuit for your oscillator. Select a resistor and capacitor for each of the multivibrators in your oscillator to obtain a 1 Hz (approximate) clock. To obtain a 1 Hz clock, each multivibrator needs to output a 500 ms pulse. Use the following equation to determine approximate resistor and capacitor values: The equation used to determine the pulse width of a 74LS123 is: Where: Tw = 0.45 x Rt x Cext

9 Tw is in nanoseconds Rt is in KiloOhms (e.g. your 7.5 K resistor is 7.5) Cext is in pf (e.g. your "223" capacitor is 22,000 pf) Note, this is an updated equation than the one presented in Exercise 2. You should consider capacitors in the range of 5 µf to 30 µf and resistors in the range of 40 k k. Capacitors in this value range are generally of a type called electrolytic and electrolytic capacitors are polarized. That is, they have a positive terminal and a negative terminal. The negative terminal is usually marked with a "-" sign or a heavy bar. The negative terminal should be inserted toward the bottom of your board. It is extremely important that you insert electrolytic capacitors into your board correctly. If you do not, they may burn out or explode. Have your TA check before you solder you electrolytic capacitors into place. Week 2: Step 3 - Modify your oscillator Obtain the necessary capacitors and resistors from the EECS Shop to modify your oscillator to operate at 1 Hz. When asking for parts from the Shop, you must be specific in the parts you ask for. Insert the new parts in the third position for RC components. Remove any previous wiring and connect your new components. Verify the frequency of your oscillator with the oscilloscope. Step 4 - Program your GAL22V10 device. Obtain a GAL22V10 and seven-segment display from the EECS Shop. Your TA will show you how to run the PLD Design tool and program your GAL22V10. Make sure you bring your floppy with your design to lab. After programming your device verify its correct operation. Insert the GAL22V10 in your circuit along with the seven-segment display. Make sure all jumpers are in their correct position. Remember to consult with your TA if you aren t sure about jumper positions and settings. Demonstrate your circuit to the TA. Step 5 - Write your lab report Write your lab report per instructions from you TA. In your lab report, make certain to explain the advantages of using the PLD over using 2 level logic as we did with the prime number recognizer. Also explain any disadvantages, should they exist.