Design Example: Demo Display Unit
|
|
- Lewis Anderson
- 6 years ago
- Views:
Transcription
1 Design Example: Demo Display Unit Say we are given an arrangement of 8 LEDs in a diamond pattern, with the LED labelled 7 at the top of the diamond, then numbered down to 0 in the clockwise direction. (See diagram). We are told that the following behaviour is desired. When the START button is pressed, the system displays on the LEDs (that is, LED 7 is lit, and all the rest are off). On every clock pulse, the LED to the left of the current lit LED lights up, and the LED that was lit is turned off. Thus, the LEDs are lit one at a time, in a counterclockwise direction. This continues until 11 clock cycles have passed, or until the user presses the REVERSE button. Then the LEDs are lit one at a time, moving now in the clockwise direction, until 11 clock cycles have passed, or until the user presses the REVERSE button. Then, the LED starts moving counterclockwise again. This process of moving counterclockwise, then clockwise, then counterclockwise, and so on continues until the user presses STOP, at which time the LEDs state however they were when STOP was pressed. This sort of display might be used in a gadget or toy as some kind of fancy display. Or, alternately, if the clock is fast enough, it might serve as a sort of randomizer. (In reality, this is a pretty contrived example, but a useful one). So we consider our overall system. As always, we break things up into control and datapath. The inputs to the controller consist of the top-level system inputs START, STOP, and REVERSE. The LEDs are driven by the datapath. At this point, we don t know enough about the datapath to determine what kind of signals we need between the controller and datapath. Copyright 2003 by Andrew W. H. House Page 1 of 7
2 So we must now design the datapath. Datapath Well, the behaviour of the system is such that it involves lighting up adjacent LEDs in either the left or right directions. Visually, it appears as if the lit LEDs is moving around the circle. We know of a basic component that allows bits to move to adjacent locations the shift register. So we can conclude that we probably need an 8-bit universal shift register. The shift register will load to the desired patter when START is pressed, then shift either left or right to emulate the lit LED moving counterclockwise or clockwise. Not that to do this successfully, we need to hook up the least significant output of the shift register to the SIR (shift-in-right) input, and the most significant output to the SIL (shift-in-left) input to allow the bit to wrap around. We can build our 8-bit shift register out of two devices, or just assume it exists (see multiplier example). The shift register operation is set by the controller. The LEDs are driven directly by the outputs of the shift register. We also have to count until 11. This suggests a counter. A 4-bit counter will be sufficient. Because the counter starts counting at zero, we actually check to see when the counter has reached 10 before reloading. The loading of the counter to zeroes is controlled by the state machine. The outputs of the counter are used to send a signal to the controller as to how many clock cycles have passed. The datapath is fully drawn in the diagram on the next page. Copyright 2003 by Andrew W. H. House Page 2 of 7
3 Copyright 2003 by Andrew W. H. House Page 3 of 7
4 With the datapath designed, we can complete our top level diagram to show the communication between the controller and datapath. Controller Now we can design the controller for our system, since we know its inputs (START, STOP, REVERSE, CLK_11) and its outputs (S0, S1, and LOAD_CNT). We will start in an IDLE state. We can specify that this state holds the output to whatever it currently is, since nothing in our original specification said what the LEDs displayed before START is pressed. When START is pressed, we must load the counter, load the initial pattern into the shift register, and start shifting left until CLK_11 is high or REVERSE is high. Then, we start shifting right until CLK_11 is high or REVERSE is high, and so on. If STOP is pressed at any time after leaving the idle state, we return to idle on the next clock edge. The ASM chart for this algorithm is on the next page. Because there are only three states, and for the sake of a bit of variety from the other examples we ve covered in class, we will use one-hot design. Hence, we need three flip-flops to store the state variables: C k, B k, and A k. We will map the IDLE state to 001, LEFT to 010, and RIGHT to 100. Copyright 2003 by Andrew W. H. House Page 4 of 7
5 Copyright 2003 by Andrew W. H. House Page 5 of 7
6 From the ASM chart we can write the state sequences: Current State C k B k A k Next State C k+1 B k+1 A k+1 Conditions IDLE 001 IDLE 001 START LEFT 010 START LEFT 010 LEFT RIGHT CLK_11) IDLE 001 STOP RIGHT 100 RIGHT LEFT CLK_11) IDLE 001 STOP C k+1 = + CLK_11) = + CLK_11) + @REVERSE B k+1 = IDLE@START + + CLK_11) = A + @REVERSE + + CLK_11) A k+1 = IDLE@START + LEFT@STOP + RIGHT@STOP = A + STOP@(B k + C k ) The outputs can also be determined. S0 = IDLE@START + LEFT = A + B k S1 = IDLE@START + RIGHT = A + C k LOAD_CNT = IDLE@START + + CLK_11) + + CLK_11) = A + + CLK_11) + + CLK_11) We have reached the point where we can implement using 3 D-type flip-flops and basic logic gates. Copyright 2003 by Andrew W. H. House Page 6 of 7
7 Class notes by Andrew W. H. House, 02 December Copyright 2003 by Andrew W. H. House Page 7 of 7
Introduction. Serial In - Serial Out Shift Registers (SISO)
Introduction Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group of flip-flops connected in a chain so that the output from one flip-flop becomes
More informationRegister Transfer Level in Verilog: Part II
Source: M. Morris Mano and Michael D. Ciletti, Digital Design, 4rd Edition, 2007, Prentice Hall. Register Transfer Level in Verilog: Part II Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National
More informationAsynchronous (Ripple) Counters
Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory. The chapter about flip-flops introduced
More informationWe are here. Assembly Language. Processors Arithmetic Logic Units. Finite State Machines. Circuits Gates. Transistors
CSC258 Week 5 1 We are here Assembly Language Processors Arithmetic Logic Units Devices Finite State Machines Flip-flops Circuits Gates Transistors 2 Circuits using flip-flops Now that we know about flip-flops
More informationCounter dan Register
Counter dan Register Introduction Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory.
More informationSequencing and Control
Sequencing and Control Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Spring, 2016 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Source:
More informationLogic Design. Flip Flops, Registers and Counters
Logic Design Flip Flops, Registers and Counters Introduction Combinational circuits: value of each output depends only on the values of inputs Sequential Circuits: values of outputs depend on inputs and
More informationELCT 501: Digital System Design
ELCT 5: Digital System Lecture 8: System Dr. Mohamed Abd El Ghany, Algorithmic State Machine (ASM) For large machines, the designers often use a different form of representation, called the algorithmic
More informationAdministrative issues. Sequential logic
Administrative issues Midterm #1 will be given Tuesday, October 29, at 9:30am. The entire class period (75 minutes) will be used. Open book, open notes. DDPP sections: 2.1 2.6, 2.10 2.13, 3.1 3.4, 3.7,
More informationCounters
Counters A counter is the most versatile and useful subsystems in the digital system. A counter driven by a clock can be used to count the number of clock cycles. Since clock pulses occur at known intervals,
More informationModeling Digital Systems with Verilog
Modeling Digital Systems with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 6-1 Composition of Digital Systems Most digital systems can be partitioned into two types
More informationCSE Latches and Flip-flops Dr. Izadi. NOR gate property: A B Z Cross coupled NOR gates: S M S R Q M
CSE-4523 Latches and Flip-flops Dr. Izadi NOR gate property: A B Z A B Z Cross coupled NOR gates: S M S R M R S M R S R S R M S S M R R S ' Gate R Gate S R S G R S R (t+) S G R Flip_flops:. S-R flip-flop
More informationState Transistional Logic
State Transistional Logic S-R Flip Flops One way to describe how a didital system operates is to define a set of states. For example, a stoplight might have three states: Green Yellow Red The heart of
More informationDigital Design Datapath Components: Parallel Load Register
ECE 274 - Digital Logic Lecture Datapath Components: Processor: Controller + Datapath Lecture Parallel Load Register Shift Registers Multifunction Registers Multifunction Register Design Process Controller
More informationFigure 30.1a Timing diagram of the divide by 60 minutes/seconds counter
Digital Clock The timing diagram figure 30.1a shows the time interval t 6 to t 11 and t 19 to t 21. At time interval t 9 the units counter counts to 1001 (9) which is the terminal count of the 74x160 decade
More informationCSE115: Digital Design Lecture 23: Latches & Flip-Flops
Faculty of Engineering CSE115: Digital Design Lecture 23: Latches & Flip-Flops Sections 7.1-7.2 Suggested Reading A Generic Digital Processor Building Blocks for Digital Architectures INPUT - OUTPUT Interconnect:
More informationFinal Exam review: chapter 4 and 5. Supplement 3 and 4
Final Exam review: chapter 4 and 5. Supplement 3 and 4 1. A new type of synchronous flip-flop has the following characteristic table. Find the corresponding excitation table with don t cares used as much
More informationControl Unit. Arturo Díaz-Pérez Departamento de Computación Laboratorio de Tecnologías de Información CINVESTAV-IPN
Control Unit Arturo Díaz-Pérez Departamento de Computación Laboratorio de Tecnologías de Información CINVESTAV-IPN Large Digital Systems In both combinational and sequential circuit design: small circuits
More informationSequential Digital Design. Laboratory Manual. Experiment #7. Counters
The Islamic University of Gaza Engineering Faculty Department of Computer Engineering Spring 2018 ECOM 2022 Khaleel I. Shaheen Sequential Digital Design Laboratory Manual Experiment #7 Counters Objectives
More informationLogic. Andrew Mark Allen March 4, 2012
Logic Andrew Mark Allen - 05370299 March 4, 2012 Abstract NAND gates and inverters were used to construct several different logic gates whose operations were investigate under various inputs. Then the
More informationThe basic logic gates are the inverter (or NOT gate), the AND gate, the OR gate and the exclusive-or gate (XOR). If you put an inverter in front of
1 The basic logic gates are the inverter (or NOT gate), the AND gate, the OR gate and the exclusive-or gate (XOR). If you put an inverter in front of the AND gate, you get the NAND gate etc. 2 One of the
More informationLSN 12 Shift Registers
LSN 12 Shift Registers Department of Engineering Technology LSN 12 Shift Registers Digital circuits with data storage and data movement functions Storage capacity is the total number of bits of digital
More informationLogic Design II (17.342) Spring Lecture Outline
Logic Design II (17.342) Spring 2012 Lecture Outline Class # 03 February 09, 2012 Dohn Bowden 1 Today s Lecture Registers and Counters Chapter 12 2 Course Admin 3 Administrative Admin for tonight Syllabus
More informationUNIT III. Combinational Circuit- Block Diagram. Sequential Circuit- Block Diagram
UNIT III INTRODUCTION In combinational logic circuits, the outputs at any instant of time depend only on the input signals present at that time. For a change in input, the output occurs immediately. Combinational
More informationFirst Name Last Name November 10, 2009 CS-343 Exam 2
CS-343 Exam 2 Instructions: For multiple choice questions, circle the letter of the one best choice unless the question explicitly states that it might have multiple correct answers. There is no penalty
More informationUniversity of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science SOLUTIONS
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science EECS 5 Fall 25 R. H. Katz SOLUTIONS Problem Set #3: Combinational and Sequential Logic
More informationENGG 1203 Tutorial. D Flip Flop. D Flip Flop. Q changes when CLK is in Rising edge PGT NGT
ENGG 1203 Tutorial D Flip Flop Sequential Logic 14/21 Feb Learning Objectives Design circuits with Flip Flop Design a finite state machine News Feb 27, 2014, 11:55pm Ack.: HKU ELEC1008, ISU CprE 281x,
More informationComputer Systems Architecture
Computer Systems Architecture Fundamentals Of Digital Logic 1 Our Goal Understand Fundamentals and basics Concepts How computers work at the lowest level Avoid whenever possible Complexity Implementation
More informationCprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Registers and Counters CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
More informationEET 1131 Lab #10 Latches and Flip-Flops
Name OBJECTIVES: 1. To study the operation of a D latch. 2. To study the operation of a D flip-flop. 3. To study the operation of a J-K flip-flop. EQUIPMENT REQUIRED: Safety glasses ICs: 7474, 7475, 74LS76
More informationRegisters and Counters
Registers and Counters Clocked sequential circuit = F/Fs and combinational gates Register Group of flip-flops (share a common clock and capable of storing one bit of information) Consist of a group of
More informationCSE 352 Laboratory Assignment 3
CSE 352 Laboratory Assignment 3 Introduction to Registers The objective of this lab is to introduce you to edge-trigged D-type flip-flops as well as linear feedback shift registers. Chapter 3 of the Harris&Harris
More information1. Convert the decimal number to binary, octal, and hexadecimal.
1. Convert the decimal number 435.64 to binary, octal, and hexadecimal. 2. Part A. Convert the circuit below into NAND gates. Insert or remove inverters as necessary. Part B. What is the propagation delay
More informationDigital Logic Design ENEE x. Lecture 24
Digital Logic Design ENEE 244-010x Lecture 24 Announcements Homework 9 due today Thursday Office Hours (12/10) from 2:30-4pm Course Evaluations at the end of class today. https://www.courseevalum.umd.edu/
More informationLogic Design II (17.342) Spring Lecture Outline
Logic Design II (17.342) Spring 2012 Lecture Outline Class # 05 February 23, 2012 Dohn Bowden 1 Today s Lecture Analysis of Clocked Sequential Circuits Chapter 13 2 Course Admin 3 Administrative Admin
More informationExperiment # 9. Clock generator circuits & Counters. Digital Design LAB
Digital Design LAB Islamic University Gaza Engineering Faculty Department of Computer Engineering Fall 2012 ECOM 2112: Digital Design LAB Eng: Ahmed M. Ayash Experiment # 9 Clock generator circuits & Counters
More informationDigital 1 Final Project Sequential Digital System - Slot Machine
Digital 1 Final Project Sequential Digital System - Slot Machine Joseph Messner Thomas Soistmann Alexander Dillman I. Introduction The purpose of this lab is to create a circuit that would represent the
More informationSequential Logic Counters and Registers
Sequential Logic ounters and Registers ounters Introduction: ounters Asynchronous (Ripple) ounters Asynchronous ounters with MOD number < 2 n Asynchronous Down ounters ascading Asynchronous ounters svbitec.wordpress.com
More informationExperiment 8 Introduction to Latches and Flip-Flops and registers
Experiment 8 Introduction to Latches and Flip-Flops and registers Introduction: The logic circuits that have been used until now were combinational logic circuits since the output of the device depends
More informationEECS150 - Digital Design Lecture 19 - Finite State Machines Revisited
EECS150 - Digital Design Lecture 19 - Finite State Machines Revisited April 2, 2013 John Wawrzynek Spring 2013 EECS150 - Lec19-fsm Page 1 Finite State Machines (FSMs) FSM circuits are a type of sequential
More informationOutcomes. Spiral 1 / Unit 6. Flip-Flops FLIP FLOPS AND REGISTERS. Flip-flops and Registers. Outputs only change once per clock period
1-6.1 1-6.2 Outcomes Spiral 1 / Unit 6 Flip-flops and Registers I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at
More informationCprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Registers and Counters CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
More informationAdvanced Devices. Registers Counters Multiplexers Decoders Adders. CSC258 Lecture Slides Steve Engels, 2006 Slide 1 of 20
Advanced Devices Using a combination of gates and flip-flops, we can construct more sophisticated logical devices. These devices, while more complex, are still considered fundamental to basic logic design.
More informationIntroduction. NAND Gate Latch. Digital Logic Design 1 FLIP-FLOP. Digital Logic Design 1
2007 Introduction BK TP.HCM FLIP-FLOP So far we have seen Combinational Logic The output(s) depends only on the current values of the input variables Here we will look at Sequential Logic circuits The
More informationMASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences
MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences Introductory Digital Systems Lab (6.111) Quiz #2 - Spring 2003 Prof. Anantha Chandrakasan and Prof. Don
More informationUsing minterms, m-notation / decimal notation Sum = Cout = Using maxterms, M-notation Sum = Cout =
1 Review of Digital Logic Design Fundamentals Logic circuits: 1. Combinational Logic: No memory, present output depends only on the present input 2. Sequential Logic: Has memory, present output depends
More informationASYNCHRONOUS COUNTER CIRCUITS
ASYNCHRONOUS COUNTER CIRCUITS Asynchronous counters do not have a common clock that controls all the Hipflop stages. The control clock is input into the first stage, or the LSB stage of the counter. The
More informationVTU NOTES QUESTION PAPERS NEWS RESULTS FORUMS Registers
Registers Registers are a very important digital building block. A data register is used to store binary information appearing at the output of an encoding matrix.shift registers are a type of sequential
More informationSynthesis Technology E102 Quad Temporal Shifter User Guide Version 1.0. Dec
Synthesis Technology E102 Quad Temporal Shifter User Guide Version 1.0 Dec. 2014 www.synthtech.com/euro/e102 OVERVIEW The Synthesis Technology E102 is a digital implementation of the classic Analog Shift
More informationSerial In/Serial Left/Serial Out Operation
Shift Registers The need to storage binary data was discussed earlier. In digital circuits multi-bit data has to be stored temporarily until it is processed. A flip-flop is able to store a single binary
More informationComputer Organization & Architecture Lecture #5
Computer Organization & Architecture Lecture #5 Shift Register A shift register is a register in which binary data can be stored and then shifted left or right when a shift signal is applied. Bits shifted
More informationUnit 11. Latches and Flip-Flops
Unit 11 Latches and Flip-Flops 1 Combinational Circuits A combinational circuit consists of logic gates whose outputs, at any time, are determined by combining the values of the inputs. For n input variables,
More informationUniversal Asynchronous Receiver- Transmitter (UART)
Universal Asynchronous Receiver- Transmitter (UART) (UART) Block Diagram Four-Bit Bidirectional Shift Register Shift Register Counters Shift registers can form useful counters by recirculating a pattern
More informationRegisters and Counters
Registers and Counters Clocked sequential circuit = F/Fs and combinational gates Register Group of flip-flops (share a common clock and capable of storing one bit of information) Consist of a group of
More informationSequential Logic Notes
Sequential Logic Notes Andrew H. Fagg igital logic circuits composed of components such as AN, OR and NOT gates and that do not contain loops are what we refer to as stateless. In other words, the output
More informationModule 4:FLIP-FLOP. Quote of the day. Never think you are nothing, never think you are everything, but think you are something and achieve anything.
Module 4:FLIP-FLOP Quote of the day Never think you are nothing, never think you are everything, but think you are something and achieve anything. Albert Einstein Sequential and combinational circuits
More informationFlip-Flops and Sequential Circuit Design
Flip-Flops and Sequential Circuit Design ECE 52 Summer 29 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6
More informationUniversity of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science. EECS 150 Spring 2000
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science EECS 150 Spring 2000 Lab 2 Finite State Machine 1 Objectives You will enter and debug
More informationD Latch (Transparent Latch)
D Latch (Transparent Latch) -One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that inputs S and R are never equal to 1 at the same time. This is done
More informationUniversity of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science EECS 150 Fall 2000 Original Lab By: J.Wawrzynek and N. Weaver Later revisions by R.
More informationRegisters. Unit 12 Registers and Counters. Registers (D Flip-Flop based) Register Transfers (example not out of text) Accumulator Registers
Unit 2 Registers and Counters Fundamentals of Logic esign EE2369 Prof. Eric Maconald Fall Semester 23 Registers Groups of flip-flops Can contain data format can be unsigned, 2 s complement and other more
More informationDigital Systems Laboratory 3 Counters & Registers Time 4 hours
Digital Systems Laboratory 3 Counters & Registers Time 4 hours Aim: To investigate the counters and registers constructed from flip-flops. Introduction: In the previous module, you have learnt D, S-R,
More informationproblem maximum score 1 28pts 2 10pts 3 10pts 4 15pts 5 14pts 6 12pts 7 11pts total 100pts
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2002 4/5/02 Midterm Exam II Name: Solutions ID number:
More informationCS3350B Computer Architecture Winter 2015
CS3350B Computer Architecture Winter 2015 Lecture 5.2: State Circuits: Circuits that Remember Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted from lectures on Computer Organization and Design,
More informationThe NOR latch is similar to the NAND latch
5-2 NOR Gate Latch The NOR latch is similar to the NAND latch except that the Q and Q outputs are reversed. The set and clear inputs are active high, that is, the output will change when the input is pulsed
More informationCatch or Die! Julia A. and Andrew C. ECE 150 Cooper Union Spring 2010
Catch or Die! Julia A. and Andrew C. ECE 150 Cooper Union Spring 2010 Andrew C. and Julia A. DLD Final Project Spring 2010 Abstract For our final project, we created a game on a grid of 72 LED s (9 rows
More informationMODULE 3. Combinational & Sequential logic
MODULE 3 Combinational & Sequential logic Combinational Logic Introduction Logic circuit may be classified into two categories. Combinational logic circuits 2. Sequential logic circuits A combinational
More informationCHAPTER 4: Logic Circuits
CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits
More informationTMEL53, DIGITALTEKNIK. INTRODUCTION TO SYNCHRONOUS CIRCUITS, FLIP-FLOPS and COUNTERS
LINKÖPING UNIVERSITY Department of Electrical Engineering TMEL53, DIGITALTEKNIK INTRODUCTION TO SYNCHRONOUS CIRCUITS, FLIP-FLOPS and COUNTERS Mario Garrido Gálvez mario.garrido.galvez@liu.se Linköping,
More informationVARIABLE FREQUENCY CLOCKING HARDWARE
VARIABLE FREQUENCY CLOCKING HARDWARE Variable-Frequency Clocking Hardware Many complex digital systems have components clocked at different frequencies Reason 1: to reduce power dissipation The active
More informationSequential Logic and Clocked Circuits
Sequential Logic and Clocked Circuits Clock or Timing Device Input Variables State or Memory Element Combinational Logic Elements From combinational logic, we move on to sequential logic. Sequential logic
More informationCOMP2611: Computer Organization. Introduction to Digital Logic
1 COMP2611: Computer Organization Sequential Logic Time 2 Till now, we have essentially ignored the issue of time. We assume digital circuits: Perform their computations instantaneously Stateless: once
More informationINC 253 Digital and electronics laboratory I
INC 253 Digital and electronics laboratory I Laboratory 9 Sequential Circuit Author: ID Co-Authors: 1. ID 2. ID 3. ID Experiment Date: Report received Date: Comments For Instructor Full Marks Pre lab 10
More informationDigital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill
Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Objectives: Analyze the operation of sequential logic circuits. Understand the operation of digital counters.
More informationWhy do we need to debounce the clock input on counter or state machine design? What happens if we don t?
EEL 37 Digital Logic and Computer Systems Test 2 Fall Semester 25. Switch debouncing. (2 pts.) Why do we need to debounce the clock input on counter or state machine design? What happens if we don t? (
More informationContents Circuits... 1
Contents Circuits... 1 Categories of Circuits... 1 Description of the operations of circuits... 2 Classification of Combinational Logic... 2 1. Adder... 3 2. Decoder:... 3 Memory Address Decoder... 5 Encoder...
More informationIT T35 Digital system desigm y - ii /s - iii
UNIT - III Sequential Logic I Sequential circuits: latches flip flops analysis of clocked sequential circuits state reduction and assignments Registers and Counters: Registers shift registers ripple counters
More informationUniversidad Carlos III de Madrid Digital Electronics Exercises
1. Complete the chronogram for the circuit given in the figure. inst7 NOT A INPUT VCC AND2 inst5 DFF D PRN Q CLRN inst XOR inst2 TFF PRN T Q CLRN inst8 OUTPUT OUTPUT Q Q1 CLK INPUT VCC CLEARN INPUT VCC
More informationLogic Devices for Interfacing, The 8085 MPU Lecture 4
Logic Devices for Interfacing, The 8085 MPU Lecture 4 1 Logic Devices for Interfacing Tri-State devices Buffer Bidirectional Buffer Decoder Encoder D Flip Flop :Latch and Clocked 2 Tri-state Logic Outputs
More informationEKT 121/4 ELEKTRONIK DIGIT 1
EKT 2/4 ELEKTRONIK DIGIT Kolej Universiti Kejuruteraan Utara Malaysia Sequential Logic Circuits - COUNTERS - LATCHES (review) S-R R Latch S-R R Latch Active-LOW input INPUTS OUTPUTS S R Q Q COMMENTS Q
More informationChapter 9 Counters. Clock Edge Output Q 2 Q 1 Q
hapter 9 ounters 9. Introduction ounters are devices which have a LOK input and produce n outputs. ounters consist of flip-flops connected together in specific ways such that on each clock edge the output
More informationCOMP sequential logic 1 Jan. 25, 2016
OMP 273 5 - sequential logic 1 Jan. 25, 2016 Sequential ircuits All of the circuits that I have discussed up to now are combinational digital circuits. For these circuits, each output is a logical combination
More informationDIGITAL REGISTERS. Serial Input Serial Output. Block Diagram. Operation
DIGITAL REGISTERS http://www.tutorialspoint.com/computer_logical_organization/digital_registers.htm Copyright tutorialspoint.com Flip-flop is a 1 bit memory cell which can be used for storing the digital
More informationRegisters and Counters
Registers and Counters A register is a group of flip-flops which share a common clock An n-bit register consists of a group of n flip-flops capable of storing n bits of binary information May have combinational
More informationCprE 281: Digital Logic
CprE 281: igital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Registers CprE 281: igital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Administrative
More informationCHAPTER1: Digital Logic Circuits
CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits 1 Sequential Circuits Introduction Composed of a combinational circuit to which the memory elements are connected to form a feedback
More informationLecture 12. Amirali Baniasadi
CENG 24 Digital Design Lecture 2 Amirali Baniasadi amirali@ece.uvic.ca This Lecture Chapter 6: Registers and Counters 2 Registers Sequential circuits are classified based in their function, e.g., registers.
More informationUniversity of Victoria. Department of Electrical and Computer Engineering. CENG 290 Digital Design I Lab Manual
University of Victoria Department of Electrical and Computer Engineering CENG 290 Digital Design I Lab Manual INDEX Introduction to the labs Lab1: Digital Instrumentation Lab2: Basic Digital Components
More information# "$ $ # %!"$!# &!'$("!)!"! $ # *!"! $ '!!$ #!!)! $ "# ' "
!" #!""! # "$ $ # %!"$!# &!'$("!)!"! $ # *!"! $ '!!$ #!!)! $ "# ' " % &! # Design a combinational logic circuit 10:4 encoder which has a 10-bit input (D9 to D0) and a 4-bit output. If bit position i of
More informationObjectives. Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath
Objectives Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath In the previous chapters we have studied how to develop a specification from a given application, and
More informationFactory configured macros for the user logic
Factory configured macros for the user logic Document ID: VERSION 1.0 Budapest, November 2011. User s manual version information Version Date Modification Compiled by Version 1.0 11.11.2011. First edition
More informationLaboratory Exercise 7
Laboratory Exercise 7 Finite State Machines This is an exercise in using finite state machines. Part I We wish to implement a finite state machine (FSM) that recognizes two specific sequences of applied
More informationSynchronous sequential circuits
8.6.5 Synchronous sequential Table of content. Combinational circuit design. Elementary combinatorial for data transmission. Memory structures 4. Programmable logic devices 5. Algorithmic minimization
More informationCPSC 121: Models of Computation Lab #5: Flip-Flops and Frequency Division
CPSC 121: Models of Computation Lab #5: Flip-Flops and Frequency Division Objectives In this lab, you will see two types of sequential circuits: latches and flip-flops. Latches and flip-flops can be used
More informationImplementation of BIST Test Generation Scheme based on Single and Programmable Twisted Ring Counters
IOSR Journal of Mechanical and Civil Engineering (IOSR-JMCE) e-issn: 2278-1684, p-issn: 2320-334X Implementation of BIST Test Generation Scheme based on Single and Programmable Twisted Ring Counters N.Dilip
More informationChapter 6. Flip-Flops and Simple Flip-Flop Applications
Chapter 6 Flip-Flops and Simple Flip-Flop Applications Basic bistable element It is a circuit having two stable conditions (states). It can be used to store binary symbols. J. C. Huang, 2004 Digital Logic
More informationStep 1 - shaft decoder to generate clockwise/anticlockwise signals
Workshop Two Shaft Position Encoder Introduction Some industrial automation applications require control systems which know the rotational position of a shaft. Similar devices are also used for digital
More informationDigital Electronics II 2016 Imperial College London Page 1 of 8
Information for Candidates: The following notation is used in this paper: 1. Unless explicitly indicated otherwise, digital circuits are drawn with their inputs on the left and their outputs on the right.
More informationRead-only memory (ROM) Digital logic: ALUs Sequential logic circuits. Don't cares. Bus
Digital logic: ALUs Sequential logic circuits CS207, Fall 2004 October 11, 13, and 15, 2004 1 Read-only memory (ROM) A form of memory Contents fixed when circuit is created n input lines for 2 n addressable
More informationEE178 Spring 2018 Lecture Module 5. Eric Crabill
EE178 Spring 2018 Lecture Module 5 Eric Crabill Goals Considerations for synchronizing signals Clocks Resets Considerations for asynchronous inputs Methods for crossing clock domains Clocks The academic
More information