Digital Logic Design ENEE x. Lecture 24
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1 Digital Logic Design ENEE x Lecture 24
2 Announcements Homework 9 due today Thursday Office Hours (12/10) from 2:30-4pm Course Evaluations at the end of class today. Log in with directory id and password Final exam info: Wednesday, Dec. 16 1:30-3:30pm in EGR 1108 (our regular classroom). Review session next class and during Thursday s recitation Information about final exam and review problems for the review sessions will be up on course webpage by tonight.
3 Agenda Last Time: The State Assignment Problem (7.5) Completing the Design of Clocked Synchronous Sequential Networks (7.6) This Time: Synchronous Sequential network design using PLDs (7.6) Algorithmic State Machines ( )
4 Realizations of Synchronous Sequential Networks using PLDs
5 PROM Realization
6 PROM Realization
7 PLA Realization
8 PLA Realization D 1 = Q 2 Q 3 x D 2 = Q 2 Q 3 + Q 1 x + Q 2 Q 3 x D 3 = Q 3 x + Q 2 x z = Q 2 x + Q 3 x
9 PLA Realization
10 Final Topic: Algorithmic State Machines Previous chapter dealt with the classical approach to clocked synchronous sequential network design Used models of Mealy and Moore Also called Finite State Machines Algorithmic State Machines (ASM) Different approach to clocked synchronous network design Approach is higher-level Uses flow-charts as in high-level programming We explicitly name and use variables! Capable of handling more complex systems
11 Algorithmic State Machine Partitions the system into two entities: Controller Controlled architecture (data processor) Data processor includes: Flip-flops, shift registers, counters, adders/subtractors, comparators, etc. Controller supplies a time sequence of commands to the devices of the data processer E.g. shift left, shift right, add, subtract, increment, reset. Data processor supplies information about the status of its various devices. The controller is a hardware algorithm (thus is called an algorithmic state machine (ASM).
12 Model of an ASM Mealy Moore
13 ASM Charts Components State Box: The state output list contains output variables that are only a function of the state. Such variables that have logic-1 value are placed in this box. Decision Box
14 Conditional Output Box: ASM Charts Components The conditional output list contains output variables that are a function of the state and external inputs. Such variables that have logic-1 value are placed in this box.
15 ASM Blocks Consists of the interconnection of a single state box along with a collection of decision and conditional output boxes. One entry path, one or more exit paths leading to another state box. A path through an ASM block from its state box to an exit path is called a link path.
16 Rules for ASM blocks For any valid combination of values to the decision-box variables, all simultaneously selected link paths must lead to the same exit path. i.e. next state is uniquely determined There can be no closed loops that do not contain at least one state box State box is the only component that is time dependent.
17 Simple ASM Charts
18 From State Diagram to ASM Chart
19 From State Diagram to ASM Chart
20 Material after this slide is NOT on the Final Exam
21 Examples of ASM Charts
22 A Sequence Recognizer Recognize input sequence of pairs x 1 x 2 = 01,01,11,00 An output z is to be 1 when x 1 x 2 = 00 if and only if the three preceding pairs of inputs are x 1 x 2 = 01,01,11 in that order.
23 A Sequence Recognizer
24 A Parallel Binary Multiplier A C M B Bits of answer are shifted out one at a time
25 A Parallel Binary Multiplier Variables: S = 1 indicates the multiplication is to start M 1 is the multiplier bit appearing at the rightmost end of register M. Z = 1 indicates the content of the counter is 0. INIT = 1 indicates initialization should be performed: 1. Setting flip-flop C and register A to 0 2. Setting counter to the number of bits in the multiplier, N 3. Parallel loading the multiplier and multiplicand into registers M, B. DECREM = 1 enables the counter for decrementing ADD = 1 indicates A and B should be added and resulting N+1 bits entered into register A and flip-flop C SR = 1 indicates the contents of flip-flop C, register A and register M should be shifted one bit position to the right while entering a 0 into flip-flop C. COMPLETE = 1 indicates the multiplication process is complete.
26 A Parallel Binary Multiplier Variables: S = 1 indicates the multiplication is to start M 1 is the multiplier bit appearing at the rightmost end of register M. Z = 1 indicates the content of the counter is 0. INIT = 1 indicates initialization should be performed: 1. Setting flip-flop C and register A to 0 2. Setting counter to the number of bits in the multiplier, N 3. Parallel loading the multiplier and multiplicand into registers M, B. DECREM = 1 enables the counter for decrementing ADD = 1 indicates A and B should be added and resulting N+1 bits entered into register A and flip-flop C SR = 1 indicates the contents of flip-flop C, register A and register M should be shifted one bit position to the right while entering a 0 into flip-flop C. COMPLETE = 1 indicates the multiplication process is complete.
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