8-BITS X 8-BITS MODIFIED BOOTH 1 S COMPLEMENT MULTIPLIER NORAFIZA SALEHAN

Transcription

1 8-BITS X 8-BITS MODIFIED BOOTH 1 S COMPLEMENT MULTIPLIER by NORAFIZA SALEHAN Report submitted in partial fulfillment of the requirements for the degree of Bachelor of Engineering (Electronic Enginering) MAY 2007

2 ACKNOWLEDGEMENT I would like to take this opportunity to thank everybody who helped in any way for this project. I would like to express my gratitude and respect to my project supervisor, Madam Norina Idris for her advice, guidance, supervision, patience and understanding throughout this project. I would like to thank my friends for all their support and friendship and I would like to wish them good luck in their future. To my family especially my parents, for their love, support and encouragement. Last but not least, to the School of Microelectronic Engineering of Universiti Malaysia Perlis for providing the facilities that enable the success of this project.

3 PENDARAB 8-BIT X 8- BIT PELENGKAP 2 TERTANDA BAUGH-WOOLEY TERUBAHSUAI ABSTRAK Dengan kemajuan dalam teknologi, banyak penyelidik telah cuba dan mencuba mereka bentuk pendarab yang menawarkan samaada kelajuan yang tinggi, penggunaan kuasa rendah, dan penggunaannya dalam Kamiran Berskala Sangat Besar, oleh itu membuatkan ia sesuai untuk pelbagai penggunaan seperti kelajuan tinggi, kuasa rendah Kamiran Berskala Sangat Besar yang padat. Projek ini memberi tumpuan kepada kelajuan Pendarab 8-Bit x 8-Bit Pelengkap 2 Tertanda Baugh-Wooley Terubahsuai. Tiga cara untuk meningkatkan kelajuan pendarab mengurangkan bilangan produkproduk separa, menambahkan kelajuan penambahan produk-produk separa dan pipelining. Kelajuan Pendarab 8-Bit x 8-Bit Pelengkap 2 Tertanda Baugh-Wooley Terubahsuai, ditingkatkan dengan mengurangkan produk-produk separa dan kemudian menjumlahkan produk-produk separa ini dengan menggunakan Carry Save Adder. Analisis kelajuan prestasi Pendarab 8-Bit x 8-Bit Pelengkap 2 Tertanda Baugh-Wooley Terubahsuai ini dibuat menggunakan Altera Quartus II. Projek ini membuktikan bahawa Pendarab mempunyai prestasi kelajuan yang tinggi dan analisa kelajuan pada EPF10K70. ii

4 ABSTRACT With advances in technology, many researchers have tried and are trying to design multipliers which offers either of following high speed, low power consumption, regularity of layout and hence less area or even combination of them in one multiplier, thus making them suitable for various high speed, low power, and compact VLSI implementation. This project focuses on speed performance of the Modified Baugh- Wooley Two s Complement Signed Multiplier. Three methods to improve speed performance of the multiplier reduce the number of partial products and accelerate the accumulation have been discussed in literature view. For Modified Baugh-Wooley Two s Complement Signed Multiplier the speed is improved by reducing the partial products and then summing these partial products using Carry Save Adder. The schematic design as well as speed performance analysis of this multiplier is done using Altera s Quartus II Software and speed obtained on EPF10K70. iii

5 TABLE OF CONTENTS ACKNOWLEDGMENT APPROVAL AND DECLARATION SHEET ABSTRAK ABSTRACT TABLE OF CONTENTS LIST OF TABLES LIST OF FIGURES Page i ii iii iv vi vii CHAPTER 1 INTRODUCTION 1.1 Background History High Speed Multiplier Objective 3 CHAPTER 2 LITERATURE REVIEW 2.1 Introduction High Speed Multiplier Array Multiplier Tree Multiplier Booth Multiplier Modified Baugh-Wooley Two s Complement Signed Multiplier Two s Complement System Modified Baugh-Wooley Two s Complement Signed Multiplier 8 v

6 Page CHAPTER 3 METHODOLOGY 3.1 Introduction Flow Chart of the Project Subcircuits Design AND Gate NAND Gate Half Adder Carry Save Adder D Flip-flop The Design of Modified Baugh-Wooley Two s Complement Signed Multiplier Approaches to Increase the Speed Performance of the Modified Baugh-Wooley Two s Complement Signed Multiplier Reduce the Partial Products Accelerate the Accumulation Pipelining 25 CHAPTER 4 RESULTS AND DISCUSSION 4.1 Introduction Half Adder Carry Save Adder Modified Baugh-Wooley Two s Complement Signed Multiplier 29 CHAPTER 5 CONCLUSION 5.1 Summary Recommendation for Future Project 38 REFERENCES 39 vi

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8 Figures No. Page 3.10 Modified Baugh-Wooley Two s Complement Signed Multiplication [9] Dependence Graph for the 4-bits x 4-bits Carry Save Array Multiplier A Carry Save Vector Merging Non-pipelined Version Pipeline Version Logic Diagram of Half Adder Simulation Waveform of Half Adder Logic Diagram of Carry Save Adder Simulation Waveform of Carry Save Adder bits x 8-bits Modified Baugh-Wooley Signed Multiplier Simulation Waveform of Both Positive Numbers Multiplication Simulation Waveform of Both Negative Numbers Multiplication Simulation Waveform of Positive and Negative Numbers Multiplication bits x 8-bits Modified Baugh-Wooley Signed Multiplier with D Flip-flop at Inputs and Outputs Speed Performance for Modified Baugh-Wooley Signed Multiplier Simulation Waveform for Modified Baugh-Wooley Signed Multiplier 35 ix

9 LIST OF FIGURES Figures No. 1.1 Mutiplication Example bits x 4-bits Array Multiplier [6] A Multiplier with Wallace Tree [6] Two s Complement and One s Complement Representations Unsigned Multiplication [9] Two s Complement Mutiplication [9] Baugh-Wooley Two s Complement Signed Mutiplication [9] Modified Baugh-Wooley Singed Two s Complement Multiplication [9] Flow Chart of the Project Logic Diagram of Two Input AND Gate Logic Diagram of Two Input NAND Gate Logic Diagram of Half Adder The (3,2) Counter Block Diagram Logic Diagram of Full Adder Block Diagram of D Flip-flop Tabular Form of Bit-Level Modified Baugh-Wooley Two s Complement Signed Multiplication Baugh-Wooley Two s Complement Multiplication [9] 22 Page viii

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11 LIST OF TABLES Tables No. Page 3.1 Truth Table for A Two Input AND Gate Truth Table for A Two Input AND Gate Truth Table for Half Adder Truth Table for Full Adder Truth Table for D Flip-Flop Performance of Modified Baugh-Wooley Two s Complement Signed Multiplier 38 vii