Sharif University of Technology. SoC: Introduction

Transcription

1 SoC Design Lecture 1: Introduction Shaahin Hessabi Department of Computer Engineering

2 System-on-Chip System: a set of related parts that act as a whole to achieve a given goal. A system is a set of interacting components, which has inputs and outputs, and exhibits specific behavior. Behavior: a function that translates inputs into outputs System: an entity consisting of hardware and software Hardware: high speed, low power consumption, less price (probably) Software: flexibility, ease of modification and upgrade Hardware system: a system whose physical components are electronic blocks Analog Digital Mixed signal Slide 2of 32

3 Digital vs. Analog Systems The critical advantage of digital systems is their ability to deal with electrical signals that have been degraded. Due to the discrete nature of the outputs, a slight variation in an input is still interpreted correctly. In analog circuits, a slight error at the input generates an error at tth the output. t The simplest form of a digital system is binary. A binary signal is modeled d as taking on only two discrete values (0 or 1, LOW or HIGH, False or True). Slide 3of 32

4 Advantages of Digital Systems 1. High noise immunity 2. Adjustable precision 3. Less sensitivity to variations in components and environmental parameters (especially temperature) 4. Ease of design ( automation) and fabrication, and therefore, low cost 5. Better reliability 6. Less need to calibration and maintenance 7. Ease of diagnosis and repair 8. Easy to duplicate similar circuits 9. Easily controllable by computer Slide 4of 32

5 Disadvantages of Digital Systems 1. Lower speed 2. Need analog to digital (A/D) and digital to analog (D/A) converters to communicate with real world; therefore, more expensive or less precise Slide 5of 32

6 Contemporary Digital Design Major changes in digital design in recent years: Scale Time Cost More complex designs New methodologies and techniques required, like SoC Shorter time-to-market (TTM) Cheaper products Pervasive use of computer-aided design tools over hand methods Multiple l levels l of design representation ti Emphasis on abstract design representations Programmable rather than fixed function components Automatic synthesis techniques Importance of sound design methodologies higher levels of integration use of simulation to debug designs Slide 6of 32

7 Software Tools Digital design need not involve any software tools; however, Software tools are nowadays an essential part of digital design. HDLs (Hardware Description Languages) and the corresponding simulation and synthesis tools are widely used. In a CAD (Computer-Aided Design) environment, the tools improve the productivity and help in correcting errors and predicting behavior. Schematic entry; HDLs compilers, simulators and synthesis tools; Timing analysers; Simulators Test benches. Slide 7of 32

8 Integrated Circuits (ICs) An IC is a collection of gates/blocks/... fabricated on a single silicon chip. ICs are classified by their size: SSI (small scale integration): 1 to 30 gates - a small number of gates. MSI (medium scale integration): 30 to 300 gates - decoder, register, counter. LSI (large scale integration): 300 to 300, gates - small memories, PLDs. VLSI (very large scale integration): > 1,000,000 transistors - microprocessors, memories. The Core 2 Extreme QX9650 Quad Core Processor (Intel 2008, 45 nm technology) has 820 million transistors (420 M transistors per die) Slide 8of 32

9 Implementation Technologies Slide 9of 32

10 Modern Systems Basic elements: Microprocessors, buses and ASICs. Basic problems: HW/SW partitioning. HW/SW co-simulation (including communication modeling). Different design trade-offs. Separate HW and SW design flows. Slide 10 of 32

11 What is an SoC? SoC Concept in the past simply implied higher levels of integration (Moore s law): A single chip replaces the whole multichip system-on- board Different chips on PCB ( (Printed Circuit Board) ) are now building blocks ( (cores) of SoC chip Advantages: On-chip interconnects are many times faster than off-chip wires Get a compact system with the same functionality Reduces pin overhead Saves much power Reduces noise in the mixed-signal/analog circuits Lower overall cost Slide 11 of 32

12 What is an SoC? (cont d) Today s concept: gaining overall productivity gains through reusable design and integration of components Complex IC that integrates the major functional elements of a complete end-product into a single chip using intellectual property (IP) blocks. IPs: pre-designed and pre-verified Also called: virtual components Slide 12 of 32

13 Design Productivity Gap Procee edings of the IEEE, June SoC/IP approach improves the situation Platform-Based Design improves it further Slide 13 of 32

14 An SoC usually contains: Inside an SoC Reusable IP Requires connecting computational units to communication medium Embedded processor, memory Real-world interface (wireless receiver/transmitter, ) Sensor Mixed-signal blocks Programmable hardware RTOS and embedded software, device drivers Has more than 500 K gates, Uses.25 μm technology or below Is not an ASIC Primary difference from ASIC: in SOC design, the goal is to maximize reuse of existing blocks or cores Slide 14 of 32

15 Why SoC? Increased functionality/performance in reduced footprint Tighter design schedule Bandwidth and performance Simplified PCB design Increased product mechanical robustness Lower power consumption Technology scaling Lower system cost Slide 15 of 32

16 System-in in-a-package (SIP) SoC technology a great success, EXCEPT for radio receiver/transmitters Can sustain mixed analog/digital hardware together on one chip, provided that: Analog hardware is in the low-frequency band Digital clocks & their harmonics are carefully chosen to avoid polluting key parts of the spectrum with noise Key result: Still unable to integrate radio frequency (RF) hardware into SoC Substrate coupling between digital and analog parts causes digital clock noise to destroy the signal-to-noise ratio of RF part RF tuners still require precision inductors, but on-chip inductors are expensive and inadequate Slide 16 of 32

17 System-in in-a-package (SIP) Interim solution: Combine separate digital & analog chips and passive components into a single package (SIP, or MCM= Multi-Chip Module) Common 2-D or 3-D substrate May contain SoC as one of the chips Proceedings of the IEEE, June 2006 Slide 17 of 32

18 Increasing complexity Time-to to-market pressure Verification bottleneck Integration Hardware v.s.. software SoC Challenges Digital circuits v.s. analog circuits Testing issues Deep submicron effects Timing i closure problem Signal integrity problem Reliability problem Slide 18 of 32

19 Time-to-Market Pressure Pressure from shorter product lifespan An additional key factor in TTM, specific for SoC: System integration = integrating g different silicon IPs on the same IC Slide 19 of 32

20 Time-to-Market Pressure (cont d) Profit model showing the value of TTM: Slide 20 of 32

21 Verification Bottleneck Verification becomes the major bottleneck of the modern design flows Slide 21 of 32

22 Increasing complexity Time-to to-market pressure Verification bottleneck Integration Hardware v.s.. software SoC Challenges Digital circuits v.s. analog circuits Testing issues Deep submicron effects Timing i closure problem Signal integrity problem Reliability problem Slide 22 of 32

23 HW/SW Integration Integrating HW/SW at the final step may require high cost. Early integration (HW/SW codesign) Trend toward increasing design complexity due to integration Slide 23 of 32

24 Challenges for Mixed Signal Designs Design challenges Chip-level l simulation takes too much time Design budgets are not distributed in a well-defined manner Too much time is spent on low-level level iterations Design is not completely systematic There is limited or no use of HDL Slide 24 of 32

25 SoC Testing Challenges Distributed design and test Core provider does not know the target t environment System integrator is responsible for manufacturing testing Test access Bed-of-nails (decomposition) system testing is not possible Most of the cores are surrounded by many other cores Results in very poor controllability and observability bilit Need electronic test hardware to access these blocks during testing Bandwidth, I/O pin count limitations Test optimization Minimizing test cost while satisfying constraints such as power, resources, coverage, etc. Slide 25 of 32

26 Increasing complexity Time-to to-market pressure Verification bottleneck Integration Hardware v.s.. software SoC Challenges Digital circuits v.s. analog circuits Testing issues Deep submicron effects Timing i closure problem Signal integrity problem Reliability problem Slide 26 of 32

27 Timing Closure Problem Traditional silicon design flows: used statistical wire-load models to estimate metal interconnects for pre-layout timing analysis load on a specific node: estimated by the sum of the input capacitances of the gates being driven statistical wire estimate based on the size of the block and the number of gates being driven Correct for 250 nm and above, because the gate propagation delays and gate load capacitances dominate Wire delay starts to dominate total delay in DSM process Lack of physical information about wire length Only statistical wire delay model can be used at design phase Inaccurate because they represent a statistical value based on the block size Incorrect estimations require long iterations to meeting timing Slide 27 of 32

28 Signal Integrity, Reliability Feature size sub-wavelength lithography (impacts of process variation), noise, cross-talk, SEU, reliability Frequency, dimension interconnect delay, electromagnetic ti field effects, timing i closure Supply voltage signal integrity (noise, IR drop, etc) Wiring level manufacturability Power consumption power & thermal issues Slide 28 of 32

29 General Architecture of Core-Based SoC Slide 29 of 32

30 1. Front-end design Design Flow Traditional Design Flow: Begins with system definition in behavioral or algorithmic form and ends with floor planning 2. Back-end design Begins with placement/routing through layout release (tape-out) Engineers in either phase don t know much about the other phase Slide 30 of 32

31 Design Flow (cont d) Vertical Integrated Design Environment: Engineers have full responsibility for a block from system design specifications to physical design prior to chip- level integration Necessary for functional verification of complex blocks with post- layout timing Avoids last minute surprises related to block aspect ratio, timing, routing, or architectural and area/performance trade-offs Must be familiar with several CAD tools in a complex EDA environment Slide 31 of 32

32 Task responsibilities of an engineer in a vertical design environment nm nt Slide 32 of 32