Module 4:FLIP-FLOP. Quote of the day. Never think you are nothing, never think you are everything, but think you are something and achieve anything.
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1 Module 4:FLIP-FLOP Quote of the day Never think you are nothing, never think you are everything, but think you are something and achieve anything. Albert Einstein
2 Sequential and combinational circuits A digital circuit whose output depends on only applied input is combinational circuit. Digital circuits studied until now are combinational circuits A digital circuit whose output not only depends on applied input but also depends on the present state of output is Sequential circuit. Sequential circuit has memory. Flip-flop is a basic element of sequential circuit.
3 FLIP-FLOP A basic sequential circuit is a flip-flop Flip-flop has two stable states of complementary output values
4 NOR Gate Latch\SR Flip-flop SR (set-reset) flip-flop based on two nor gates. If R=,S= then output of both NOR gates depend on other inputs,i.e Q and Q Assume Q= and Q = initially Observe that out put will not change SR-FLIP-FLOP R S Q Q
5 NOR Gate Latch\SR Flip-flop SR (set-reset) flip-flop based on two nor gates. If R=,S= then output of both NOR gates depend on other inputs,i.e Q and Q Assume Q= and Q = initially Observe that out put will not change SR-FLIP-FLOP R S Q Q Last state
6 NOR Gate Latch\SR Flip-flop SR (set-reset) flip-flop based on two nor gates. If R=,S= then output of Gate 2 becomes one, i.e. Q = and output of gate which depends on Q becomes. Observe that out put set to one whatever may be previous state of O/P. SR-FLIP-FLOP R S Q Q Last state
7 NOR Gate Latch\SR Flip-flop SR (set-reset) flip-flop based on two nor gates. If R=,S= then output of Gate becomes zero, i.e Q= and output of gate 2 which depends on Q becomes. Observe that out put reset to zero whatever may be previous state of O/P. SR-FLIP-FLOP R S Q Q Last state
8 NOR Gate Latch\SR Flip-flop SR (set-reset) flip-flop based on two nor gates. If R=,S= then output of both Gates becomes zero, i.e. Q= and Q =. This is not allowed state of Flip Flop. Is Illegal state or Forbidden state of Flip-flop SR-FLIP-FLOP R S Q Q Last state Illegal
9 NAND Gate Latch\S R Flip-flop SṞ (set-reset) flip-flop based on two nor gates. If R =,S = then output of both Gates becomes one, i.e. Q= and Q =. This is not allowed state of Flip Flop. Is Illegal state or Forbidden state of Flip-flop S R -FLIP-FLOP R S Q Q Illegal
10 NAND Gate Latch\S R Flip-flop SṞ (set-reset) flip-flop based on two nor gates. If R =,S = then output of Gate-2 becomes one, i.e Q = and output of gate which depends on Q becomes. Observe that out put reset to zero whatever may be previous state of O/P. S R -FLIP-FLOP R S Q Q Illegal
11 NAND Gate Latch\S R Flip-flop SṞ (set-reset) flip-flop based on two nor gates. If R =,S = then output of Gate- becomes one, i.e Q= and output of gate 2 which depends on Q becomes. Observe that out put set to one whatever may be previous state of O/P. S R -FLIP-FLOP R S Q Q Illegal
12 NAND Gate Latch\S R Flip-flop SṞ (set-reset) flip-flop based on two nor gates. If R =,S = then output of both NOR gates depend on other inputs,i.e Q and Q. Assume Q= and Q = initially. Observe that out put will not change. S R -FLIP-FLOP R S Q Q Illegal
13 NAND Gate Latch\S R Flip-flop SṞ (set-reset) flip-flop based on two nor gates. If R =,S = then output of both NOR gates depend on other inputs,i.e Q and Q. Assume Q= and Q = initially. Observe that out put will not change. SR-FLIP-FLOP R S Q Q Illegal Last state
14 Truth table R S R S Q Q Illegal Last state SR-FLIP-FLOP R S Q Q Output(Q) Last state Last state Set Reset Illegal Illegal
15 Flip-Flop The previous slides described you the NAND/NOR Gate Latch. You observed that a latch using NAND is referred as SṞ latch. SR-FLIP-FLOP R S Q Q Illegal Last states To obtain SR latch using NAND gates, we are suppose to add two NOT gates implemented using NAND gates at the terminal of these inputs SṞ.
16 SR latch using NAND gates Flip-flop Truth table Logical Symbol R S R S Q + Q + Last state Illegal S R Q Q
17 Gated Flip-Flops In the latches observed till now output responds immediately to the changes in input. In many digital systems it is required that the circuit responds only at some prescribed time, decided by another input called the enable or clock input. A Flip-Flop which immediately responds to the changes of input in spite of enable or clock input is referred as latch. Some flip-flops responds to the changes of input during the edges of the clock inputs.
18 Gated Flip-Flops The latch will disable with C= and continue the last state. The output is said to be latched. It will enable with C= and function as normal SR F/F. Q n is present state of output, Q n- last state of output state
19 Gated Latch-Clocked RS Flip-flop Logical Symbol S Q C R Q
20 Input output waveform CLK S R Q
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