Project 6: Latches and flip-flops

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1 Project 6: Latches and flip-flops Yuan Ze University epartment of Computer Engineering and Science Copyright by Rung-Bin Lin, 1999 All rights reserved ate out: 06/5/2003 ate due: 06/25/2003 Purpose: This project is to design CMOS latches and flip-flops. Characterization of setup and hold times is also carried out. Introduction: Latches and flip-flops not only form the basic components of a finite state machine, but also serve as memory elements for data path. The most commonly used latches are level-sensitive latches, while the most commonly used flip-flops are edge-triggered and T flip-flops. Choice of latches or flip-flops depends on design methodology and area and timing requirements. In general, latches are employed for high-speed and high-density designs, but the use of latches may impose very strict timing requirement for the design and thus poses a difficult challenge for timing verification. While the use of edge-triggered flip-flops may be easier to deal with timing-related problems for the design, but flip-flops are slower and take more area. Since a flip-flop usually consists of two latches, understanding the operation of latches is indispensable to designing of flip-flops. Latches and flip-flips can be static or dynamic. A dynamic latch or flip-flop gradually loses its content as time goes, while a static one retains its content no matter how much time is elapsed. Figure 6.1 shows a static latch, while Figure 6.2 shows a dynamic one. As one can see in Figure 6.2, the charge will leak out of the output capacitor of the dynamic latch as time goes and thus the content of the latch is lost. So the use of a dynamic latch should be carefully scrutinized. Figure 6.3 shows a positive edge-triggered flip-flop. This is a static flip-flop which consists of two static latches. The data is allowed to enter the first latch during CLK=0 whereas the second latch is closed (not allowing the data to enter the latch). When the clock goes from 0 to 1, the first latch is closed, while the second latch is opened to allow data to enter

2 the latch. At other moments, the output of flip-flop remains the same. Figure 6.4 shows a dynamic flip-flop whose content will be lost as time goes. Some of the latches or flip-flops can have set or/and reset inputs such that they can be set to a desired value synchronously or asynchronously. A latch or flip-flop is said to be - - synchronously set or reset if set or reset function is controlled by a clock. Figure 6.5 shows a static flip-flop that has asynchronous set and reset inputs. Figure 6.1. A static latch - - Figure 6.2. A dynamic latch

3 Figure 6.3. A static and positive edge-triggered flip-flop Figure 6.4. A dynamic flip-flop - -reset Figure 6.5. A static flip-flop with asynchronous set and reset -set In general, the operation of a latch or flip-flop involves two timing parameters- setup and hold times. The input data must arrive earlier than the clock and remains unchanged for a period after the clock arrives. Thus, setup time is defined as the difference between the latest input arrival time and the clock arrival time, while hold time is the difference between the clock arrival time and the time the input data can be changed. Thus, to design a latch or flip-flop, one should know how to characterize setup and hold time. See the appendix for the method employed to characterize setup and hold times. The designing of latches and flip-flops is of great important to a standard cell library. Since the cells of a standard cell library have the same height and its height is usually defined by the cell height of the flip-flops. If the cell height is improperly set, one may have difficulties to complete the layout design of other cells by the same cell height. If the cell height is set to 64λ (λ is the basic dimension used by the lambda rules to characterize a process technology), the designing of flip-flops may be quite a

4 challenge because routing resources become scarce. Basically, the larger is the cell height, the easier is the layout design. Problem descriptions: 1. Suppose input rise/fall time is 0.3ns (measured from 0.1V dd to 0.9V dd ), assign the sizes to the transistors respectively in the two latches shown in Figure 6.1 and 6.2 such that the propagation delay (from 0.5V dd to 0.5V dd ) of any circuit structure is 1 ns ± 0. 1ns and the output rise/fall time is 0.5ns ± 0. 05ns for output load = 0. pf. Characterize setup time, hold time, minimum pulse width and power consumption of these two circuits under the given load. C out 4 2. Lay out the two latches with cell height set to 80λ. Their layouts should have the same cell height and power bus width. 3. Perform post layout timing simulation to obtain their propagation delay and rise/fall time. Compare these results to those obtained in problem (2). 4. Perform simulations to verify the functionality of the flip-flops shown respectively in Figure 6.3, 6.4 and 6.5. Find the propagation delay, output rise/fall time, and power consumption of the flip-flops with input rise/fall time set to 0.3ns and output load C out = 0. 4 pf. 5. Repeat the tasks in problem (2) for flip-flops. 6. Repeat the tasks in problem (3) for flip-flops. Notes: TSMC 0.35um process technology should be employed. Only metal 1 layer and poly layer can be used to interconnect transistors. Power and ground bus also use metal 1 layer. The width of power and ground buses is set to 10% of the cell height. The pin must be placed on grid with metal 1. The size of a grid is defined as the pitch from via 1 to via 1 which connects metal 1 to poly. Under the given timing requirements for each circuit, one should try to minimize the cell area. References: [1]. Neil H. E. Weste and Kamran Eshraghian, Principles of COMS VLSI esign: A System Perspective, Second Edition, Addison-Wesley, [2]. HSPICE User s Manual, Meta-Software, 1990.

5 Appendix: Characterization of setup time, hold time and minimum pulse width (A). Minimum Setup Time The minimum setup time is the smallest time interval for which data must remain stable on a data output before it is latched in by an active transition on an appropriate control input. For a flip-flop, this is the time period for which the data input must be maintained before the arrival of the active level of the clock input CLK. Setup time is measured from the clock transition relative to the input data transition at the 50% (default) points. Figure 6.6 shows the input/output waveforms of a flip-flop to describe this concept. The minimum setup time measurement is carried out by the following steps. First, let the data signal transit to a desired level at some point. After a long enough period of time is past, the clock transition is asserted. This time period is called reference setup. The propagation delay from clock to output transition is measured as a reference delay. Then, the data signal is changed to approach the clock active edge which should be fixed after the reference delay is obtained. The time difference between the changing data signal and the active clock edge is called T setup. The circuit designer defines an upper-bound and a lower-bound for the data transition moment around the active edge of clock signal and a bisection algorithm is used to search the minimum setup time within the window defined by the upper-bound and lower-bound. The minimum setup time is found when the output delay increases by more than 10% of the reference delay and the difference between the upper-bound and the lower-bound exceeds the user-defined precision. Figure 6.7 shows the measurement of setup time for a positive edge-triggered flip-flop. The following formula is used to determine the accuracy of the measurement iterations. p = { w/2 n } where p: the user-defined precision. w: the starting-window length. n: the number of iterations. So, for a starting window of 5ns with 10 iterations, the minimum setup time can be obtained with 0.01ns precision.

6 CLK CLK SET T setup CLR elay Figure 6.6. A positive-edge triggered flip-flop and its input/output waveforms Figure 6.7. The setup time measurement (B). Minimum Hold Time The minimum hold time is the shortest time interval immediately following the active transition of a control input during which the data on the appropriate data input must remain stable for the correct value to be latched. For a positive-edge flip-flop, the minimum hold time is the period of time after the active edge of clock input during which the input must be held constant. Figure 6.8 shows the hold time measurement for a positive-edge triggered flip-flop. The measurement methodology is the same as that for minimum setup time measurement.

7 CLK CLK SET T hold CLR Reference elay Figure 6.8. The hold time measurement for a positive edge-triggered flip-flop. (C). Minimum Clock Pulse Width The minimum pulse width of a clock signal is the shortest time needed between two edges of a signal for that signal to be functional. A signal can have both high and low minimum pulse widths. The first step of minimum pulse width measurement is to define a long fixed-width pulse as a reference pulse (see Figure. 6.9) and the propagation delay measured from active edge of clock signal to output transition as the standard output delay. Next, move the rising edge of measurement pulse closer to the falling edge until the flip-flop fails or until the output delay increases by more than 10% (failure threshold) of the standard delay. Figure 6.10 shows the relationship of output delay and pulse width. Figure 6.9. Reference pulse and measurement pulse

8 Figure The relationship of output delay and pulse width

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