Flip-Flops and Registers

Transcription

1 The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and were used with permission from Cengage Learning. Flip-Flops and Registers (Lecture #19)

2 Flip-Flops (continued)

3 SR Flip-Flop The SR Flip-Flop has three inputs Clock (Ck) --- denoted by the small arrowhead Set (S) and Reset (R) Similar to an SR Latch S = 1 sets the flip-flop (Q + = 1) R = 1 resets the flip-flop (Q + = 0) Like the D Flip-Flop, the Q output of an SR Flip-Flop only changes in response to an active clock edge. Positive edge-triggered Negative edge-triggered

4 SR Flip-Flop S R Q Q not allowed } Q+ } } = Q store Q + = 0 reset Q + = 1 set positive edge-triggered SR Flip-Flop State change occurs after active Clock edge

5 SR Flip-Flop (master-slave) SR Latches Enabled on opposite levels of the clock

6 SR Flip-Flop: Timing Diagram

7 JK Flip-Flop The JK Flip-Flop has three inputs Clock (Ck) --- denoted by the small arrowhead J and K Similar to the SR Flip-Flop J corresponds to S: J = 1 Q + = 1 K corresponds to R: K = 1 Q + = 0 Different from the SR Flip-Flop in that the input combination J = 1, K = 1 is allowed. J = K = 1 causes the Q output to toggle after an active clock edge.

8 JK Flip-Flop } Q+ } Q+ } Q+ } Q+ = Q store = 0 reset = 1 set = Q' toggle Characteristic Equation: Q + = J.Q' + K'.Q

9 JK Flip-Flop (master-slave) SR Latches Enabled on opposite levels of the clock

10 JK Flip-Flop: Timing Diagram

11 T Flip-Flop The Toggle (T) Flip-Flop has two inputs Clock (Ck) --- denoted by the small arrowhead Toggle (T) The T input controls the state change when T = 0, the state does not change (Q + = Q) when T = 1, the state changes following an active clock edge (Q + = Q') T Flip-Flops are often used in the design of counters.

12 T Flip-Flop Characteristic Equation: Q + = T.Q' + T'.Q = T xor Q

13 T Flip-Flop: Timing Diagram

14 Building a T Flip-Flop

15 Asynchronous Control Signals

16 Asynchronous Control Signals: Timing Diagram

17 D FF with Clock Enable

18 Flip-Flops in VHDL

19 JK Flip-Flop architecture JKFF of JKFF_entity is signal Qint: std_logic; begin Q <= Qint; Qnot <= not (Qint); process (Clk) begin if Clk'event and Clk = '0' then FF Clk Qint <= (J and not (Qint)) or (not (K) and Qint); end if; end process; end architecture;

20 D FF with Asynchronous Inputs Clk process (Clk) begin if ClrN = '0' then Q <= 0; elsif PreN = '0' then Q <= 1; elsif Clk'event and Clk = '1' then Q <= D; end if; end process;

21 Registers

22 Registers Several D flip-flops may be grouped together with a common clock to form a register. Because each flip-flop can store one bit of information, a register with n D flip-flops can store n bits of information. A load signal can be ANDed with the clock to enable and disable loading the registers. A better approach is to use registers with clock enables if they are available.

23 Register: 4 bits

24 Data Transfer between Registers Data transfer between registers is a common operation in computer (i.e. digital) systems. Multiple registers can be interconnected using tri-state buffers. Data can be transferred between two registers by enabling the proper tri-state buffer.

25 Data Transfer between Registers

26 Register with Tri-state Output

27 Data Transfer using Tri-state Bus

28 Shift Register shift register is a register in which binary data can be stored nd shifted either left or right. The data is shifted according to he applied shift signal; often there is a left shift signal and a ight shift signal. shift register must be constructed using flip-flops (i.e. edgeriggered devices); it cannot be constructed using latches or ated-latches (i.e. level-sensitive devices).

29 Shift Register: 4 bits

30 Shift Register (4 bits): Timing Diagram

31 8-bit SI SO Shift Register

32 4-bit PI PO Shift Register

33 -bit PI PO Shift Register: Operation

34 Registers in VHDL

35 4-bit Shift-Right Register process (Clock) begin if (Clk'event and Clk = '1') and Shift = '1' then Q3 <= SI after 8 ns; Q2 <= Q3 after 8 ns; Q1 <= Q2 after 8 ns; Q0 <= Q1 after 8 ns; SO <= Q0 after 8 ns; end if; end process;

36 Parallel Adder with Accumulator

37 Parallel Adder with Accumulator In computer circuits, it is frequently desirable to store one number in a register (called an accumulator) and add a second number to it, leaving the result stored in the register.

38 n-bit Parallel Adder with Accumulator

39 Loading the Accumulator Before addition in the previous circuit can take place, the accumulator must be loaded with X. This can be accomplished in several ways. The easiest way is to first clear the accumulator using the asynchronous clear inputs on the flip-flops, and then put the X data on the Y inputs to the adder and add the accumulator in the normal way. Alternatively, we could add multiplexers at the accumulator inputs so that we could select either the Y input data or the adder output to load into the accumulator.

40 Adder Cell with Multiplexer

41 Questions?