EKT 121/4 ELEKTRONIK DIGIT 1

Transcription

1 EKT 2/4 ELEKTRONIK DIGIT Kolej Universiti Kejuruteraan Utara Malaysia Sequential Logic Circuits - COUNTERS -

2 LATCHES (review)

3 S-R R Latch

4 S-R R Latch Active-LOW input INPUTS OUTPUTS S R Q Q COMMENTS Q Q No change (Latch in hold condition) Latch SET Latch RESET Not allowed (Invalid) Active-HIGH input

5 Gated S-R S R Latch ) In order for the SET and RESET inputs to change the latch, the gate input must be active HIGH (ENABLE) 2) When the gate input is LOW, the latch remains in the HOLD condition

6 Gated D Latch

7 Synchronous Flip-Flop Flop (review)

8 J-K K Flip-Flop Flop (Positive Edge-Triggered)

9 J-K K Flip-Flop Flop (Negative Edge-Triggered)

10 S-R R Flip-Flop Flop (Positive Edge-Triggered) INPUTS OUTPUTS S R CLK Q Q COMMENTS Q Q NO CHANGE (Latch in hold condition) Latch SET Latch RESET NOT ALLOWED (Invalid)

11 D Flip-Flop Flop (Positive Edge-Triggered) Output, Q will follow input, D when CLK is positive edge-triggered

12 Master-Slave J-K J K flip-flop flop (Pulse Triggered)

13 Master-Slave J-K J K flip-flop flop (Pulse Triggered)

14 Master-Slave J-K J K Flip Flop (Truth Table) J K CLK Q Q Comments Q Q HOLD RESET SET Q Q TOGGLE (opposite state)

15 Asynchronous Flip-Flop Flop (review)

16 J-K K Flip-Flop Flop With Asynchronous Input Why ASYNCHRONOUS input???

17 INTRODUCTION COUNTER A group of flip-flops connected together to perform counting operations The number of flip-flops used and the way in which they are connected determine the number of states (Modulus) Normally, uses JK/T flip-flops. D flip-flop also can be used but required many basic gates. Two broad categories according to the way they are clocked :. Asynchronous Counter (Pembilang tak segerak) 2. Synchronous Counter (Pembilang Segerak)

18 ASYNCHRONOUS COUNTER (Pembilang Tak Segerak) Also referred as ripple counter because the input clock pulse is first felt by first flip-flop. flop. This effect cannot get to next flip-flop flop immediately because propagation delay through first flip-flop. flop. One in which the flip-flops flops within the counter do not change states at exactly the same because they do not have a common clock pulse. The clock is applied only for the first flip-flip which is always LSB and the second flip-flip is triggered by the Q output of first flip-flop flop and so on. Because of the input of clock pulses for first flip-flop flop and second flip-flop flop are not at the exact same time then it will cause inherent propagation delay time (tp( tp)

19 Asynchronous counter can be built by using JK flip-flop flop connected in series. Modulus counter (Mod) is the number of unique states that the counter will sequence through Maximum decimal number to be counted : If Mod 6, then the max decimal number is 5 If Mod N = 2 n then the max decimal counted is N-N To determine the required number of flip-flops flops : n flip-flop flop 2 n output = Mod N Counter can be designed to have a number of states in their sequence that is less maximum number and it is called truncated sequence

20 A 2-bit asynchronous binary counter Both flip-flops flops are assumed to be initially RESET (Q low) In digital logic, Q is always the LSB unless otherwise specified

21 The Timing diagram for 2 bit for 2 bit Asynchronous Binary Counter This is a complete timing diagram & propagation delay time are not indicated. Overall timing diagram they are normally omitted for simplicity but it is very important in design & troubleshooting purposes

22 The Binary State Sequence for 2 bit Asynchronous Binary Counter CLOCK PULSE Initially (recycles) Q Q

23 3-bit asynchronous binary counter and its timing diagram for one cycle.

24 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.

25 The Binary State Sequence for a 3-bit Binary Counter CLOCK PULSE Initially (recycles) Q 2 Q Q

26 Four-bit asynchronous binary counter and its timing diagram.

27 An asynchronously clocked decade counter with asynchronous recycling. From to there is no states where Q and Q3 are HIGH at the same time

28 The 74LS93A 4-bit asynchronous binary counter logic diagram. Specific IC for Asynchronous Counter To reset input (Pin numbers are in parentheses, and all J and K inputs are internally connected HIGH.)

29 Two configurations of the 74LS93A asynchronous counter. (The qualifying label, CTR DIV n, indicates a counter with n states.)

30 74LS93A connected as a modulus-2 counter. Immediate after counter goes to count 2 (), it is RESET to

31 SYNCHRONOUS COUNTERS (Pembilang Segerak) All the flip-flops flops in the counter are clocked at the same time by a common clock pulse (external clock) 2 advantages compared to Asynchronous Counter : ) Very less propagation delay time 2) Able to perform counting in random mode (eg :,,3,5,8,,,,3,5,8,..)

32 A 2-bit synchronous binary counter. Assumed initial in binary states meaning that both flip-flops flops are in RESET condition

33 Timing details for the 2-bit synchronous counter operation (the propagation delays of both flipflops are assumed to be equal)

34 Timing diagram for 2-bit synchronous counter

35 A 3-bit synchronous binary counter.

36 Timing diagram for the counter

37 A 4-bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH are indicated by the shaded areas Shades area indicate point the AND gate output HIGH

38 A synchronous BCD decade counter. Counting from till and then reset to at clock pulse

39 Timing diagram for the BCD decade counter (Q is the LSB)

40 The 74HC63 4-bit synchronous binary counter. (The qualifying label CTR DIV 6 indicates a counter with sixteen states.)

41 Timing example for a 74HC63.

42 The 74LS6 synchronous BCD decade counter. (The qualifying label CTR DIV indicates a counter with ten states.)

43 Timing example for a 74LS6.

44 A basic 3-bit up/down synchronous counter

45 Up/Down Synchronous Counter Up Synchronous Counter : UP is set to and AND gate is active causing output OR gate is HIGH. This will cause Q output toggling. The AND gate 2 also active causes Q 2 toggling Because of JK connection from Q output, the counting sequence is UP. Down Synchronous Counter : DOWN is set to and AND gate 3 is active causing output OR gate is HIGH. This will cause Q output toggling. The AND gate 4 also active causes Q 2 toggling Because of JK connection from Q output, the counting sequence is UP

46 Timing Diagram Up/Down Synchronous Counter

47 The 74HC9 up/down synchronous decade counter.

48 Timing example for a 74HC9.

49 General clocked sequential circuit. Information stored on memory & combinational logic is required proper operation of the circuit The memory is called present states at any given time and will advance to a next state on a clock pulse as determined by conditions on the excitation lines

50 State diagram for a 3-bit Gray code counter.

51 Next-state table for a 3-bit Gray code counter. Q Q Q 2 Q Q Q 2 Next State Present State

52 Next-state table for a 3-bit Gray code counter. Output Transitions Flip-flop Inputs Q N Q N+ J K X X X X

53 Examples of the mapping procedure for the counter sequence represented in previous tables

54 K-Maps for present-state J and K inputs.

55 Three-bit Gray code counter.

56 Example: Design a counter with the irregular binary count sequence as shown in the state diagram. Use J-K flip-flops

57 Next-state table Present State Next State Q 2 Q Q Q 2 Q Q

58 Next-state table for a 3-bit Gray code counter. Output Transitions Flip-flop Inputs Q N Q N+ J K X X X X

59

60

61 State diagram for a 3-bit up/down Gray code counter. Refer to the next- state table page 486 from your text book

62 J and K maps for Table 9-. The UP/DOWN control input, Y, is treated as a fourth variable.

63 Three-bit up/down Gray code counter.

64 Cascaded Counter Counter can be connected in cascade to achieve higher- modulus operation The circuit is called CASCADED when an output from last flip-flop flop is connected to input of first flip-flop flop from the following counter. When synchronous counter is connected in cascaded mode, it will produce a propagation delay time. To overcome this problem, most of the synchronous counter is added another input called Enable Input and one output called Terminal Count/ Ripple Clock/ Carry Output Enable Input enabling the process of counting occurs Terminal Count - to synchronous the next counter

65 Two cascaded counters (all J and K inputs are HIGH).

66 Timing diagram for the cascaded counter configuration

67 A modulus- counter using two cascaded decade counters.

68 Three cascaded decade counters forming a divide-by- frequency divider with intermediate divide- by- and divide-by- outputs.

69 Example: Determine the overall modulus of the two cascaded counter for (a) and (b) - For (a) the overall modulus for the 3 counter configuration is 8 x 2 x 6 = For (b) the overall modulus for the 4 counter configuration is x 4 x 7 x 5 = 4

70 A divide-by- counter using two 74LS6 decade counters.

71 A divide-by-4, counter using 74HC6 4-bit binary counters. Note that each of the parallel data inputs is shown in binary order (the right-most bit D is the LSB in each counter).

72 A 3-bit counter with active-high decoding of count 2 and count 7.

73 A basic decade (BCD) counter and decoder.

74 Outputs with glitches from the previous decoder. Glitch widths are exaggerated for illustration and are usually only a few nanoseconds wide.

75 The basic decade counter and decoder with strobing to eliminate glitches.

76 Strobed decoder outputs for the circuit

77 Simplified logic diagram for a 2-hour digital clock.

78 Logic diagram of typical divide-by-6 counter using 74LS6A synchronous decade counters. Note that the outputs are in binary order (the right-most bit is the LSB).

79 Logic diagram for hours counter and decoders. Note that on the counter inputs and outputs, the right-most bit is the LSB.

80 Functional block diagram for parking garage control.

81 Logic diagram for modulus- up/down counter for automobile parking control.

82 Parallel-to-serial data conversion logic.

83 Example : parallel-to-serial conversion timing for the previous circuit

84 Next week Shift Registers - Thank you -