Decade Counters Mod-5 counter: Decade Counter:

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1 Decade Counters We can design a decade counter using cascade of mod-5 and mod-2 counters. Mod-2 counter is just a single flip-flop with the two stable states as 0 and 1. Mod-5 counter: A typical mod-5 counter is shown below. Fig (a) shows the truth table, and how the count increases from 000 to 100, and then back to 000. A typical arrangement consisting of JK flip flops is shown in Fig (b). Working: The FF A toggles every time as long as C is zero. If C is 1 then it remains reset at next clock. This is achieved by keeping K A tied to 1 while J A is connected to C. (C means C-bar). FF B toggles every time A goes from 1 to 0. This is achieved by keeping both J B & K B and tied to 1, while clock input is driven by A. FF C toggles every time BA transitions from 11 to 00. This is achieved by ANDing B with A, and connecting the output to J C, while K C is tied to 1, and FF C is triggered by Clock. The resulting timing waveforms are shown in Fig (b). The modular logic block reference is shown in Fig (d). Decade Counter: The decade counter (mod-10) is used more often. The reason for its popularity stems from the fact that the numbers system that is widely used is the decimal number system. In order to count from 0 to 9 we require 4 flip-flops. One can count 0 to 15 using 4 flip-flops. Out of these 16 states, we should skip 6 states, i.e. after 9 th count, the counter has to reset and fresh count has to start. The counting sequence is summarized by the state diagram shown in the figure below. 1

2 The truth table, timing diagrams and circuit connections are shown below in Fig a,b & c respectively. The counter is a binary counter, i.e. the count sequence increments sequentially from 0000 to A is mod-2 FF/counter, while FFs BCD from mod-5 counter. This arrangement is called a cascade of 2x5 counters. Another arrangement of decade counter is possible, 5x2 counter which is shown below. The count sequence as shown in the truth table is a biquinary sequence, and not a binary sequence. Eg: 1000 means ( 1 = =0) = 6, and ( 1 = =4) = 9. The MSB is either 0/1 which is 0/5, while last three bits are 3-bit binary numbers. 2

3 7490 Decade Counter: Decade counters are available commercially as monolithic ICs. One of them is shown below. It can be operated either as a binary decade counter or as a biquinary decade counter, based on the way inputs A and B are connected. If Q A is connected to input B, then we have a binary counter. If Q D is connected to input A, then we have a biquinary counter. Also keenly observe the MSB and LSB outputs in both cases. (Q A Q B Q C Q D ) from the truth table. 3

4 The importance of using IC decade counters is demonstrated in the figure below, where we show a cascade of three 7490 decade counters. The LSB (rightmost IC) is always clocked by an external clock pulse, which increments the count from 0000 (Decimal 0) for every clock pulse. Once the count reaches 1001 (Decimal 9), the negative going pulse of output D ( 1 to 0, since 1001 to 0000 ) increments the middle counter by 1. So every time the LSB counter counts ten, the middle counter increments. Similarly the MSB counter increments every time middle counter goes from 1001 to Thus we can call this cascade as Hundreds, Tens, and Units counters. We thus have a decimal counter capable of counting from 000 to 999. We can cascade any number of such counters, which are widely used as voltage meters, counters etc. Presettable Counters: The is a synchronous presettable binary up counter. It is a 16-pin DIP and its pinout is shown below. The is a synchronous presettable binary counter which features an internal lookahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CK). The outputs (Q A to Q D ) of the counters may be preset to a HIGH or LOW level. A LOW level at the Load input disables the counting action and causes the data at the data inputs (A to D) to be loaded into the counter on the positive-going edge of the clock. For the the clear function is synchronous and active when low. A LOW level at the clear input sets all four outputs of the flip-flops to LOW level after the next positive- 4

5 going transition on the clock (CK) input. The look-ahead carry simplifies serial cascading of the counters. Both enable inputs (P and T) must be HIGH to count. The synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both enable inputs (P and T) must be HIGH to count. An example of a decade counter is shown below, using NAND gate logic to control input clear. The dotted states are the omitted states, and rest are all stable states (0 to 9). Another popular counter is the Synchronous Up-Down Counter. Its logical diagram with state diagram (+ sequence) is shown below. It can count UP/DOWN based on whether the clock is given to CP U /CP D. The preset inputs are P A to P D while the outputs are Q A to Q D. The carry out is taken from either TC U or TC D. MR is the master reset, while PL is the asynchronous, active low, preset load control input. An example of decade counter using NAND gate and PL is shown below. The difference from previous counter (74163) is that, has an asynchronous PL. So the moment the logic evaluates to 15 ( 1111 ), the counter loads preset input 1001 without waiting for the clock edge. Thus 15 is an unstable state, and is also referred to as a glitch. (shown in dotted circle) 5

6 Counter design as a synthesis problem We need to design a modulo-6 counter, the counting states (memory values) of which are shown in state transition diagram. We need three memory elements or flipflops for this as with n flip-flop we can get at most 2 n number of different counting states. We shall consider the design challenge as that of a finite state machine. Let us select JK flip flops, and try to list the state transition diagram, and also the required values of inputs J & K for all flip flops. C n B n A n C n+1 B n+1 A n+1 J C K C J B K B J A K A X 0 X 1 X X 1 X X X X 0 1 X X X 1 X X 0 0 X 1 X X 1 0 X X 1 The observation of J A and K A leads us to the solution J A =K A =1. We shall use K-map technique to solve for other inputs as shown below. 6

7 The final circuit diagram is shown below. The carry out (Y) is generated by ANDing of complement outputs of all flip flops. Whenever the counter transitions from 101 to 000, the complement outputs are

8 D/A Conversion and A/D Conversion A digital-to-analog converter, or simply DAC, is a semiconductor device that is used to convert a digital code into an analog signal. Digital-to-analog conversion is the primary means by which digital equipment such as computer-based systems are able to translate digital data into real-world signals that are more understandable to or useable by humans, such as music, speech, pictures, video, and the like. It also allows digital control of machines, equipment, household appliances, and the like. Binary equivalent weight: The fraction of weight pushed by a binary digit across voltage. The requirement of conversion from digital to analog for a 3 bit system is shown below. If the number of bits increases, the bit weights also modify as shown below for a 4-bit DAC method. For a 3-bit system the LSB weight is 1/7, and for a 4-bit system it is 1/15. Thus, in general the weight of LSB starts from 1 / (2 n -1). The requirement is that of a resistive ladder that can generate voltages as shown below. The resistor divider must do two things to change the digital input into an equivalent analog output voltage. 8

9 The 2 0 bit must be changed to +1V, and 2 1 bit must be changed to +2V, and 2 2 bit must be changed to +4V. These three voltages representing the digital bits must be summed together to form the analog output voltage. We shall study 2-methods for this resistive divider, Variable Resistor and Binary Ladder Networks. Variable Resistive Divider The variable resistive divider network shown below is for a 3-bit DAC. The LSB has a resistance of R 0, while all successive resistors are half of their previous resistor. R L is load resistor which is very large to prevent loading, and can thus be ignored in calculations. An example for input of 001; is shown below with connections and necessary voltage equations using Millers theorem. Thus the analog output is +1 V which is desired for a digital input of 001, which is 1 LSB. In general for any other digital input, the value of analog output is given by the following expression. Disadvantages: Difficulty in choosing resistors, and uneven current distribution (LSB has lowest current, while MSB has highest current). 9

10 Binary Ladder Network The binary ladder is a resistive network whose output voltage is a properly weighted sum of the digital inputs. It consists of only R and 2R values of resistors, and the current is uniform for all inputs. The example input of 1000 leads to the following circuit simplifaication, and hence output voltage. Similarly, the analog outputs for each bit as weight can be calculated, and is shown in below table. In general for any other digital input, the value of analog output is given by the following expression. 10

11 4-bit D/A Converter The actual circuitry of DAC includes other components apart from resistive divider as shown below for a 4-bit D/A converter. The registers load the inputs to the resistive divider, while the level amplifiers ensure appropriate voltage levels to minimize errors during conversion. D/A Accuracy and Resolution The accuracy of the D/A converter is primarily a function of the accuracy of the precision resistors used in the ladder and the precision of the reference voltage supply used. Accuracy is the measure of how close the actual output voltage is to the theoretical output voltage. Resolution, on the other hand, defines the smallest increment in voltage that can be discerned, which is LSB. Resolution is primarily a function of the number of bits in the digital input signal. 11

12 Simultaneous A/D Conversion The process of converting an analog voltage into an equivalent digital signal is known as analog-to-digital conversion. There are various techniques for conversion, based on conversion time and hardware resources needed. Some of them even use a D/A converter in the architecture. The concept of simultaneous conversion is the simplest one. Shown below is the logic for A/D conversion. The three comparators are connected to the analog input voltage simultaneously, while their other inputs are V/4, V/2 and 3V/4 as shown. If the input analog voltage is between 0 and V/4, then all the comparators output are 0. The outputs change as shown in the table (b). This circuit can detect four voltage ranges, and thus needs only 2-bits. The final arrangement of decoding the three comparator outputs to two binary output signals is shown below. Since the analog input is simultaneously converted to digital output, this converter is also called Flash A/D Converter. It is the fastest of all A/D comparators. Disadvantage: As the number of bits increase the number of comparators needed also increases. For eg: A 10-bit ADC needs =1023 comparators, which is unmanageable. 12

13 Counter type A/D Converter This architecture needs a single comparator and a DAC as shown below. The counter starts with all 0 s, and is incremented till it becomes equal to the analog input. This is achieved by first converting the counter output to analog using a DAC, and using a comparator as shown. Once the DAC output becomes either equal or slightly greater than analog input voltage, the comparator stops further increment of counter, and the counter is now the digital equivalent of analog input. Disadvantage: Conversion time is very slow, and has a worst case value of 2 n comparisons. Also every time the counter begins from all 0 s. For eg: A 10-bit ADC needs 1024 comparisons. If each comparison needs one clock period, then for a 1 MHz clock the conversion time is 1024 μs. Continuous A/D converter The need to start from all 0 s for the counter does not arise, if we can track the new analog input to be converted from our previous count itself. In this case, we may need an up/down counter. The necessary circuit arrangement is shown below. (Tracking ADC) 13

14 Disadvantage: Even though the conversion time is just one clock cycle once the circuit tracks the analog input, we cannot use a single ADC to convert multiple channels of analog input, where we essentially use a multiplexer. Since we lose the tracking information once we multiplex to another analog input. The solution is SAR ADC. Successive Approximation Converter The circuit diagram and logic explanation (hunting) is shown below. The only change in this design is a very special counter circuit known as a successiveapproximation register. Instead of counting up in binary sequence, this register counts by trying all values of bits starting with the most-significant bit and finishing at the leastsignificant bit. Throughout the count process, the register monitors the comparator s output to see if the binary count is less than or greater than the analog signal input, adjusting the bit values accordingly. The way the register counts is identical to the trialand-fit method of decimal-to-binary conversion, whereby different values of bits are tried from MSB to LSB to get a binary number that equals the original decimal number. The advantage to this counting strategy is much faster results: the DAC output converges on the analog signal input in much larger steps than with the 0-to-full count sequence of a regular counter. A/D Accuracy and Resolution Since the A/D converter is a closed-loop system involving both analog and digital systems, the overall accuracy must include errors from both the analog and digital positions. In determining the overall accuracy it is easiest to separate the two sources of error. Quantization error: The error inherited in any digital system due to the size of the LSB. Differential linearity: It is the measure of the variation in voltage-step size that causes the converter to change from one state to the next. 14