Lab #12: 4-Bit Arithmetic Logic Unit (ALU)

Transcription

1 Lab #12: 4-Bit Arithmetic Logic Unit (ALU) ECE/COE 0501 Date of Experiment: 4/3/2017 Report Written: 4/5/2017 Submission Date: 4/10/2017 Nicholas Haver 1 H a v e r

2 PURPOSE The purpose of this lab was to design and build an arithmetic logic unit, and incorporate it into our existing register file from Lab 11. In doing this, we created a simple computer capable of storing values and performing a variety of arithmetic and logic operations on the values. Each operation required two 4-bit ALU inputs, and the ALU produced a single 4-bit output. After the circuit was designed in Altera Quartus II, a series of programs were used to test circuit functionality. These programs were waveforms designed to carry out a specific operation on a specific pair of operands. Both logic operations, such as AND and XOR, and arithmetic operations, such as addition and multiplication, were carried out in the test programs. METHOD 1) After examining the provided block diagram in Figure 1, the 4-bit latch was designed on paper, then using Altera Quartus II with D flip-flops, and was then tested using a vector waveform. Figures 2 and 3 show the 4-bit latch schematic and test waveform. 2) Based on the block diagram, the Altera Quartus schematic was revised to include the latch, arithmetic logic unit (ALU), and 4x2: data selector. A writeback datapath between the ALU output and data selector was also added. The Quartus schematic can be seen in Figure 4. 3) Using a vector waveform, shown in Figure 5, schematic functionality was verified by simulating four operations, two logic and two arithmetic. For each operation, two operands were loaded into two different registers, and the output was written to a third register. Operations, function select codes, mode control inputs, data inputs, and data outputs are shown in Table 1. 4) The next program, implemented in the form of a vector waveform, allowed the ALU to sum four hexadecimal digits, and store the result in one of the registers. Table 2 shows the function select code, mode control input, data inputs, data output and final register values of this operation. Figure 6 shows the vector waveform generated used for this simulation. 5) The final program allowed the ALU to multiply two hexadecimal numbers ad store the lower four bits of the result to a register. Prior to implementing this operation in the form of a vector waveform, a pseudo-assembly code was written to improve the accuracy and efficiency of the waveform inputs to be implemented. Table 3 shows the pseudo-assembly code and final register values for the multiplication process. 6) Based on the pseudo-assembly code, a vector waveform file, shown in Figure 7, was constructed to implement the multiplication. Periodic checkpoints in which all register values were read out were included to simplify any necessary debugging. Table 4 shows the function select code, mode control input, data inputs, data output and final register values of this operation. Due to laboratory time constraints, the schematic was only simulated to calculate the first partial product. However, based on the pseudo-assembly code, the method used could be continued with each additional bit of the first multiplicand, and the values could be summed to complete the multiplication. 7) Based on the Quartus schematic, the ALU circuit was implemented on a protoboard, adding to the register file constructed in Lab 11. All of the control inputs were implemented using de-bounced switches using 7400 Quad NAND integrated circuits. The de-bounced switch schematic is shown in Figure 8. Table 5 details the integrated circuits used in implementing the ALU/register file. Specification for the integrated circuits are shown in Figures ) The operations discussed in Steps 3, 4, and 6 were carried out on the circuit, and evaluated using an Intronix LogicPort logic analyzer. Logic analyzer waveforms are shown in Figures H a v e r

3 RESULTS Figure 1: ALU/Register Block Diagram for Lab #12 Figure 2: Altera Quartus 4-Bit Latch Schematic 3 H a v e r Figure 3: Altera Quartus 4-Bit Latch Test Waveform

4 Figure 4: Altera Quartus ALU Schematic Figure 5: Vector Waveform for ALU Functionality Verification 4 H a v e r

5 Operation Function Select Mode Control Input A Input B Output A OR B A XOR B A plus B (A AND B) minus Table 1: Inputs, Outputs, and Control Signals for ALU Functionality Verification Operation Function Select Mode Control Data Inputs Data Output Final Register Values A plus B plus C plus D (3) 1011 (11) 1011 (11) 0101 (5) 0101 (5) 0010 (2) 0010 (2) 0001 (1) 0001 (1) Table 2: Inputs, Outputs, and Control Signals for ALU 4 Hex Sum Program Figure 6: Vector Waveform for ALU 4 Hex Sum Program 5 H a v e r

6 Data Input: A R0 Data Input: B R1 Data Input: 0001 R2 R2 latch ALU OP: R1 AND latch 000b 0 R2 R2 latch ALU OP: R0 AND latch 000 a 0b 0 R3 R2 latch ALU OP: A plus A*: R2 / latch 00 b 0 0 R2 //shift 000b 0 left R2 latch ALU OP: R0 AND R2 00 a 1b 0 0 R2 R2 latch ALU OP: R2 OR R3 00 a 1b 0 a 0b 0 R2 Data Input 0001 R3 //This value remains on DIP switches ALU OP: R1 AND R3 000 b 0 R3 ALU OP: A plus A*: R3 / latch 00 b 0 0 R3 //shift 000b 0 left ALU OP: A plus A*: R3 / latch 0 b 0 00 R3 // shift 00b 00 left ALU OP: R0 AND R3 0 a 2b 0 00 R3 ALU OP: R3 OR R2 0 a 2b 0 a 1b 0 a 0b 0 R2 ALU OP: R3 AND R1 000 b 0 R3 ALU OP: A plus A*: R3 / latch 00 b 0 0 R3 ALU OP: A plus A*: R3 / latch 0 b 0 00 R3 ALU OP: A plus A*: R3 / latch b R3 ALU OP: R0 AND R3 a 3b R3 ALU OP: R2 OR R3 a 3b 0 a 2b 0 a 1b 0 a 0b 0 R2 //First Partial Product! ALU OP: A plus A*: R3 / latch 0010 R3 ALU OP: R1 AND R3 R3 R0 latch ALU OP: A plus A*: R0 / latch a 2a 1a 00 R0 //A is shifted left permanently ALU OP: R3 AND R0 00 a 0b 1 0 R3 ALU OP: R3 OR R2 R2 ALU OP: A plus A*: R3 / latch 0010 R3 ALU OP: R3 AND R1 00b 10 R3 ALU OP: A plus A*: R3 / latch 0b 100 R3 ALU OP: R0 AND R3 0 a 1b 1 00 R3 ALU OP: R2 OR R3 R2 ALU OP: A plus A*: R3 / latch 0010 R3 ALU OP: R3 AND R1 00b 10 R3 ALU OP: A plus A*: R3 / latch 0b 100 R3 ALU OP: A plus A*: R3 / latch b 1000 R3 ALU OP: R3 AND R0 a 2b R3 ALU OP: R3 OR R2 R2 ALU OP: A plus A*: R3 / latch 0010 R3 ALU OP: A plus A*: R3 / latch 0100 R3 R0 latch ALU OP: A plus A*: R0 / latch a 1a 000 R0 ALU OP: R1 AND R3 0 b 2 00 R3 ALU OP: R0 AND R3 0 a 0b 2 00 R3 ALU OP: R2 OR R3 R2 ALU OP: A plus A*: R3 / latch 0010 R3 ALU OP: A plus A*: R3 / latch 0100 R3 ALU OP: R3 AND R1 0b 200 R3 ALU OP: A plus A*: R3 / latch b 2000 R3 ALU OP: R3 AND R0 a 1b R3 ALU OP: R3 OR R2 R2 ALU OP: A plus A*: R3 / latch 0010 R3 ALU OP: A plus A*: R3 / latch 0100 R3 ALU OP: A plus A*: R3 / latch 1000 R3 ALU OP: R3 AND R1 b 3000 R3 R0 latch ALU OP: A plus A*: R0 / latch a 0000 R0 ALU OP: R0 AND R3 a 0b R3 ALU OP: R3 OR R2 R2 //RESULT: R2 = R0 x R1 ***Final Register Values*** R0: a 0000 R1: B R2: (a 3b 0+a 2b 1+a 1b 2+a 0b 3) (a 1b 1 + a 2b 0+a 0b 2) (a 1b 0 + a 0b 1) a 0b 0 R3: a 0b Table 3: Pseudo-Assembly Code for Hexadecimal Value Multiplication 6 H a v e r

7 Figure 7: Vector Waveform for First Partial Product of Hexadecimal Multiplication Operation Function Selects Mode Control Data Inputs Data Output Final Register Values A x B 1011 (A AND B) (5) 0101 (5) 0101 (5) 1100 (A plus A*) (3) 0011 (3) 1001 (A plus B) (5) 0000 (0) Table 4: Inputs, Output, and Control Signals for First Partial Product of ALU Hex Multiplication Program Figure 8: De-Bounced Switch Control Input Schematic 7 H a v e r

8 Integrated Circuit Use in ALU/Register File Quad 2/1 Data Selector (Multiplexor) Select register input between user data input and ALU output x4 Register File Store 4 hexadecimal (4-bit) data inputs, ALU operands, and ALU outputs Bit Up/Down Binary Counter Cycle through register addresses to read and write BCD to 7-Segment Decoder Drive 7-segment LED displays at register output and ALU output Arithmetic Logic Unit Perform logic or arithmetic operations based on function select inputs 7474 Dual D Flip-Flop 4-Bit latch for ALU operand input 7400 Quad 2-Input NAND Gate De-bounced switch for control inputs 7-Segment LED Display Display hexadecimal values at register output and ALU output Table 5: Integrated Circuits Used to Implement ALU and Register File Figure 9: Quad 2/1 Data Selector (Multiplexor) Pin Diagram and Descriptions Figure 10: 4x4 Register File Pin Diagram and Descriptions 8 H a v e r

9 Figure 11: 4-Bit Up/Down Binary Counter Pin Diagram and Descriptions Figure 12: BCD to 7-Segment Decoder Pin Diagram and Descriptions Figure 13: Arithmetic Logic Unit Pin Diagram and Descriptions 9 H a v e r

10 Figure 14: Dual D Flip-Flop Pin Diagram and Logic Diagram Figure 15: Quad 2-Input NAND Gate Pin Diagram and Logic Diagram Figure 16: 7-Segment LED Display Wiring Diagram 10 H a v e r

11 Figure 17: Logic Analyzer Waveform for "1101 OR 0110 = 1111" Figure 18: Logic Analyzer Waveform for "1001 XOR 0100 = 1101" As with the Quartus simulation, four operations were carried out to verify circuit functionality. Figure 17 shows that 1101 (13) OR 0110 (6) = 1111 (15). In Figure 18, 1001 (9) XOR 0100 (4) = 1101 (13). Figure 19 shows that 0101 (5) plus 0001 (1) = 0110 (6). Lastly, in Figure 20, [0011 (3) AND 0010 (2)] minus 1 = 0001 (1). Figure 19: Logic Analyzer Waveform for "0101 plus 0001 = 0110" 11 H a v e r

12 Figure 20: Logic Analyzer Waveform for "(0011 AND 0010) minus 1 = 0001" Figure 21: Logic Analyzer Waveform for First Partial Product of Hexadecimal Multiplication "0101 x 0011 = 1111" 12 H a v e r

13 CONCLUSION The purpose of this lab was to design and build an arithmetic logic unit, and incorporate it into our existing register file from Lab 11. In doing this, we created a simple computer capable of storing values and performing a variety of arithmetic and logic operations on the values. Using Altera Quartus, a schematic was tested using programs in the form of vector waveforms with inputs and control signals. Logic operations and arithmetic operations, such as addition and multiplication were carried out both in Quartus and on the protoboard. The time consumption and complexity of these operations, particularly multiplication, is a testament to the marvel that is modern computing. In Lab 13, the circuit constructed in Labs 11 and 12 will be realized on a field programmable gate array, or FPGA. Circuit characteristics will be established in PC software, which will then be downloaded onto the FPGA. REFERENCES Dr. Alex Jones s laboratory instructions ECE/COE 0501 Lab Manual Data sheets for 74157, 74670, 74193, 74247, 74181, 7474, and 7400 integrated circuits 7-Segment LED display wiring diagram Lab Partner: Jenn Gingerich 13 H a v e r