2 The Essentials of Binary Arithmetic

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1 ENGG1000: Engineering esign and Innovation Stream: School of EE&T Lecture Notes Chapter 5: igital Circuits A/Prof avid Taubman April5, Introduction This chapter can be read at any time after Chapter 1 ( Induction: Instruments, Components and Circuits ). At the end of that document, we introduced elementary digital logic and showed how it could be constructed from simple combinations of transistors. Many of you will, by now, have constructed and tested these logic circuits in the laboratory. Where your project calls for digital logic, you are recommended to use the TTL logic IC s (74LSxxx series chips) whose data sheets appear on the course s VISTA web-site under the "atasheets" organizer. These devices use BJT s (Bipolar Junction Transistors) which tend to be more robust (electrically) than the CMOS transistors which are used in most VLSI (Very Large Scale Integration) digital IC s. The main disadvantage of BJT s is that they consume more power than CMOS transistors; on the other hand, they are harder to damage and their outputs can drive significant loads (e.g., enough to power an LE). These properties both recommend them for an introductory design course such as this. Where appropriate, we will refer to specific TTL part numbers. However, the main purpose of these notes is to introduce you to three key building blocks of digital design: 1) binary arithmetic; 2) stateless digital logic; and ) clocksynchronized state management. There are many excellent formal tools for digital design, but we will not try to introduce them here. Instead, the main purpose of these notes is to give you the minimum set of tools you need to do interesting things. When formal tools are introduced in later courses, you will be able to appreciate them more fully, having already designed circuits without them. 2 The Essentials of Binary Arithmetic igital logic works with binary signal representations, in which a high voltage level is typically interpreted as a 1, while a low voltage level is typically inter- 1

2 c Taubman, 2007 igital Circuits (ENGG1000) Page 2 preted as a 0. For TTL logic, the supply rails are at 0V (GN)and5V (V CC ), a high input voltage level is considered to be anything over about 2V andalow input voltage level is considered to be anything under about 0.8V. Signals in between these limits have uncertain logic levels. Such voltage levels should not appear in a digital circuit, except when signals are transitioning from high to low, or from low to high. This is because digital logic devices are essentially amplifiers with high voltage gains, producing output voltages which are always close to one of the rail voltages. Since digital logic represents information through 1 s and 0 s, it is important that we have a way to represent more general numerical quantities using only 1 s and 0 s. To this end, non-negative integers are always represented in base-2 (as opposed to base-ten). For example, the integer value ten is represented in base-2 as 1010b. The suffix b is used here to make it clear that these are binary digits. As in the more familiar base-ten number system, the right-most digit represents units; moving to the left, the digits represent multiples of 2, 4, 8 and so forth. We use the term bits to refer to the digits in a base-2 (or binary) numeric representation. The right-most digit is identified as the least significant bit (or LSB). Some of the TTL devices you might possibly use for your design project which accept or produce binary numbers are: 74LS161: This is a binary 4-bit counter IC. It outputs four digital signal lines, commonly denoted 0, 1, 2 and, which identify the current value of the count. 0 is the least significant bit (LSB) of the count, while is the most significant bit (MSB). This means that the base-2 count value is b and the integer value of the count can be written as Check (using the data sheets) that you understand what happens when the count reaches the maximum possible value of 15 = 1111b. 74LS18: This is a -8 line digital decoder IC. It accepts a -bit input, identified by data bits 0, 1 and 2. Together, these represent an integer in the range 0 to 7, where 0 is the LSB and 2 is the MSB. This integer is the index of one of 8 output data lines which goes low, leaving the other seven high. 74LS151: This is a 1 of 8 digital multiplexor IC. It again accepts a -bit index, which identifies one of 8 binary input lines whose value is to be copied to a single binary output. There is, of course, much more we could say about binary arithmetic. We could describe the representation of signed integers (integers which can be positive or negative). We could also describe the representation of fractional quantities (analogous to decimals) and floating point values, and we could discuss arithmetic on these quantities (addition, subtraction, multiplication and so forth). Much of this, however, would be a distraction at this introductory stage.

3 c Taubman, 2007 igital Circuits (ENGG1000) Page AN OR XOR NAN NOR INVERT Figure 1: Basic logic gates. Gates: Building Blocks for igital Logic In Chapter 1, we introduced a number of 2-input, 1-output logic gates. In particular, we showed how NOR and NAN gates could be constructed using transistors; you might like to review that material before continuing. Four basic logic gates with which you should be familiar are the AN gate, the OR gate, the XOR gate, and the INVERTER; their schematic representations appear in Figure 1, along with the NAN and NOR gates from before. TheANgateoutputsa1 (high) if and only if both of its inputs are 1. The OR gate outputs a 1 if either or both of its inputs is a 1. The XOR (exclusive OR) gate outputs a 1 if either, but not both of its inputs are 1. The inverter has the obvious function of outputting a 1 (high) when its input is 0 (low) and outputting a 0 (low) when its input is 1 (high). Logic functions are often prescribed (e.g., in data sheets) using truth tables, so it is good that you get used to reading them. Truth tables for the AN, OR, XOR and NAN gates are shown below. AN Gate Inputs Out OR Gate Inputs Out XOR Gate Inputs Out NAN Gate Inputs Out All of the logic functions shown in Figure 1 can be obtained by a suitable combination of NAN gates, or by a suitable combination of NOR gates. As an example of this, Figure 2 shows how the OR and XOR gates can be implemented using only NAN gates. See if you can do the rest yourself.in view of this fact, you may ask why we even bother to create logic symbols for any more than one gate. There are two answers to this:

4 c Taubman, 2007 igital Circuits (ENGG1000) Page 4 in1 out in1 out in2 in2 OR XOR Figure 2: Implementing OR and XOR gates using NAN gates. 1. The gates in Figure 1 provide logical operations which are natural for certain tasks. Even though the AN gate can be implemented using three NOR gates, for example, it is more natural to think in terms of the output being on if and only if both inputs are on. As another example, it turns out that numerical addition and subtraction operations are most easily understood with the aid of XOR gates. Consider, for example, the addition of two integers represented using binary digits (base-2). Some thought should convince you that the LSB (least significant bit) of the result is the XOR of the LSB s from each input integer. 2. The TTL logic IC s you are most likely to work with for your project provide packaged collections of each of the gates shown in Figure 1. If you really need an OR operation, you could obtain this function using three of the four NAN gates in a 74LS00 package. However, you could obtain the function more naturally by using only one of the four OR gates provided by a 74LS2, with less wires and less things to go wrong..1 Bubbles on the Schematic and Active Low Signals You have probably figured out by now that the bubbles (small circles) in the schematic representation of digital logic indicate that a signal is inverted. You can see this in the outputs of the NAN and NOR gates. The INVERTER is actually a buffer (the triangle) with an inverted output (the bubble). You will also see bubbles used at the inputs to certain logic gates, meaning that the input is considered to be inverted before it enters the logic gate. It follows that an AN gate with bubbles at all inputs and at the output is actually an OR gate. Another, equally valid way to interpret the bubbles is as a reversal of the convention that high voltages refer to logical values of 1, while low voltages refer to logical values of 0. When a bubble appears at the input or output of a gate or logic circuit, you can interpret this as meaning that a logical 1 is now represented by a low voltage, while a logical 0 is represented by a high voltage. Many of the TTL logic IC s you might investigate for your project adopt this perspective when describing various control inputs. For example, the 74LS161 has a Load Enable input pin which is said to be Active Low and is shown on the schematic with a bubble at its input (see the data sheets). This signifies

5 c Taubman, 2007 igital Circuits (ENGG1000) Page 5 V V out V in gate input threshold t Figure : Behaviour of logic gate with noisy input. that a low voltage level on the Load Enable pin means that the load function is on logically 1 or true..2 Gates with Hysteresis Logic gates are essentially high gain amplifiers. When the input voltage is in the vicinity of a threshold, call it V T, small changes in the input voltage will cause large changes in the output voltage. igital circuits are not designed to operate with gate input voltages near V T, since this renders the circuit very sensitive to small fluctuations caused by electronic noise, supply rail variations and so forth. Also, the actual value of V T tends to vary somewhat from device to device. Figure illustrates the problem of a noisy input signal whose voltage dwellsforsometimeinthevicinityofv T. As you can see, small changes in V in can then cause the detected logic level to jump wildly between the low (0) and high (1) states. The problems described above do not normally occur when gates are driven from the outputs of other gates, since gate outputs are designed to slew quickly and monotonically between the low and high states. Problems can occur, however, when the signal driving a gate has to travel over a large length of wire; in this case, electromagnetic effects associated with current traveling in long conductors can cause oscillations in the signal voltages, whose magnitude might exceed the slew rate of the signal. A common source of logic level uncertainty occurs when you connect gate inputs to opamps, switches, R-C circuits, or other analog circuit components. To avoid the problem observed in Figure, it is a good idea to use gates whose input circuitry contains hysteresis. To understand hysteresis, consider the circuitshowninfigure4.observefirstly that R 1 and form a resistive divider network, so that V S = V in + R 1 R 1 + (V out V in ) = V in R V out R 1 R 1 +

6 c Taubman, 2007 igital Circuits (ENGG1000) Page 6 V in R 1 V s V out Figure 4: Non-inverting gate (buffer) with hysteresis. Now suppose the non-inverting gate (buffer) shown in this circuit has a threshold voltage of V T and that V out is currently in the high state let s say for simplicity that V out = V CC. Then in order for the gate to transition to the low state, the input must force V S <V T,meaningthat R 1 V in <V T V CC. R 1 + R 1 + Equivalently, we need V in <V T,min,where µ V T,min = 1+ R 1 R 1 V T V CC. Suppose, on the contrary, that the output is currently in the low state say for simplicity that V out = V CC. Then in order for the gate to transition to the high state, we require V S = V in >V T. R 1 + Equivalently, we need V in >V T, max,where µ V T,max = 1+ R 1 V T The important thing is that the positive going threshold V T,max is greater than the negative going threshold, V T,min.Thedifference, V T,max V T,min is known as the gate s hysteresis. Hysteresis is created by positive feedback. That is, high values of V out serve to pull V S even higher, so that the input voltage has to go much lower in order to reverse the logic level. Similarly, low values of V out pull V S even lower, so that the input voltage has to go much higher in order to change things. Make sure that you understand why this solves the problem seen in Figure. Gateswithhysteresisareoftendepictedwiththespecialsymbolshownon the right in Figure 4. The 74LS12 is a useful TTL component whose inputs have hysteresis. Another useful TTL component with hysteresis is the 74LS244 octal buffer, which is used in the alek enemy target at the external interfaces.

7 c Taubman, 2007 igital Circuits (ENGG1000) Page 7. Unused Inputs It quite commonly happens that you do not care what the value of some input to a gate or digital IC is. For example, you might only use of the 4 NAN gates provided by a 74LS00 IC. When working with TTL logic chips, it is OK to leave these unused inputs disconnected. With CMOS devices, however, all unused inputs should generally be connected to ground, to avoid static electric discharge which can potentially damage the device. If a TTL input is left unconnected, it will tend to take on a logical 1 (high) state. However,ifyoudoneedthevaluetobeseenasa1, itisbesttotiethe input to V CC, since this will improve robustness to rapid transitions in other parts of the circuit 1. If you need the input to be seen as a 0, youmusttieitto 0V (GN)..4 TTL Output Considerations As a general rule, you should avoid connecting the output from one logic gate directly to the output from another logic gate. This is generally a pretty senseless thing to do anyway. There is, however, one important exception. Some devices have what are known as tri-state (or -state) outputs. Tri-state outputs can be placed in a special high impedance (high-z) state, which is neither low nor high. In the high-z state, the output driving transistors are all disabled and the output line is essentially disconnected. This allows another device s output to drive the same line. Tri-state devices are designed to share the responsibility for driving output lines with other tri-state devices, but at most one of the devices whose output is attached to a given line should be enabled (i.e., not in the high-z state). The 74LS244 device, for which data sheets are supplied on the VISTA site, offers tri-state outputs with output-enable controls. Although the output from a single gate can drive the inputs to many other gates, there is a limit to the number of inputs which one output can drive. For TTL devices, this limit is determined by the amount of current required to maintain a gate input in the low or high state. The number of inputs which canbedrivenbyasingleoutputisknownasthefan-out factor. The fan-out factor of a 74LS00 NAN gate is about 20, for example. Some devices are specially designed to supply (and sink) larger output currents so that they can drive more gates or heavier loads. One example of this is the 74LS244 octal line driver component. As you might expect, all this information is available from the data sheets..5 Gate elay So far, we have considered only the static properties of logic gates. In practice, it takes some time for changes at the input to propagate to be reflected at the output of a logic gate. This time may be on the order of a few nanoseconds 1 Many students experience unreliable behaviour from their designs precisely because they have not realized that the high state of an unconnected pin is unreliable

8 c Taubman, 2007 igital Circuits (ENGG1000) Page 8 S R Figure 5: Set-reset flip-flop. for discrete TTL logic chips, down to a few tens of picoseconds for the internal gates within a high speed micro-processor. The principle origin of this delay is capacitance. Recall from Chapter that capacitance slows circuits down. Capacitance appears in deliberately manufactured capacitors, but it also appears wherever conductors with different voltages are close to each other. We refer to this as stray capacitance and note that it is impossible to entirely eliminate all stray capacitance from a circuit. 4 Flip-Flops: State and Synchronous esign 4.1 From Gates to Flip-Flops By clever use of positive feedback, we can make combinations of gates which remember the state of some previous input. The easiest way to illustrate this is with the set-reset configuration shown in Figure 5. Notice firstly the use of bars over the S and R inputs. This is another way of indicating on the schematic that these input lines do what their names suggest (S for set and R for reset ) when they are low, rather than high i.e., they are active when low. To understand this circuit, suppose that both inputs are high (inactive). We claim that the outputs and must hold opposite digital values. If is high, the lower NAN gate forces low and this forces the upper NAN gate to keep in the high state. Similarly, if is low, the lower NAN gate forces high, so that the upper NAN gate keeps in the low state. If both and happenedtobeinthehighstate,orbothhappenedtobeinthelowstate,say immediately after power up, they would fight against each other and one of or would wind up in the high state, with the other in the low state after a very short time (on the order of the gate delay). This is because the internal amplification gains associated with the two gates can never be exactly identical to infinite precision, so one is bound to win over the other. Now suppose that the S input goes low (active), but R remains high (inactive). It is easy to see that this forces into the high state (set) regardless of and that the lower NAN gate will force low shortly thereafter. Similarly, if R goes low (active) when S is high, a reset operation is performed, forcing to 0 and to 1. Once S and R are returned to the high (inactive) state, the flip-flop retains the state produced by the most recent set or reset operation. The condition in which both S and R are low at the same time is not of interest

9 c Taubman, 2007 igital Circuits (ENGG1000) Page 9 CLK Figure 6: Positive edge-triggered flip-flop. to us. The term flip-flop is used to refer to a device that can be flipped to one state or ( flopped to) another, where both states are stable. By stability, we mean that the state is retained after the stimulus (flipping or flopping) is removed. You will come to use the term flip-flop for any device which can remember its state. The set-reset flip-flop described above can be used to build a much more interesting device known as the flip-flop, as shown in Figure 6.For the present course, it is not important that you know exactly how this circuit achieves its ends, but for the interested student we provide the following brief explanation. When the CLK (read clock ) input is low, the first pair of NAN gates allow and its inverse to pass through to the first set-reset flip-flop, so that its upper output is set (if is high) or reset (if is low). uring this time, the value of affects the first set-reset flip-flop, but has no impact on the second set-reset flip-flop, whose outputs are denoted and. When the CLK input goes high, the input no longer has any impact on the state of the first set-reset flip-flop. However, the third pair of NAN gates now pass the values stored in the first set-reset flip-flop through to the second. Based on this brief description, you should be able to convince yourself that the and outputs can only change on the rising edge of the CLK input (i.e., immediately after CLK goes from low to high). When this happens, the output assumes the value which was present at the input immediately before the clock transition, while holds its inverse. Apart from the period immediately prior to the rising edge of the clock, the value at the input has no impact whatsoever on the outputs. You don t generally build flip-flops yourself, from discrete gates. Instead, you might use a TTL IC such as the 74LS74, which packages up two flip-flops for you. Alternatively, the 74LS74 is an octal flip-flop which memorizes the state of 8 separate input bits whenever its clock signal transitions from low to high, retaining their values on 8 output pins until the next positive going transition of the clock.

10 c Taubman, 2007 igital Circuits (ENGG1000) Page From Flip-Flops to Sequential Machines The flip-flop just described plays an immensely important role in digital circuit design. Virtually all complex digital circuits employ a common clock (CLK) signal, driven by a stable oscillator. The clock signal in your home computer s micro-processor may execute billions of cycles per second (i.e., Gigahertz). The important thing is that all flip-flops in the circuit receive the same clock signal. This means that their outputs all change at essentially the same time (e.g., on the positive going clock edge). These outputs drive networks of logic gates to produce new inputs for the flip-flops. The logic network has the best part of an entire clock cycle to generate stable values for these new inputs, which become the flip-flop outputs on the next clock edge. Circuits of this form are known as state machines or synchronous digital circuits. This repetitive process of inputs moving to outputs, which generate new inputs, might seem rather pointless at first. It is, however, the key to accomplishing a great wealth of functionality with a small amount of logic. To understand this, consider first the implementation of a 4-bit digital counter, as shown in Figure 7. The output of the counter appears at the outputs of the four flip-flops, with the LSB at the top and the MSB at the bottom. The logic network which connects the outputs of the flip-flops back to their inputs consists of four XOR gates and four AN gates. Together, these implement an adder, whose XOR outputs hold the numeric result obtained by adding the 4-bit input (obtained from the outputs of the flip-flops) to the 1-bit value represented by the COUNT ENABLE signal. See if you can verify that this network does indeed perform the claimed arithmetic. In any event, you should be able to easily verify that when COUNT ENABLE is 0 (low), the signal fed back to the flip-flop inputs is identical to that at the flip-flop outputs, so nothing changes from clock edge to clock edge. When COUNT ENABLE is 1 (high), the count value appearing at the flip-flop outputs increases by 1 immediately after each rising clock edge, wrapping around back to 0000 after 1111b. Now suppose we replace the logic network in Figure 7 with one which is able to add two 4-bit numbers together, as shown in Figure 8. The adding network is only a little more complex than the one shown explicitly in Figure 7, but we do not need to worry about its inner workings here. In this new circuit, the 4-bit integer represented by 0 (LSB) through (MSB) is added to the 4-bit value stored in the flip-flops, represented by 0 (LSB) through (MSB). The result becomes the new value stored by the flip-flops on the next rising clock edge. By feeding this circuit with a different numeric input in each clock cycle, our circuit will add all of the numbers in sequence. To achieve this behaviour with a single network of logic gates, we would need to replicate the adder network many times, as suggested by the arrangement on the right hand side of Figure 8. The lesson to be learned here is that a small amount of logic can accomplish a great deal when deployed within a synchronous digital circuit. In fact, it is only a relatively small step from here to build a central processing unit (CPU) which sequentially carries out pre-programmed instructions, one per clock cycle i.e., a computer. igital design engineers do build CPU s (micro-processors),

11 c Taubman, 2007 igital Circuits (ENGG1000) Page 11 COUNT ENABLE CLK Figure 7: 4-bit synchronous counter. but they also build circuits which can perform complex yet dedicated functions much faster than a general purpose CPU. The rest of the story is, of course, beyond the scope of these introductory notes.

12 c Taubman, 2007 igital Circuits (ENGG1000) Page 12 CLK 0 v A 0 A 1 A 2 A Addition network Σ=A+B B 0 B 1 B 2 B Σ 0 Σ 1 Σ 2 Σ Sequential circuit to add a sequence of 4-bit numbers 1 2 A 0 A 1 A 2 A Addition network Σ=A+B B 0 B 1 B 2 B v 2 Σ 0 Σ 1 Σ 2 Σ A 0 A 1 A 2 A Addition network Σ=A+B B 0 B 1 B 2 B v Complete network to add four 4-bit numbers Σ 0 Σ 1 Σ 2 Σ A 0 A 1 A 2 A Addition network Σ=A+B B 0 B 1 B 2 B v 4 Σ 0 Σ 1 Σ 2 Σ Figure 8: Left: synchronous digital circuit for repeatedly adding 4-bit numbers to an accumulator ( ). Right: direct combinatorial logic network for adding four 4-bit numbers.