Lancelot. VGA video controller for the Altera Nios II processor. V4.0. December 16th, 2005

Transcription

1 Lancelot VGA video controller for the Altera Nios II processor. V4.0 December 16th,

2 1. Description Lancelot is a VGA video controller for the Altera Nios (II) processor. The peripheral consists of two parts; the Lancelot core and the Lancelot VGA Board. This a add-on daughter board, which fits on the expansion interface of various Altera (and Altera partner) development boards, like the Altera Cyclone Nios Development Board, Altera Stratix Nios development board and the Altera EPXA1 Development board. The board holds the Video DAC and the VGA, PS2 and audio connectors. The Lancelot core is written in VHDL and can be used for Altera APEX 20KE/C, APEX II, Cyclone and Stratix devices. Master Registers State Machine Line Buffer Line Buffer Colour Table Video DAC R G B Slave Registers Local Registers State Machine HS VS Core Board The Lancelot core reads out the line buffers, drives the external video DAC and generates the sync signals. After the processor initialises and starts Lancelot, the VGA state machine requests new video data. The bus wrapper state machine reads one horizontal video line from the SDRAM and stores it in the line buffer. While one (empty) line buffer is filled by the bus wrapper DMA controller, the other (full) line buffer is readout by the VGA state machine. When the video line buffer is empty and the other line buffer is full, the line buffers are swapped and the process starts again. The colour table converts the 256 colour data to 24-bits colour pixels. The VGA state machine is also responsible for generating VGA timing and video DAC control signals. Lancelot VGA controller Page 2

3 2. Lancelot Signals Table 2.1. shows the Lancelot core signals for the Nios processor. The master port connects to the S(D)RAM controller and reads video data from the S(D)RAM using DMA. The processor can access the Lancelot register through the slave port. Signal Size Direction Description avalon_clk 1 In System clock video_clk 1 In Video clock reset_n 1 in Reset master_addr 32 out Avalon master address master_rddata 32 in Avalon master read data master_rd 1 out Avalon master read select master_waitreq 1 in Avalon master wait request slave_cs 1 in Avalon slave chip select slave_addr 3 in Avalon slave address slave_rddata 32 out Avalon slave read data slave_wrdata 32 in Avalon slave write data slave_rd 1 in Avalon slave read select slave_wr 1 in Avalon slave write select R 7 out Red output to video DAC G 7 out Green output to video DAC B 7 out Blue output to video DAC HS 1 out Hsync to VGA VS 1 out Vsync to VGA M1 1 out Mode select video DAC M2 1 out Mode select video DAC Blank_n 1 out Control signal to video DAC Sync_n 1 out Control signal to video DAC Sync_t 1 out Control signal to video DAC Table 2.1. Lancelot Core signals Lancelot VGA controller Page 3

4 3. Lancelot Registers The Lancelot core has 7 registers, which are all 32-bits wide. Register Map Offset Register Mode 0 Control W 0 Status R 1 Colour Table W 2-3 Reset W 4 Resolution R/W 5 Horizontal Timing R/W 6 Vertical Timing R/W 7 DMA R/W Control Register Bit Name Description 5 VS Polarity Writing a logic 1 inverts the VS output. 4 HS Polarity Writing a logic 1 inverts the HS output. 3 Set DAC Mode A logic 1 sets the Video DAC in RGB mode. 2 Start Video Writing 1 to this bit starts the internal video state machine. 0 Reset The Lancelot Core is automatic reseted during power-up. Status Register Bit Name Description Signature MG (5247) 9 New Frame This bit is 1 when the next frame is the first frame of the screen. 8 Frame Missed The bit is set when the line buffer isn t filled with a new line after an dma request or writing the line buffer data took longer than maximum line time (32 µs). 7 Line Buffer Video Full This bit is 1 when the video line buffer is full. 6 Line Buffer Video Empty This bit is 1 when the video line buffer is empty. 5 Line Buffer DMA Full This bit is 1 when the DMA line buffer is full. 4 Line Buffer DMA Empty This bit is 1 when the DMA line buffer is empty. 3 Blank VS This bit indicates the vertical blank status ( 1 = vertical blank). 2 Blank HS This bit indicates the horizontal blank status ( 1 = horizontal blank). 1 VS Internal vsync signal. 0 HS Internal hsync signal. Lancelot VGA controller Page 4

5 Colour Table Register Colour index Red value 15 8 Green value 7 0 Blue value Resolution Register Horizontal Resolution 15 0 Vertical Resolution Horizontal Timing Register Pulse Width 15 8 Back Porch Width 7 0 Front Porch Width Vertical Timing Register Pulse Width 15 8 Back Porch Width 7 0 Front Porch Width DMA Register 31-0 DMA start address Lancelot VGA controller Page 5

6 4. Video Timing The two figures below show the timing of a video line and video frame. According to the resolution a line consists of 640, 800 or 1024 pixels. A frame is divided into 480, 600 or 768 lines. If the BLANKn signal is asserted the output of the video DAC is forced to zero. When the horizontal sync signal (HS) is low indicates a new line. A new frame is indicated by a low pulse on the vertical sync signal (VS). Active Line BLANKn RGB HS A B C D E Figure 4.1. Horizontal Video Timing (Line) Active Line BLANKn RGB VS F G H I J Figure 4.2. Vertical Video Timing (Frame) Lancelot VGA controller Page 6

7 Resolution 640 x x x 768 A Line Period 32.8 µs 26.4 µs 20.7 µs B Hsync Sync Period 3.8 µs 3.2 µs 2.1 µs C Hsync Back Porch 1.9 µs 2.2 µs 2.5 µs D Active Video 25.4 µs 20 µs 15.7 µs E Hsync Front Porch 0.6 µs 1 µs 0.4 µs F Frame Period 16.7 ms ms ms G Vsync Sync Period 0.05 ms 0.1 ms 0.12 ms H Vsync Back Porch 1 ms 0.6 ms 0.6 ms I Active Frame 15.3 ms ms ms J Vsync Front Porch 0.3 ms 0.02 ms 0.06 ms Table 4.1. Video Timing Table 4.2. shows the video settings, which can be used to set the Lancelot horizontal and vertical timings registers. Resolution 640 x x x 768 * Video Clock 25.2 Mhz 40 Mhz 65 Mhz Horizontal Resoltution Vertical Resolution Hsync Pulse Width Hsync Back Porch Width Hsync Front Porch Width Vsync Pulse Width Vsync Back Porch Width Vsync Front Porch Width Table 4.2. Video Settings * Note; This video mode is only supported by the Excalibur ARM reference design. Lancelot VGA controller Page 7

8 5. Reference Designs Perform the following steps to run the Lancelot reference design on your Altera Nios Development Board. - Unplug the power cable from the development board. - Mount the Lancelot VGA Card on the Santa Cruz proto header as shown in figure 5.1 (Altera Stratix Nios Board or Altera Cyclone Nios Board). - Connect the VGA output to a monitor. - Connect an Altera programming cable to the JTAG header. - Power the development board. - Open de Nios II SDK Shell and browse to the flash_image directory in the Nios II reference design installation. - Type the command./lancelot_flash_image to load the Nios II configuration into the development board flash device. - Press the Reset Config button to run the Lancelot reference design. JTAG Connector Reset Config Figure 5.1. Altera Cyclone / Stratix Nios Development Board Lancelot VGA controller Page 8