SINGLE CHIP EIGHT-BIT PARALLEL

Transcription

1 v. % y, v-i K! x SI - ^vj 5 ;!AaP A<o -i\^ fj l_ «V 88 SINGLE CHIP EIGHT-BIT PARALLEL APRIL 97

2 ^ - ". - % / >» fnfewhicikm l/l. #. Z. nwwof«mmg 2- # ««' ii «% \ L Tflil^ linruciqiii Complee Funcional Definiion» ' 'V 7 Daa and inrucion Forma Summary of Proceor Inrucion ^ How o Ue '# IS ix II. Appendix ni » J, Appandix IV. Baic Syem Block Diagram b'< i 25 Appandix V. iiorn VI 26 Appandix VL Memory and Peripheral Device for he MCS-8 Microproceor Family «/<.~ > Appendix V MCS-8 Sofware Library.....» Appandix VI II.5 Y

3 he daa for ue in general purpoe digial. I i fabricaed on a ingle chip uing Inel' n-channel ilicon gae MOS prohu offering much higher performance han convenional microproceor (2f» inrucion A complee micro compuer yem i forme# o be in he he adoher device uch a he 88 CPU i inerfaced wih I/O por (up inpu and oupu por) and any ype or of emi-conducor memory. rificany higher in performance han are a follow: microproceor, he 88 ha been de- o be ofware compaible a he ource code level wih Inel' 88 micro-proceor. Like he 88, he 88 conain ix 8-bi daa regier, an < branche and -fai accumulaor, four 8-bi emporary regier, four eable flag bi, and an 8-bi parallel binary arihmeic uni. The 88 alo provide decimal arihmeic capabiliy, and i include ixeen bi arihmeic and immediae operaor which grealy implify memory addre calculaion, and high arihmeic operaion. I T < > '.,,. >: f <, in Daa Regier The 88 ha a ack archiecure wherein any porion of he exernal memory can be ued a a ir ou ack o ore/rerieve he conen of he accumulaor, he flag, or any of he daa regier. The 88 alo conain a 6-bi ack poiner o conrol he addreing of hi exernal ack. One of he major advanage of he ack i ha muliple level inerrup can eaily be handled ince complee yem au can eaily be aved when an Inerrup occur and hen be reored afer he inerrup. Anoher major advanage i ha almo unlimied ubrouine neing i poible. Thi proceor ha been deigned o grealy implify yem deign. Separae 6-line addre and Sack Binary Arihmeic Decimal Arihmeic The purpoe of hi publicaion i o preen he ', inrucion e, and elecrical characeriic, in addiion, oher memory and peripheral circui which have been deigned, and pecified for ue wih he 88 are preened. DIRECT frine bidirecional daa bue are ued o allow direc inerface o memorie and I/O por. Conrol ignal, which require no decoding, are provided cfirecly by he proceor. All bue, including conrol, are TTL compaible. REGISTER.. V

4 +» f!sf H i iljm ' ' \ V. K? / «r of ail of ID pin configuraion i hown in / V S. (oupu ri-ae) APDHfcSS BUS; he addre word) or i he lea ignifican add ' -» fr o memory (up o 6K and IVO, (inpu/oupu) ri-ae DATA BOS; he daa bu provide bidirecional ory and I/O device for inrucion and daa, can bi coflmnivficion oerween memi he lea igniff- SYNC (oupu) SYNCHflONIZING SIGNAL; he SYNC pin provide a ignal o indicae he beginning of each machine cycle. (Inrucion can be execued in, 2,, or 5 machine cycle, and he au informaion c exernal lache a SYNC ime.) See 2-2. f each machine cycle i en o / DBIN (oupu) DATA BUS IN; he DBIN ignal indicae o exernal in he inpu mode. Thi ignal hould be ued o he 88 daa bu from memory or I/O. circui ha he daa bu i of daa ono PA READY (Inpu) I READY; he READY ignal indicae o he 88 ha vahd memory or inpu daa i available on he 88 daa bu. Thi ignal i ued o ynchronize he CPU wih lower memory or I/O device. If afer ending an addre ou he 88 doe no receive a READY inpu, he 88 will ener a WAIT ae for a long a he READY line i low. I $ i 5 WAIT (oupu) WAIT; he WAIT ignal acknowledge ha he i in a WAIT ae. / K m (oupu) WRITE; he WR ignal i ued for memory daa on he daa bu i able while he WR or I/O oupu conrol. The i acive (WR = ). # «HOLD (inpu) HOLD; he HOLD ignal reque he CPU o ener he HOLD ae. The HOLD ae allow an exernal device o gain conrol of he 88 addre and daa bu a oon a he 88 ha compleed i ue of hee bue for he curren machine cycle. I i recognized under he following condiion: he CPU i in he HALT ae he CPU i in he T2 or TW ae and he READY ignal $ acive \ ^ r. A a reul of enering he HOLD ae he CPU ADDRESS BUS (A l5 -Ao) and DATA BUS (D 7 -D ) will be in heir high impedance ae. The CPU acknowledge i Sae wih he HOLD ACKNOWLEDGE (HLDA) pin. See Figure. The CPU will alway fmih he execuion of he curren machine cycle. When he HOLD ignal i removed, he operaion will reume from he T ime of he nex machine cycle. (See aached iming char, Fgure and h in Appendix ML), / 2

5 HOW indicae ha inrepone he o he HOLD ^ r > v < > > - o aier cae, he HLDA ignal appear afer he riing edge of <f>, and high ' V iffte occur afer heriing edge of $,. SeeAppendix lll-f for iming au l\ LE; indicae he conen of he inernal inerrup enable flip/flop may be e or ree by he S and Dl inrucion and inhibi inerrup from being acceped by he CPU if i i ree, i i auoree (diabling furher inerrup) a ime T of he inrucion fech cycle (M) when an inerrup i acceped and i alo ree by he RESET ignal. ^ ^ S S/ '. I N.«.. ' / f AFT (pu INIfcHHUPT REQUEST; he CPU recognize an inerrup reque on hi line a he end of he curren inrucion or whie haled. If he CPU i in he HOLD or if he Inerrup Enable Hip/flop i ree i will no honor he reque Tle CPU acknowledge accepance of an inerrup by ending ou he < INTA (inerrup Acknowledge) au-ignal a SYNC ime. During he nex inrucion lech cycle he program couner i no advanced and a bye inrucion (uually REST ART) can be inered. SeeAppendix!.. «k % J (inpu) ; while he i and he inrucion a locaion in memory Noe ha he flag, accumulaor The HL and DE regier <6 e e G, Afer he program couner, he program will are alo ree, a wih he 88. V. Ground Reference. V d V. V. + 2 ± 5% Vol + 5 ± 5% Vol 5 ± 5% Vol (ubrae bia) 2 exernally upplied clock phae, (non ) ' 2-2. Sau Informaion Inrucion for he 88 require from one o five machine cycle for complee execuion. The 88 ou 8 bi of au informaion on he daa bu a he beginning of each machine cycle (during SYNC ime). The following able define he au informaion. V STATUS INFORMATION DEFINITION Symbol Daa Bu Bi Definiion HLTA D, Acknowledge ignal for HALT inrucion. INTA D Acknowledge ignal for INTERRUPT reque. Signal hould be ued o gae a rear inrucion ono he daa bu when DBIN i acive. INP D Indicae ha he addre bu conain he addre of an inpu device and he inpu daa hould be placed on he daa bu when DBIN i acive. OUT D Indicae ha he addre bu conain he addre of an oupu device and he daa bu will conain he oupu daa when WR i acive. MEMR D, Deignae ha he daa bu will be ued for memory read daa M I D, %. Provide a ignal o indicae ha he CPU i in he fech cycle for he fir bye of an inrucion. p STACK D 2 Indicae ha he addre bu hold he puhdown ack addre from he Sack Poiner. WO, Indicae ha he operaion in he curren machine cvcle will be memory or OUTPUT funcion (WO = ). INPUT operaion will be execued. Oherwie, a READ memory hree au bi can be ued o conrol he flow of daa ono he 88 daa

6 Iwnu limn in he 88 conain one o hree bye. in require from one o five machine nomory cycle for feching and execuion. are called M, M2,..., M5. Each macycle require from hree o five ae., T5 for i compleion. Each ae ha he of one clock period (.5 micro-econd), are hree oher ae (WAIT, HOLD, and HALT) which la one o an indefinie number of period, a conrolled by exernal ignal. Machine cycle M i alway he operaion-code hecycle ha i currenly being iniiaed. T i alway followed by anoher ae,t2, during which he condiion of he READY, HOLD and HALT Acknowl- i edge Signal are eed. If READY i rue, T can be enered; oherwie, he CPU will go ino he wai fade. <TW) and ay here for a long a READY i READY hu allow he CPU peed o be ynchron-, ized o a memory wih any acce ime or o any inpu device. Furhermore, by properly conrolling he READY line, he uer can ingle-ep hrough od cycle and la four or five ine cycle M2, M, M, and M5 normally la dock period each. To underand he baic operaion of he 88, refer o he implified ae diagram hown in Figure he iming diagram of Figure 2. During T he conen of he program couner i o he addre bu, SYNC i rue, and he daa conain he au informaion peraining o, During T, he daa coming from memory i available on he daa bu and i ranferred ino he inrucion regier (during M only) a hown in he 88 block diagram of Figure. The inrucion decoder and conrol ecion hen generae he baic ignal o conrol he inernal daa ranfer, he % iming, and he machine cycle requiremen of he new inrucion. mum Figure 2. Baic 88 Inrucion Cycle

7 r I P 9 9 ^. > < ^ > V # I JJflNTE F/F IS RESET IF INT F/F IS SET. IWT F/F IS RESET IF INTE F/F IS RESET BIKE SECTION.

8 A«rend a T, if he cycle i complee, or ele a of T5, he 88 goe back o T and ener J unle 9 cycle for i execuion, li a new Ml cycle i many cycle and loop I P»- upoama»mum of 8» he conen for he ne concern II e obly during he la aa of he la Machine he inerrup reque ine i eed and a i enered, during which no profraafr-couner incremening ake place and INTER- ACKNOWLEDGE au i en ou During Mi cvh and of diah iwffawh'wmi A he maximum dock fre- mean ha all inruc-»r ranging from 2 ps he proioernip i \ - <." ;

9 w. «^ «> r e underflow Reauizero O A fkxi Logical produc caion or regier ^ \ i A "or" v v A. Incluive "or" Bi m of he A-regier «SP PC Sack Poiner ( ranferred o A "don' care" ' V > f I Source regier for daa > V ODD Deinaion regier for daa Regier # (SSSor DDD)» B c o E H L Memory ACC ilhuctlon SET r Bye Cycle Decripion of Opwfe > ' MOV r r, (r,) «- (r 2 ) Load regier r, wih he coneno r. The conen of r 2 remain unchanged. MOVr.M MOVM, r 2 2 (r) «-(M) Load regier r wih he conen of he memory locaion addreed by he conen of regier H and L. (M) - (r) Load he memory locaion addreed by he conen of regier H and L wih he conen of regier r. MVIr <Bj> 2 2 (r)«- <B,> Load bye wo of he inrucion ino regier r. MVIM 2 <B 2 > Load memory and L

10 > INfl r oefp M + M ~(r) - "I The Of he condiion rae. All by he reult by one. ' All by he reul. AOQr ADCr i "» (A) + (r) Add he conen of regier r o he conen of and place hereul ino regier A. (All flag affeced (A)«(A) + (r) -- (carry) Add he conen of regier conen of he carry flip-flop o he conen of he A re reul ino. % r (A) -(A) - (r) of regier A and ubracion i ued. (AW flag from he conen complemen ^ < f (A) - (A) - (r) - he conen of he he reul ino regier A. regier r and of regier A and.) ANAr (A) «- (A) A (r) Place he ogicaf pro< fac of he regier A and \ regier r ino regier A. (Ree carr^ f.) XRAr (A) «- (A) V (r) Place he "excluive and regier r ino regier A. (Ree carry.) - or" ofhe conen of regier A '» ' OfAr (A)«(A) V (r) Place he "incluive -or" of he conen of regier A and regier rino regier A (Ree carry.) CMP r (A) (r) Compare he conen of re gier A wih he conen of regier r. The conen of regier A remain uncha flip-flop are e by he reul of he ubracion. Ei indicaed by he zero flip-flop e o "Le han Indicaed by he.carry. flip-flop, e o "." r) i «ADO M ADCM SUB M S8BM ANAM 2 (A) - (A) + (M) ADD 2 (A) «-(A) + (M) + (carry) ADD wih carry 2 (A) (A) (M) SUBTRACT 2 (A) «- (A) (M) - (borrow) SUBTRACT wih borrow 2 (A) (A) A (M) Logical AND XRAM ORAM CMP M ADI 2 <Bj> 2 (A) - (A) V (M) Excluive OR 2 (A)-(A)V(M) Incluive OR 2 (A) - (M) COMPARE 2 (A) ADD (A) + <B 2> (M) addreed by he conen of regier H and L ««Flag affeced are ameaarr. ACI 2 <B 2 > SUI 2 <b 2 > 2 (A) - (A) + <B 2 > + (carry) ADO wih carry 2 (A) - (A) - SUBTRACT S SBI 2 <B 2 > ANI 2 <B,> XRI 2 <B,>? (A)-(A) - <B 2 > - (borrow) SUBTRACT wih borrow (A)-(A)A<B 2 > Logical AND (A)«- (A) <B 2 > Excluive OR ORI 2 <Bj> 2 (A) - (A) Incluive OR 2 > CPI 2 <Bj> 2 (A) - <B 2 > COMPARE / J RLC 9 < A» +, A m> Ao A 7, (carry) «- A 7 Roae he conen of regier A lef one bil Roae Aj ino Aq and ino he carry flip-flop. RRC A- A. + i, A,«-A, (carry) «-Ao Roae he conen of regier A righ one bi Roae Ag ino A r and ino he carry flip-flop.

11 Bye Cycle Decripion of Operaion RAL A. +,«- A m, A, «- (carry), (carry) - A, Roae he conen of Regier A lef one bi Roae he conen of he carry flip-flop ino A Roae A, ino he carry flip-flop. i v. RAR A. «-A +L,A (carry), (carry) 7 AO. Roae he conen of regier A righ one bi Roae he conen of he carry flip-flop ino i Roae An ino he carry flip-flop. JMP (PC) <- <B > <B 2 > Jump uncondiionally o he inrucion locaed locaion addreed by bye wo and bye hree. <B»> JC If (Carry) «(PC) - <Bj> <B,> Oherwie (PC) = (PC) + JNC If (Carry) = (PC) <B,> <B,> <B,> <BJ> Oherwie (PC) = (PC) + JZ If (Zero) = (PC)«- <B,> <B,> <Bj> <B,> Oherwie (PC) = (PC) + JNZ If (Zero) = (PC) «- <B,> <B 2 > <B 2 > Oherwie (PC) = (PC) + JP If (Sign) = (PC) - <B > <B 2 > <B 2 > <B,> Oherwie (PC) = (PC) + A JM If (Sign) - (PC) - <B,> <B 2 >... <b > ' Oherwie (PC) = (PC) + JPE If (Pariy) = (PC) - <B,XB,> <BJ> Oherwie (PC) = (PC) + JPO If (Pariy) = (PC) - <B,> <B 2 > <B 2 > <BJ> Oherwie (PC) = (PC) + HLT On receip of he Hal Inrucion, he aciviy of he proceor i immediaely upended in he STOPPED ae. The conen of all regier and memory i unchanged and he PC ha been updaed. CALL 5 ISP - [SP - 2] - (PC), (SP) = (SP) -2 <B,> <BJ> (PC) - <B > <Bj> Tranfer he conen of PC o he puhdown ack in memory addreed by he regier SP. > The conen of SP i decremened by wo. Jump uncondiionally o he inrucion locaed m memory locaion addreed by bye wo and bye hree of he inrucion. CC /5 If (carry) = [SP - iffsp - 2] - PC, <B,> (SP) = (SP) 2, (PC) <BJ> <B 2 >; oherwie (PC) = (PC) + CNC /5 If (carry) = [SP - ] [SP - 2] PC, <B 2 > (SP) = (SP) - 2, (PC) - <B > <B 2 >; <B > oherwie (PC) = (PC) + CZ ' /5 If (zero) = [SP - ] [SP - 2] - PC, <BJ> (SP) - (SP) - 2, (PC) - <Bj> <B 2 >; <BJ>. oherwie (PC) = (PC) + CNZ /5 If (zero) = [SP - ] [SP - 2] - PC, <B 2 > (SP) = (SP) - 2, (PC) - <B > <B 2 >; <B,> oherwie (PC) = (PC) + CP /5 If (ign) «[SP - J [SP - 2] - PC, <B 2 > (SP) = (SP) - 2, (PC) - <B > <B 2 >; <B,> oherwie (PC) = (PC) + 9

12 % a# V f- v \ v Til conen of SP i incremened oy wo. T/ If (carry) (SP) - - ISP), ISP +, + 2; (PCJ + UNC / IJ. «. oherwie (PC) = + RZ If (zero) - (PC) - (SP) -(SP) + 2; +.. r oherwie (PC) = + / If (zero) (SP) - flihmwm (PC) + 2;, ISP -, v RP (PC) + (SP) (SP) + 2; (PC) «A v + (SP) (PC) - (SP) + 2;, JSP +). i < + If (pariy) «(PC) - [SP], {SP +. (SP) «(SP) + 2; oherwie (PC) = + \ npo / If (pariy)» + (SP) - (SP) + 2; oherwie (PC) + RST ISP- (SP)«(PC) [SP - 2] - (PC), (SP) - 2 ( AAAQ) IN 2 (A) (Inpu daa) A T ime of hird cycle, he I/O device number, i en o he I/O device hrough he addre, line', and he INP au informaion, inead of MEMR, i en ou a ync ime. New daa for he accumulaor i loaded from he daa bu when DBIN conrol ignal i acive. Die condiion flip-flop are no affeced. > OUT <B 2 >.2 (Oupu daa) (A) A T, ime of he hird cycle, bye wo of he inrucion, which denoe he I/O device number, i en o he addre line', and he OUT au informaion i en ou a ync ime. The conen of he accumulaor i made available on he daa bu when he WR conrol ignal i. LXB <B,> (C) «- <B 2 >; (B) <B > Load bye wo of he inrucion ino C. Load bye hree of he inrucion ino B. I \ LXID <B 2 > <B,> (E) <B 2 >, (D) <Bj> Load bye wo of he inrucion ino E. Load bye of he inrucion ino D. LXIH (L) - <B 2 >, (H) - <B } > Load bye wo of he inrucion ino inrucion ino H. 'The device addre appear on and A» «I

13 Bye CydK Decripion of Operaion (SP),. - <BJ>, (SP) H - < > Load bye wo of he inrucion ino he lower order 8-bi of he poiner and bye hree ino he higher order 8-bi of he ack poiner. i PUSfPSW ISP ] - (A), (SP - 2J (F), (SP) - (SP) 2 Save he conen of A and F (5-flag) ino he puhdown ack addreed by he SP regier. The conen of SP i decremened by The flag word will appear a follow: D : CY, D,: D 2 : Pariy D,: D«: CY, D,: D : Zero D,: MSB (Carry) (even) (ign) PUSH B [SP - (B) {SP - 2 (C), (SP) - (SP) - 2 ^, PUSH D [SP - J - (D) (SP (E). (SP) - (SP) - 2 PUSHH POPPSW S [SP - J «-(H) [SP (L), (SP)(SP» - 2 " (F) - [SP, (A) - [SP + I], (SP) = (SP) + 2 Reore he la value in he puhdown ack addreed by SP ino A and F. The conen of SP i incremened,by wo. ' '» POPB (C) - [SP], (B) - [SP +, (SP) - (SP) + 2 POPO (E) - [SP], (D) - ISP +, (SP) «(SP) + 2 POPH (L) «" [SP], (H) - [SP + ], (SP) - (SP) + 2 STA [<BJ> <B 2 >J <- (A) Sore he accumulaor conen ino he memory locaion addreed by bye wo and bye hree of he inrucion. «LDA <B,> <Bj> (A) «- [<BJ> <B 2 >] Load he accumulaor wih he conen of he memocy locaion addreed by bye wo and bye hree of he inrucion. XCHG (H)» (D) (E) (L) Exchange he conen of regier H and L and regier D and E. XTHL S (L) [SP], (H) [SP + ] Exchange he conen of regier H, L and he la value in he puhdown ack addreed by regier SP. The SP regier ielf i no changed. (SP) = (SP) SPHL (SP) - (H) (L) Tranfer he conen of regier H and L ino regier SP. PCHL (PC)«- (H) (L) JUMP INDIRECT DAD SP (H) (L) - (H) (L) + (SP) - Add he conenofregier SP o he conen ofregier H and L. and place he reul ino regier H and L If he overflow i generaed, he carry flip-flop i e; oherwie, he carry flip-flop i ree. The oher condiion flip-flop 9re no affeced. Thi i ueful for addreing daa in he ack. DADB (H) (L)«- (H) (L) + (B) (C) DADH (H) (L) - (H) (L) + (H) (L) (double preciion hif lef H and L) DAD D (H) (L) - (H) (L) + (D) (E) STAX B 2 [(B) (C)l - (A) Sore he accumulaor conen in he memory locaion addreed by he conen of regier B and C. STAXD 2 [(D) (E)] - (A) Sore he accumulaor conen ino he memory locaion addreed by he conen of regier D and E. LDAXB 2 (A) - [(B) (C)J Load he accumulaor wih he conen of he memory locaion addreed by he conen of regier B and C.

14 «V HWJ ICJJ Load he accumulaor wih he conen of memory locaion addreed ^liweonen of regier O ami E. j i MR& + The conen of regier pair B and C i incremened by one. All of he fip-flop are no affeced. mmm <hml> («) (U + The conen of regier H and L i incremened by one. All of he condiion fip-flop are no affeced. WXO (D) (E) + 9fXSP (SP»-(SP) + OCXB (8MQ - (B) (C) - OCXH (H(LM-(H)(L) - OCXD (D) - (D) (E) OCXSP (SP)«-(SP) - CMA (A) - (A) ^ W 9 ^ W. < ' «««v The conen of accumulaor i complemened. Thecondiion ffp-flop are no affeced. STG (Carry) - Se he carry flip-flop o. The oher condiion flip-flop are no SRVCQ mmm ri > rl ' CMC (carry) «- (carry) The conen of carry i complemened. The oher condiion fup»flap are no affeced. v DAA Decimal Adju Accumulaor - The 8-bi value in he accumulaor conaining he reul from an arihmeic operaion on decimal operandi adjued o conain wo valid BCD digi by adding a value according o he following rule: Accumulaor If (V ) or (carry from bi ) hen Y = Y + 6 wih carry o X digi. If (X ) or (carry from bi 7) or. l(y > ) and (X = 9)] hen X «X + 6 (which e he carry flip-flopj. Two carry flip-flop are ued for hi inrucion. CY, repreen he carry from bi (he fourh bi) and i acceible a a fifh flag. CY 2 i he cany from bi 7 and i he uual carry bi - AH condiion flip-flop are affeced byhiinrucion. ( SHLD 5 [<Bj> <B 2 >] (), {<B,> <Bj> + J (H) <B 2 > Sore he conen of regier H and L ino he memory locaion <B,>. addreed by bye wo and bye hree of he inrucion. LHLD 5 (L) - {<B } > <B 2 >I, (H) - [<B,> <B 2 > + ] <B 2 > Load he regier H and L wih he conen of he memory locaion <B,> addreed by bye wo and bye hree of he inrucion. El - inerrup Syem Enable Dl Inerrup Syem Diable The inerrup Enable flip-flop (INTE) can be e or ree by uing he above menioned inrucion. The INT ignal will be acceped if he INTE i e. When he INT ignal i acceped by he CPU, he INTE will be ree immediaely: During inerrup enable or diable inrucion execuion, an inerrup will no be acceped. INR M [MJ - [M] +. The conen of memory deignaed by regier H mid L i incremened by one. All of he condiion flip-flop excep carry are affeced by he reul. DCR M [M] [M]. The conen of memory deignaed by regier H and L i decremened by one. All of he condiion flip-flop excep carry are affeced by he reul. 2

15 % ' V >. i : ; u a, ^ ^ O. Q, D, O, D ' V J inrucion may be dm, wo, or hroabyea in ucceive word in program memory. pxiealar operaion execued. D, P, P D, D, Dp i OP CODE «, memory referor logical, roae Inrucion «Bye Inrucion V A Par he 88 a logic "" i defined aa higj level and a logic "" i defined a a ow level. :'?. > Or IV D. p«iv Of MOV r r, D D MOV M, r MOV r, M D D HLT MVIr D D D MViM INRr D D D OCR r D D D ADD r ADC r SUB r O SBBr ANA r XRA r ORAr CMP r S ADD M ADC M SUB M SBBM ANAM XRA M - ORAM CMP M ADI ACI SUI SBI NDI XRI ORI CPI RLC RRC RAL RAR. JMP JC JNC JZ JNZ. JP JM» ' & S ) DDD or SSS B C D E H L Memory ACC Z Time Sae = Clock Period / %

16 > «VI I (/ «V e, % e. 9 f ' : f ; '. ^ ^ 9 a ' I i'. ' < A LXIH LXISP PUSHB PUSH O PUSH H PUSHPSW POP B POP D POPH POPPSW STA LDA XCHG XTHL 8PHL PCHL DAD B DADD DADH OADSP STAXB STAXD LDAXB LDAXD INX B INXD INXH INXSP DXCB DXCD OCX H DCXSP CMA STC CMC DAA SHLD LHLD El Dl NOP ) T f ' -f Q & e i r» A A A %. «««I a 8 f 9 T >.»< r a f.» i > V «V v :v.a S V ' I 7". 7 ' i, ' V i C f ' S ) %. i

17 APPENDIX I HOW TO USE THE PUSHDOWN STACK «. PC Canon! SP Conen N - INSTR. N - N SP <- (INTERRUPT ARRIVES HERE) instr. N i i Rear inrucion inered here «. N + () SP - 2 Save PC value N in ack uing rear inrucion o jump o S. SUBROUTINE FOR HANDLING INTERRUPT PUSH H El S + (2)SP- Save HL in ack if deired Enable furher inerrup if deired. S + n POPH S + n () SP - 2 Reore HL from ack S + n + RET N ()SP Reurn PC from ack CONTENTS LOW MEMORY () (2) () Saved H&L L H TOS 5MQ rw N TOS Saved PC Saved PC TOS X x w X X Old op of ack (TOS) NOTE: The uer can iniialize he ack poin SP regier wih a LXI SP inrucion o ue any ecion of read-wrie memory a a ack. The SP i decremened when daa i puhed ono he ack, and incremened when daa i popped (ha i he ack grow "downward").

18 APPENDIX II fpwrnir operaion) Addiion: Memory addre of Augend; D and E i (ALPHA) Memory addre of Addend; H and L i (BETA) Operand Explanaion Commen LXI LX! MVI D, ALPHA H,BETA C, 8 Load O and E immediae Load H and L immediae Load C wih "8" Sa addre o DE Sal addre o HL LOOP XRA LDAX ADC DAA STAX I NX INX DCR JNZ D M D H D C LOOP Excluive or A wih A Load A wih (DE) Add M o A (HL) Decimal Adju Sore A o (DE) Incremen HL Incremen OE Decremen C If no zero go o loop dear Carry Load Augend o Acc Add Addend o Augend Replace Reul Renew addre HL Renew addre DE Check end of calculaion Calculaion ime (6 digi) 2 /iec I Decimal Subracion Memory addre of Minuend; D and E (ALPHA) Memory addre of Subrahend; H and L (BETA) Mnemonic Operand Explanaion Bye Commen. LXI D, ALPHA Load D and E Immediae Se addre o DE LXI H, BETA Load H and L immediae Se addre o HL MVI C, 8 Load C wih "8" 2 STC Se Carry 2 LOOP: MVI A.99H Load A wih 99 HEX 99, 6 + = 9 A, ACI Add wih carry 2 SUB M Subraced from A XCHG Exchange DE and HL Acual ly Decimal ADD M Add M o A DAA Adju -2 = = MOV M, A Load A o M % XCHG Exchange DE and HL No borrow occur here INX D Incremen DE INX H Incremen HL DCR C Decremen C JNZ LOOP Calculaion ime (6 digi) /ec 6

19 Muliplier, Q and E I A - ( S Bye LXI MV : DAD RAL JNC DAD ACI DCR JNZ H, B, 8 H DEC D B Iniialize Parial 8 - B o conrol IIUUUO l/b6iwfl8fu o Te o ee if B bi o carry couner ierae a ime < V. «\ - T k 2 Calculaion ime for 8 x 6 muliply ~ 2 pec % Operand Bye MOV MVI LDA MOV LDAX LDAX LHLD MOV POP IN A, B A, 2 98 A, B D 88 A, M A Load A wih Regier Load A wih Daa Immediae "2" Load A wih conen of memory LQC 98 Load A uing H and L a addre Load A uing B and C a addre Load A uing D and E a addre Load A indirec uing IjOC 88 Load A wih daa from ack Load A wih daa from Device i 2 2» 7

20 APPENDIX ffl K HCAOV WAIT / i. FTEAOY WAIT AIM» READY WAIT / DATA SHOULD BE STABLE

21 6 ' '. i > I I > b.. < «> UNKNOWN READY STATUS WFOFTMATTON 9

22 nolww Hkm M M j 'h -h Xi % Ti nf m PC UNKNOWN PC2 PC- BYTE ONE FLOATING BYTE BYTE THREE Wh M Q M STATUS TN (L Inpu Inrucion

23 ahpbt MSTfHJCTlOfi WAIT ^, «STATUS TTON MEMR f I MEMR WO OUT f f HOLD OPE RATI ON (READ MODE) #i o» HOLD HOLO READY HOLD F/F INTERNAL HLOA W HOLD SIGNAL CAN BE SYNCHRONIZED «Y THE RISING EDGE OF OR oj. ATTACHED ELECTRICAL CHARACTERISTICS T AND % OPERATION CAN BE DONE INTERNALLY.

24 I V. I» HOLO F/F MTCRNAL HOLO Operaion (DAD) HOLD REOUEST HOLD HEADY HOLDOFF DAD" INSTRUCTION <l R ADY SIGNAL WILL NOT BE REQUIRED (2) ONLY ONE SYNC SIGNAL <> HLOASK2NAL APPEARS AT ONE CLOCK PERIOD FOLLOWING T TIME

25 \ MTF/F (NTERNAU mumt STORE C ) INTERNAL $ ^» STATUS MFOMIATION % V. «FLOATING Pw SVMC 9N HOLD MOTOF/F (INTERNAL) HLOA MT i INT»NTF/F (INTERNAL) STATUS INFORMATION

26 L MALT Inrucion «$ r STATUS INFORMATION J.-RESET INTERNAL RESET STATUS INFORMATION MEMR Mi WO LFL WHCN RESET SIGNAL IS ACTIVE, ALL OF CONTROL OUTPUT SIGNALS WILL BE RESET IMMEDIATELY OR SOME CLOCK PERIODS LATER. THE RESET SIGNAL MUST BE ACTIVE FOR A MINIMUM OF THREE CLOCK CYCLES. IN THE ABOVE DIAGRAM N AND I MAY BE ANY INTEGER. I I _ L ; I ; I

27 APPENDIX IV BASIC DIAGRAM i \ m ; ; v - -r i V A ^f «% WIUT momnifuuch STATUS LATCH r DATA BUS OUT i, / I V. '. i ' H ' ' '» T _ ^. «\» v / w:. < r «i.» V» i N MEMORY DATA IN PROCESSOR STATUS MTEimUfT WULIION POUT Typical 88 Syem Block Diagram

28 . 6 %.6 APPENDIX V 9 ' NOTE Thi elecrical and iming pecificaion i only preliminary.. wilf no occur during he engineering mil be releaed in lae May, J97. No /,+ be given a hi ime «ha The final pecifica Abolue Maximum Raing Under Bia Co7lfC Temperaure 65rCo+5 C AH Inpu or Oupu Volage wih repec o he mo negaive volage, V BB +25V o -.V Volage Vqd and V$ wih repec o \^ +2V o -&V Diipaion OW COMMENT: SmwafaoMehoe lied under "Abolue Maximum Raing" may r»»iii permanen damage o he device. Thi i a re raing only and funcional operaion of he device a hee or any oher condiion above hoe indicaed in he operaional ecion of hi pecificaion i no implied. Expoure o abolue maximum raing condiion for exended period may affec device nn^iy. D.C. Characeriic T A» C o +7CfC, V DO = +2V ± 5%, V cc = +5V ± 5%, V BB = -5V ± 5%, VSS= OV. unle oherwie noed. Symbol Parameer Min. I Typ, Ma. I Uni Te Condiion V,LC Clock Inpu Low Volage V-. V V MC Clock Inpu High Volage '. ' V V L Inpu Low Volage V a V V H Inpu High Volage. \ VCC V ' Vol Oupu Low Volage».5 V V OH Oupu High Volage 2. V «lo.7ma On Daa Bu lo.".75ma On All Oher I OH /xa 'doi Power Supply Curren (Vqd ) during HOLD ma >2 Power Supply Curren (Vqd > during HOLD cci Power Supply Curren (Vcc) during HOLD # ma ma Coninuou Operaion T A= 25 C 'CC2 Power Supply Curren (Vcc ) during HOLD 7 ma T cy = 8n Ibb Power Supply Curren ma ^ d Timing Diagram. 9 28

29 T«fCo 7(fC # V DO =+2V ± 5%, Vec +5V i Mi. LA Te Condiion Dock Period 2!, MS J i >. r Clock Rie and Fail Time 5 n Pule Widh of, / n «Pule Widh of 2! ^ n Clock Delay beween <j and 2 Clock Delay beween 2 and ^ «OA Addre Oupu Delay from 2 2 oo Daa Oupu Delay from 2 %. oe Conrol Signal Oupu Delay from j or 2 (SYNC, WE, WAIT and HLOA) 2 IT Land CL=5pF DBIN Oupu Delay from 2 Clock Delay o 2 Daa Seup Time o during Daa Hold Time from 2 during Ready Ree Time during 2 2 Ready Seup Time during 2 Hf Hold Ree Time during 2 Hold Seup Time during 2 Addre Delay o Ener Hold Sae Daa Delay o Ener Hold Sae Capaciance T A = 25 C; Unmeaured Pin Grounded n Limi (pf) SymfK>l Te Typ. Max. c i Clock Capaciance 2 C2 Clock 2 Capaciance 2 «9 C N Inpu Capaciance. 8 /. C OUT Oupu Capaciance (Addre In High Impedance Sae) 5 27

30 APPENDIX VI MEMORY AND 2 BIT FULLY DECODED STATIC MOS RANDOM 256 x Organizaion o Mee Need for Small Syem Memorie» Acce Time 85n Max. Single +5V Supply Volage f AH Inpu Have Proecion Again Saic Charge Direcly TTL Compai ble All Inpu and Oupu Saic MOS No Clock or Refrehing Required» Simple Memory Expanion Inpu Low Co 22 Pin Plaic» Low Power mw OR-Tie The Inel 8 i a 256 word by bi aic random acce memory elemen uing normally off N-channel MOS device inegraed on a monolihic array. I ue fully DC able circuiry and herefore require no clock or refrehing o operae. The daa i read ou nonderuciveiy and ha he ame polariy a he inpu daa. «i The 8T i deigned for memory applicaion where high performance, low co, large bi orage, and imple inerfacing atre imporan deign objecive. - I i direcly TTL compaible in ail repec: inpu, oupu, and a ingle+5v upply. A eparae chip enable ( ) lead allow eay elecion of an individual package when oupuareor-ied. ' The Inel 8 i fabricaed wih N-channel ilicon gae echnology. Thi echnology allow he deign and producion of high performance, eay-o-ue MOS circui and provide a higher funcional deniy on a monolihic chip han eiher convenional MOS echnology or P-channel ilicon gae echnology. \ Inel'ilicon gae echnology alo provide excellen proecion again conaminaion. Thi permi he ue of low co ilicone packaging. PIN CONFIGURATION LOGIC SYMBOL BLOCK DIAGRAM PIN NAMES Dh-OI«OAT A INPUTS!«CHIP ENABLE A Ay ADDRESS INPUTS DO -OO DATA OUTPUTS MM READ/WRITE INPUT!l Vcc POWER (+SV)

31 2 BIT FULLY MOSRANDOM DATA I/O Organizaion 256 Word by Bi On Chip Addre Common Daa inpu and Oupu Single ~5V Supply Volage Direcly TTL Compaible Ail inpu and Oupu All Inpu Have Charge Low Co Packaging 8 Pin Plaic Saic MOS No Clock or Refrehing Required Typically 5 mw Acce Time 85n Max. OR-Tie Simple Memory Expanion ESnable Inpu The Inel 8 i a 256 word by bi aic random acce memory elemen uing normally off N-channel MOS device inegraed on a monolihic array. I ue fully DC able (aic! circuiry and herefore require no dock or refrehing o operae. The daa i read ou nonderucive^ and ha he ame polariy a he inpu daa. Common inpu/oupu pin are provided. The8 i deigned for microcompuer memory applicaion in mall yem where high performance, low oa, large bi orage, and imple inerfacing are imporan deign objecive. I i direcly TTL compaible in all repec: inpu, oupu, and a able (CE) lead allow eay elecion of an individual package when. A eparae chip en- -ied. The Inel 8 i fabricaed wih N-channel ilicon gae echnology. Thi echnology allow he deign and producion of high performance, eay-o-ue MOS circui and provide a higher funcional deniy on a monolihic chip han eiher convenional MOS echnology or P-channel ilicon^ae echnology. Inel' ilicon gae echnology alo provide excellen proecion again conaminaion. Thi permi he ue of low co ilicone packaging. N CONFIGURATION PIN NAMES BLOCK DIAGRAM R/W Ao-A i OO R/W ADDRESS INPUTS OUTPUT DISABLE READ/WRITE INPUT CE, CHIP ENABLE CE 2 CHIP ENABLE 2 L/O V I/O INPUT/OUTPUT Z L/«, / ' Z'/ I l/o ENABLE OUTPUT: CE CE? WRITE: W«CEi E 2 Q PIN NUMBERS 79

32 2 BIT FULLY 9 J ' ^ # A RANDOM <» Single +5 Vol Supply Volage Oupu Ail Inpu Saic MOS No Clock or ^ Low Power Typically 5 mw rave Saic Charge 85n Max. 6 Pin Plaic. i ' Three-Sae Oupu OR-Tie Capabiliy The Inel 82 i a 2 word by one bi aic MOS device inegraed on a monol rhic array, no clock or refrehing o operae. The daa inpu daa. ue' reac able normally off N-chanhel and herefore require he ame polariy a he The 82 i deigned for microcompuer memory orage, and imple inerfacing are imporan I i direcly TTL compaible in-all repec oupu, and, low co, large bi A eparae chip enable (CE) lead allow eay elecion of an individual package when oupu are OR-ied. The Inel 82 i fabricaed wih N-channel ilicon gae echnology; allow he deign and producion of high performance, eay-o-ue MOS circui and provideahigher funcional deniy on a monolihic chip han eiher convenional MOS echnology or P-channel Inel' ilicon gae echnology alo provide excellen proecion again conaminaion. Thi permi he ue of low co ilicone packaging. PN CONFIGURATION LOGIC SYMBOL BLOCK DIAGRAM DATA OUT DATA IN GND DATA PIN NAMES DIM DATA INPUT ADDRESS INPUTS CE CHIP ENABLE DOUT DATA OUTPUT f/w READ/WRITE INPUT S Vcc POWER (+5V) Q'WIWUMKM

33 ^ FULLY DECODED RANDOM 96 BIT DYNAMIC Low Co Per Bi Low Sandby Power Typical 7 /iw/bi Eay Syem Inerface Only One High Volage Inpu Signal Chip Enable All Oher Inpu are TTL Compaible Addre Regier Incorporaed on he Chip Chip Selec Inpu Lead Fully Decoded On Chip Addre Decode Oupu I Three Sae arid Compaible wih Low Power TTL Gae Ceramic 22-Pin DIP The87A i a 96 word by bi dynamic RAM. I wa deigned for microcompuer memory applicaion where very low co and large bi orage are imporan deign objecive. The 87A ue dynamic circuiry which reduce he operaing and andby power diipaion.. Reading informaion from he memory i non-derucive. Refrehing i accomplihed by performing one read cycle on each of he 6 row addree. Each row addre mu be refrehed every one milliecond. The memory i refrehed wheher Chip Selec i a logic one or a logic zero. The 87A i fabricaed wih N-channel ilicon gae echnology. manufacure of device uing minimum ize ranior ha have he ame allow he deign and a device uing much larger ranior. PIN CONFIGURATION LOGIC SYMBOL BLOCK DIAGRAM AF A A ROW DECODE and BUFFER REGISTER MEMORY ARRAY 6x6 V CC MB CE TIMING CONTROL GENERATOR COLUMN AMPLIFIERS 6 I/O COLUMN DECODE and BUFFER REGISTER PIN NAMES v.. DATA INPUT CE CHIP ENABLE AFT-AII ADDRESS INPUTS DOUT DATA OUTPUT WRITE' ENABLE. YCC POWER <+5V) S CHIP SELECT NC NOT CONNECTED OMIT A. A, A, A, A W A)j

34 28 BIT READ Fully Decoded, 256 x 8 Inpu and Oupu TTL Compaible» Three-Sae Oupu OR-Tie Capabiliy ' "The Inel 82 i a fully decoded 256 word by 8 bi meal mak ROM. i i ideal for large volume producion run of microcompuer yem iniially uing he 872A eraable and elecrically programmable ROM. The 82 ha he ame pinning a he 872A. The 82 i enirely aic no clock are required. Inpu and oupu of The oupu i hree-ae for OR-ie capabiliy. A eparae The 82 i packaged in a 2 pin dual-in-line hermeically ealed ceramic package; are TTL compaible. eay memory expanion. ^ The 82 i fabricaed wih p-channel ilicon gae echnology. Thi low hrehold allow he deign and producion of higher performance MOS circui and provide a chip han convenional MOS echnologie. funcional deniy on a monolihic ni CONFIGURATION DIAGRAM MMfT DATA OUT 9 DATA OUT DATA OUT 2 DATA OUT DATA OUT DATA OUT 5 OATA OUT 6 DATA OUT 7 OATA OUT 8 AA A? PN NAMES A<r A7 Q DOvDOa ADDRESS INPUTS CHIP SELECT INPUT DATA OUTPUTS «

35 892 BIT STATIC MOS READ ONLY MEMORY Organizaion-2 Word x 8 Bi Fa Acce 5 n Maximum OR-Tie Direcly Compaible wih 88 CPU Maximum Proceor Speed Two Chip Selec Inpu for Eay Memory Expanion Direcly TTL Compaible All Inpu and Oupu i», On Chip Decode Inpu Proeced All Have Proecion Again Saic Charge The Inel 88 i an 8,92 bi aic MOS Read Only Memory organized a 2 word by 8 bi. Thi ROM i deigned for 88 microcompuer yem applicaion where high performance, large bi orage, and imple inerfacing are imporan deign objecive. The inpu and oupu are fully TTL compaible. _ ' \ The88 read only memory i fabricaed wih N-channel ilicon gae echnology. Thi echnology provide he deigner wih high performance, eay-o-ue MOS circui. PIN CONFIGURATION BLOCK DIAGRAM Vcc <+5V) FMOFTOIM DATA OUT 8 M> (+2V) 92 BIT ROM MATRIX (2X8) A \ > / VFEFOV) PIN NAMES AO-A Or CS,. CS 2 ADDRESS INPUTS DATA OUTPUTS CHIP SELECT INPUTS

36 6,8 BIT MOS READ ONLY MEMORY 28 Word x 8 Bi Single - 5 Vol Power Supply Volage OR-Tie and Oupu > Low Power Diipaion of.7 ju.w/bi Maximum Three Programmable Chip Selec inpu for Eay Memory Expanion Fully Decoded On Chip Addre Decode ' ' A. Inpu Proeced All Inpu Have Proecion Again Saic Charge The Inel 86 i a 6,8 bi aic MOS read only memory organized a 28 word by 8 bi. Thi ROM i deigned for microcompuer memory applicaion where high performance, large bi orage, and imple inerfacing are imporan deign objecive. ^ The inpu and oupu are fully TTL compaible. Thi device operae wih a ingle +5V power upply. The chip elec inpu are programmable. Any combinaion of acive high or low level chip elec inpu can be defined and he deired chip elec code i fixed during he making proce. Thee hree programmable chip elec inpu, a well a QR-ie compaibiliy on he oupu, faciliae eay memory expanion. The 86 read only memory i fabricaed wih N-channel ilicon gae echnology. Thi echnology provide he deigner wih high performance, eay-o-ue MOS circui. Only a ingle +5V power upply i needed and all device are direcly TTL compaible. BLOCK DIAGRAM

37 28 BIT AND READ MEMORY /» Ra Programming 2 Minue for 28 Bi Fully Decoded, 256 x 8 Organizaion ^ OR-Tie Saic MOS No Clock Required Simple Memory Expanion Chip i The 872A i a 256 word by 8 bi elecrically programmable ROM ideally uied for microcompuer yem developmen where fa urn-around and paern experimenaion are imporan. The 872A undergoe complee programming and funcional eing on each bi poiion prior o hipmen, hu inuring % programmabiliy. The872A i packaged in a 2 pin dual-in line package wih a ranparen quarz lid. The ranparen quarz Kd allow he uer o expoe he chip o ulraviole ligh o erae he bi paern. A new paern can hen be wrien ino he device. Thi procedure can be repeaed a many ime a required. The circuiry of he 872A i enirely aic; no clock are. required. yem ii for large volume The 872 producic chip han hrehold echnology allow he deign and deniy on a monolihic PIN CONFIGURATION BLOCK DIAGRAM OfXAOUT OATA OUT 8 DATA OUT DATA OUT 2 OATA OUT PROGRAM OATA OUT OATA OUT 5 OATA OUT 6 OATA OUT 7 OATA OUTS PROGRAM A A A? > THIS PIN IS THE DATA INPUT LfrAD DURING PROGRAMMING. PIN NAMES A-A7 ADDRESS INPUTS 5 CHIP SELECT INPUT D v D 2 DATA OUTPUTS 5

38 yii^u riun 96 BIT READ FuMf amended On Chip Addrm Syem Program Sorage < I. Decode andbuffer The 86 i a 52 x 8 elecrically programmable ROM ideally uied for high performance microcompuer yem where fa urnaround i imporan for yem program developmen and for mall volume of idenical program in producion yem. m PIN CONFIGURATION DIAGRAM DATA OUT QND PIN NAMES 8

39 ' V, f \ 96 BIT ERASABLE ; >>.. ->» f i REPROGRAMMABLE READ ONLY MEMORY / Fa Programming wih Volage Pule per Bi Compaible Low Power During Programming Fully Decoded, 52x8 Organizaion OR-Tie li 5 n Thc 87 i a high peed 52 word by 8 bi elecrically programmable ROM i uied for microcompu- er yem developmen where fa acce and low power are required. The87 i packaged in a 2 pin dual-in-line package wirranparen quarz lid. The ranparen uer o expoe he chip o ulraviole ligh o erae new paern ino PN CONFIGURATION BLOCK DIAGRAM DATA OUT DATA OUTS moanam % PROGRAM A«A A PIN NAMES Ao-A c ADDRESS INPUTS OrO. R/W S DATA OUTPUTS READ/WRITE CHIP SELECT INPUTS 7

40 HIGHSPEED DECODER I/O Por or Memory Selecor.25 ma Enable inpu Technology Direcly Compaible wih TTL Logic Circui min. Ceramic or The 825 decoder can be ued for expanion of yem which uilize inpu por, oupu por, and memory componen wih acive low chip elec inpu. When he 825 i enabled, one of i eigh oupu goe "ow", hu a ingle row of a memory yem i eleced. The chip enable inpu on he 825 allow eay yem expanion. For very large yem, 825 decoder can be cacaded uch ha each decoder can drive eigh oher decoder for arbirary memory expanion. The Inel 825 i packaged in a andard 6 pin dual-in-line package; and i performance i pecified over he emperaure range of C o +75 C, ambien. The ue of Schoky barrier diode clamped ranior o obain fa wiching peed reul in higher performance han equivalen device made wih a gold diffuion Droce. PIN CONFIGURATION LOGIC SYMBOL i 2 E, -la -J A o, Oi O, Ej 26 9m E olii 7 GRD o E2 o< 6 7 A - AJ r I) PIN NAMES AOORESS INPUTS ENABLE INPUTS DECODED OUTPUTS ADDRESS ENABLE OUTPUTS A# A Aj E, L L L L L H L H H H H H H H H L L L L H H L H H H H H H L H L L L M H H L H H H H H H H L L L M H H H L H H H H L L H L L H H H H H L H H H H ' L H L L H. H H H H H L H M L H M L L H M H H H H H L H H H H L L H H H H H H H M L X X X L L L H H H H H H H H X X X H L L H H H H H H H H X X X L H H H H H H H H M X X X H H I H H H M H M H H X X X H L H H H H H H H H H X X X L H H H H H H H H H H X X X H H H H H H H H M H H 8

41 r Schoky Bipolar 82 TTL-TO-MOS LEVEL SHIFTER AND HIGH VOLTAGE CLOCK DRIVER Four Low Volage Driver One High Volage Driver «TTL and DTL m Oupu Compaible wih f7a MOS Memorie Operae from Sandard Bipolar and MOB PowerSuppiie# Maximum MOS Device Proecion Oupu Clamp Diode The Inel 82 i a Bipolar-o-MOS level hifer and High volage driver which accep TTL and DTL inpu. I conain four () low volage driver and one high volage driver, each wih curren driving capabiliie uiable for driving N-channel MOS memory device. The 82 i paricularly uiable for driving he 87 A N-channel MOS memory chip. The 82 operae from he 5 vol and 2 vel power upplie ued o bia he memory device. The four low volage driver feaure wo common enable inpu per pair of driver? which permi addre or decoding. The high volage driver wing h 2 vol required o drive he chip enable (clock) inpu #orhe87a. I The 82 high volage driver require an exernally conneced PNP ranior. The PNP bae i conneced o pin 2, he collecor o pin, and he emier o pin or VDQ The U!Of fai wiching, high vol-, high curren gain PNP, like he 2N577 i recommended. X. 99

42 S^BRR INPUT/OUTPUT j» Fully Parallel 8-Bi Daa Regier or Buffer Lew Inpu Load Curren.25 ma Max. Three Sae Oupu Oupu Sink 5 ma.5v Oupu High Volage for Direc Inerface o 88 CPU 9 Replace Buffer, Lache and Muliplexer in Syem Reduce Syem Package Coun Aynchronou Regier Clear I I / f The822 i a muli-mode ach/buffer device deigned for ue in microcompuer yem. i The device coni of an 8-bi lach wih ri-ae oupu buffer, along wih conrol logic, and a ervice reque flip-flop. AH of he principal peripheral and inpu/oupu-funcion of a microcompuer yem can be implemened wih hi device. i «$ PIN CONFIGURATION BLOCK DIAGRAM REO \ F F OOl oo» CONTROL LOGIC OO 7 DO, DO, OO «TRISTATE BUFFER DO oo DPS DO«oo 5 DO 7 ACK DO, GNO FUNCTIONAL LOGIC DESCRIPTION y ACKNOWLEDGE DIvDI OOv DSi OS 2 MO ACK ST PIN NAMES DATA IN DATA OUT DEVICE SELECT MODE (CLK) STATUS F-F CLEAA (ACTIVE LOW) WR (Wrie Enable) EN (Oupu EnaM) S (SR Flip-Flop Se) R (SR Flip-Flop Reaa) ST (Sau Ou) CR (Clear) HT, OS 2 MO + ACK (Daa i lached afer WR i removed) DS ' OS2 MO MO b, DS2 (Aynchronou. Se override Reell ACK (Synchronou, negaive edge riggered) Ogg S (Oupu inhibied during Se, when e by DSj and OS only) Reaa all lache o "" and e»s.r. Flip-Flop o ""

43 inel Bipolar 826 BIT PARALLEL BIDIRECTIONAL BUS DRIVER Daa Bu Buffer Driver for 88 CPU Low Inpu Load Curren.25 ma Maximum High Oupu Drive Capabiliy for Driving Syem Daa Bu.5V Oupu High Volage for Direc Inerface o 88 CPU Three Sae Oupu Reduce Syem Package Coun The 826 i a -bi bi-direcional bu driver/receiver. All Inpu are low power TTL compaible. For driving MOS, he O oupu provide VOH (.5V), and for high capaciance erminaed bu rucure, he I/O oupu, provide a higher IQL (25 ma) capabiliy. PIN CONFIGURATION LOGIC DIAGRAM S Oo Ol/Oo l/oo > o, Ol/O l/o h GND O I/O 2 ol/o o c

44 : Silicon ^ f UNIVERSAL COM ' maji jfciiii oiiiimfci yncnronou ana A y ncn TO nou jjj Baud Rae -DC o 5 k Baud Operaion Synchronou; 5-f Bi Characer Inernal or Exerna] Characer Synchronizaion Auomaic Sync Inerion/Deleion Aynchronou: 58 Bi Characer Clock Rale 6, 2 or 6 Time Baud Rae Break Characer Generaion, %, or 2 Sop Bi Bi Deecion Fun Duplex,. Double Buffered, m Pariy, 9 Overrun, Overflow, and Framing» Fully Compaible wih 88 CPU AH Inpu and Oupu Are TTL Compaible Single $ Vol Supply The 82 i a univeral communicaion inerface device ued for daa communicaion in 88 microproceyem. Thi device i ued a an 88 peripheral device and can be programmed by he 88 o opuing virually any erial daa ranmiion echnique preenly in I accep daa characer from he 88 in parallel forma and hen conver hem ino a coninuou erial daa ream for ranmiion. Simulaneouly, i can receive erial daa ream and conver hem ino parallel daa characer for he 88. Thi communicaion inerface will inerrup he 88 wherever i can accep a new characer for ranmiion, or whenever i ha received a characer for he 88. In addiion, i will alo inerrup he 88 if any ranmiion error occur (i.e., pariy error, framing error, overrun error or underrun error). i V, 9 Pin Name Pin Funcion Daa Bu (8 bi) C/D READ WRITE Conrol or Daa i o be Wrien or Read Daa Command Wrie Daa or Conrol Command Chip Enable Clock Pule (TTL) Ree TxC TxD RxC RxD RxRDY TxRDY Tranmier Clock»,» Tranmier Daa Receiver Clock Receiver Daa Receiver Ready (ha characer for 88) Tranmier Ready (ready for char, from 88) Pariy Error Overrun Error FE/SYNC Framing Error (Ayn Mode) Sync Deec (Sync Mode) > V RTS CTS TxE Reque o Send Daa Clear o Send Daa Tranmier Empy +5 Vol Supply Ground 2

45 APPENDIX VII LIBRARY PL/M Compiler A High Level Syem Language 'I' eay o program he MCS-8 Microcompuer nmg PL/M, a new high level language concep developed o mee he pecial need of microcompuer yem programming. Programmer can now uilize a rue high level language o efficienly program microcompuer. PL/M i an aembly language replacemen ha can fully command he 88 CPU and fuure proceor o produce efficien run-ime objec code. PL/M wa deigned o provide addiional developmenal ofware uppor for he MCS-8 microcompuer yem, permiing he programmer o concenrae more on hi problem and le on he acual ak of programming han i poible wih aembly language. Programming ime and co are draically reduced, and raining, documenaion and program mainenance are implified. Uer applicaion program and andard yem program may be ranferred o fuure compuer yem ha uppor PL/M wih lile or no reprogramming. Thee are advanage of high-level language programming ha have been proven in he large compuer field and are now available o he microcompuer uer. PL/M i derived from IBM' PL/I, a very exenive and ophiicaed language which promie o become he mo widely known and ued language in he near fuure. PL/M i a ube of PL/ wih emphai on hoe feaure ha accuraely reflec he naure of yem programming requiremen. PL/M IS AN EFFICIENT LANGUAGE Te on ample program indicae ha a PL/M pro- gram can be wrien in le han % of he ime i ake o wrie he ame program in aembly Ianguage wih lile efficiency lo. The main reaon for hi aving in ime i he fac ha PL/M allow he programmer o define hi problem in erm naural o him, no in he compuer' erm. Conider he following ample program which elec he large of wo number. In PL/M, he programmer migh wrie: If A > B, hen C = A; ele C B; Meaning: "If variable A i greaer han Variable B, hen aign A o Variable C; oherwie, aign B o C " A correponding program in aembly language i welve eparae machine inrucion, and convey lile of original inen of he program. Becaue of he and conciene wih which program can be wrien and he error free ranlaion ino machine language achieved by he compiler, he ime o program a given yem i reduced over aembly language. Debug and checkou ime of a PL/M program i alo much le han ha of an aembly language program, parly becaue of he inheren clariy of PL/M, bu alo becaue wriing a program in PL/M encourage good programming echnique. Furhermore, he of he PL/M language enable he PL/M compiler o deec error condiion ha would lip by an aembler. The PL/M compiler i wrien in Sandard FORTRAN IV and will execue on mo large machinewih lile aleraion. «$ % /

46 MCS-8 Cro Aembler Sofware, I, P8CXO6 9 The MCS-8 cro aembler ranlae a ymbolic ^preenaion of he inrucion and daa ino a,orm which can be loaded and execued by he MCS-8. By cro aembler, we mean an aembler execuing on a machine oher han he MCS-8 which generae code for he MCS-8. Iniial developmen ime can be ignificanly reduced by aking advanage of a large cale compuer' proceing, ediing and high peed peripheral capabiliy. Program are wrien in he aembly language uing mnemonic ymbol boh for 88 inrucion and for pecial aembler operaion. Symbolic adree can be ued in he ource program; however, he aembled program will ue abolue addre. The Aembler, deigned o operae ineracively from a erminal, i wrien in andard FORTRAN IV and can be modified o run on mo large cale machine. MCS-8 Simulaor Sofware Package The MCS-8 Simulaor i a compuer program wrien in FORTRAN IV language and called INTERP/8 TM program provide a ofware imulaion of he rie 88 CPU, along wih execuion monioring» command o aid program developmen for he MCS-8. INTERP/8 accep machine code produced by he 88 Aembler, along wih execuion command from a ime haring erminal, card reader, or dik file. The execuion command allow manipulaion of he imulaed MCS-8 memory and he 88 CPU regier. In addiion,operand and inrucion breakpoin may be e o op execuion a crucial poin in he program. Tracing feaure are aio available which allow he CPU operaion o be moniored. INTERP/8 alo accep ymbol able from eiher he PL/M compiler or MCS-8 cro aembler o allow debugging, racing and braking, and diplaying of program uing ymbolic name. The PL/M compiler, MCS-8 aembler and MCS-8 imulaor ofware package may be procured from Inel on magneic ape, or alernaively, from naionwide Compuer ime haring ervice. Conac Inel for deail.,

47 # «APPENDIX VIII MCS-8 DEVELOPMENT SYSTEMS nehec 8 Wih 88 CPU SPECIFICATIONS FEATURES Ideal for developing MCS-8 yem. The Inellec 8 microcompuer yem hafok bye of memory (expandable o 6K, I/O, TTY Inerface, andard ofware, conrol panel, power upplie, and a compac finihed cabine (le han.8 f. ). The hear of he Inellec 8 i Inel' eigh-bi "compuer-on-a-chip," he 88. Thi i an 8-bi parallel CPU wih a reperoire of 78 inrucion, even working regier, ack archiecure, inerrup capabiliy, and i direcly addree 6K bye of memory. Direc acce o memory via conrol conole. Sandard ofware provided wih he Inellec 8 include a yem monior (loader, hex memory dump, inrucion edior), a reiden aembler, and a ex edior. Wih hi yem, all program developmen may be done in RAM memory. A complee PROM programmer i provided. Afer he program i firm, i may be commied o nonvolaile orage in Inel' 72A programmable and eraable Read-Only-Memory. Complee yem conrol and hardware debugging aid are provided via he conrol panel. Cryal clock are ued for yem abiliy. Syem i expandable o 6 microcompuer module in a ingle chai. < Word Size: Memory Size: inrucion Se: ^ \ ' i Daa: 8 bi Inrucion: 8,6, or 2 bi 8K RAM, 2K ROM bye expandable o 6K bye 78, including: condiional branching, decimal binary arihmeic, logical, regiero-regier and memory reference operaion Machine Cycle Time: 2/ - # Syem Clock: I/O Channel: Cryal conrolled expandable o 8 inpu por expandable o 2 oupu por _ Inerrup: Single level Direc Memory Acce: Sandard via he conrol panel Operaing Temperaure: C o 55 C Power Supplie +5V ± 5% 9V ±5 /< Phyical Size: ' Weigh: Sandard Sofware: Suppor Sofware «' + > A < TTL Compaible 2 amp.8 amp 'Larger power upplie may be. required for expanded yem inellec 8:7"x7y e "x2'/ " (able op only) b. Syem Monior Reiden Aembler Tex Edior PL/M Compiler " wrien Cro Aembler - JT orran Simulaor J iv 6

48 HCfELLBC 8 (imnrs-6). Sandard Syem include he following module: Cenral Proceor Module wih 88 CPU Inpu/Oupu Module «PHOM Memory Module Two RAM Memory Module PROM Programmer Module Chai wih Moher Board Power Supplie Conrol and Diplay Panel Finihed Cabine V. Loaded o yem via paper ape. program during program devel-. - <. AS andsimulaor available wih cro aembler, and imulaor FORTRAN cale compuer conac from in Sandard Sofware > ' ' Syem Monior Reiden Aembler Tex Edior OPTIONAL MODULES available for he Inellec 8:» Addiional I/O or Oupu Module Addiional RAM Memory Module Univeral Prooype Module PL/M COMPILER. PL/M i a high level procedureoriened yem language for programming he Inel MCS-8 microcompuer. The language conain he feaure of a high-level language, wihou acrificing he efficiencie of aembly language.» A ignifican advanage of hi language i ha PL/M program can be compiled for eiher he Inel Module Exender 8Q8or88. Drawer Slide and Exender for Rack Mouning Sofware STANDARD. AH peripheral inerface o Inellec 8 andard ofware i via TTY, model ASR. The andard ofware include a Syem Monior, Reiden'Aembler and Tex Edior. A. Monior. Conained in eigh 72A PROM locaed on he PROM memory module. 2. Program aigned o upper 2K bye of memory. '» ASSEMBLER. The MCS-8 Aembler generae Objec code from ymbolic aembly language inrucion. I i deigned o operae on a large cale compuer wih inpu by paper ape, direcly from a erminal, or % SIMULATOR. The MCS-8 Simulaor, called IN- TERP/8, provide a ofware imulaion of he Inel 88 CPU, along wih execuion monioring command o aid program developmen for he MCS-8.. Remaining K of memory may hen be ued for eiher program or daa orage.. Inellec 8 modular compuer yem have a conrol program called a Reiden Monior in PROM o ha no "boorap" operaion need ever be performed. The monior funcion are a follow: a. Load RAM memory from paper ape, eiher in BNPF forma or hexadecimal forma. b. Diplay he conen of RAM memory on a priner. c. Modify Individual bye of RAM memory, move block of RAM memory, fill block of RAM memory wih conan daa. d. Wrie conen of RAM memory o paper ape in eiher BNPF or hexadecimal forma. B. Reiden Aembler v i Microcompuer Module Decripion. All module are 8" wide, 6.8" high and ue andard -pin conimm8-8 Cenral Proceor Module, Inel' 88 eigh-bi parallel ingle chip CPU n-channel ilicon gae MOS. Accumulaor and ix 8-bi working regier. Unlimied ubrouine neing. Inerface o 6K 8-bi bye of PROM, ROM, or RAM via he PROM Memory Module and RAM Memory Module.. Tranlae he mnemonic code o binary machine Inerface for expanion o bi inpu code. por and bi oupu por, via he 2. Loaded Ino yem RAM memory via paper ape.. 8K of memory orage i required for boh he reiden aembler and he ymbol able.. hree pa aembler generae program ape I/O and Oupu Module. Inerrup capabiliy. Two phae cryal clock. All module inerface are TTL compa- 9 < 6